TWM529274U - Normally-off cascode high electron mobility transistor - Google Patents

Abstract

This utility model provides a normally-off cascade high electron mobility transistor, comprising a substrate; a buffer layer formed on the substrate; a depletion mode high electron mobility transistor formed on the buffer layer; a first passivation layer overlaying the depletion mode high electron mobility transistor and the buffer layer; and a first thin film transistor formed on the first passivation layer, wherein the depletion mode high electron mobility transistor is electrically connected with the thin film transistor in serial to form a cascade structure.

Description

Normally closed type high electron mobility transistor

The present invention relates to a High Electron Mobility Transistor (HEMT), and more particularly to a normally closed Cascode high electron mobility transistor.

High electron mobility transistor (HEMT) generally consists of a heterostructure formed by two materials of different energy gap widths. This heterostructure produces a two-dimensional electron gas (2DEG) at the junction, resulting in two dimensions. Electron gas can act as a channel to conduct current. Since high electron mobility transistors have high-speed electron mobility characteristics, high electron mobility transistors can be applied to high-power, high-frequency, and high-temperature operation electronic components by appropriately selecting the materials used. High electron mobility transistors can be classified into two types: enhanced (E-mode) and depleted (D-mode) according to their on-voltage, wherein the depletion-type high electron mobility transistor is normally on (normally on) The device, compared to the enhanced high electron mobility transistor, the depletion high electron mobility transistor is in an on state even when the gate voltage is 0V, so it is energy consuming.

The present invention is characterized in that a normally closed splicing type high electron mobility transistor comprises: a substrate; a buffer layer formed on the substrate; and a depletion type high electron mobility transistor formed on the buffer layer; a first protective layer covering the depletion type high electron mobility transistor and the buffer layer; and a first thin film transistor formed on the first protective layer, and the depletion type high electron mobility transistor and the first film The transistors are stacked.

Another feature of the present invention is to provide a normally-off splicing type high electron mobility transistor as described above, wherein the above-described depletion type high electron mobility transistor comprises: a first channel layer having a first An energy gap is formed on the buffer layer; a barrier layer has a second energy gap formed on the first channel layer, wherein the second energy gap is greater than the first energy gap; and a first gate and a first source a first drain is formed on the barrier layer, and the first source and the first drain are respectively located on opposite sides of the first gate.

Another feature of the present invention is to provide a normally closed splicing type high electron mobility transistor as described above, wherein the first thin film transistor comprises: a second gate formed on the first protective layer; a second protective layer covering the second gate and the first protective layer; a second channel layer formed on the second protective layer, and the pair is located at the second gate; and a second source and a first The second thin film transistor is formed on the second channel layer at intervals. The first thin film transistor includes a first through hole and a second through hole, and the first through hole and the second through hole are located at the second gate. a first source and a first gate are respectively exposed through the first protective layer, the second drain is electrically connected to the first source via the first through hole, and the second source is connected to the first source via the second through hole The first gate is electrically connected.

Another feature of the present invention is to provide a normally-off splicing type high electron mobility transistor as described above, wherein the first through hole and the second through hole respectively penetrate the second protective layer.

Another feature of the present invention is to provide a normally-off spliced high electron mobility transistor as described above, wherein the first channel layer comprises a gallium nitride layer, and the barrier layer comprises an aluminum gallium nitride layer.

Another feature of the present invention is to provide a normally-off spliced type high electron mobility transistor as described above, wherein the first channel layer comprises an amorphous germanium layer, a hydrogenated amorphous germanium layer or a low temperature polycrystalline germanium layer.

Another feature of the present invention is to provide a normally-off spliced type high electron mobility transistor as described above, wherein the first protective layer comprises a ruthenium oxide layer or a tantalum nitride layer.

Another feature of the present invention is to provide a normally-off spliced type high electron mobility transistor as described above, wherein the second protective layer comprises a ruthenium oxide layer or a tantalum nitride layer.

Another feature of the present invention is to provide a normally-off spliced high electron mobility transistor as described above, wherein the buffer layer comprises a gallium nitride layer containing a carbon dopant.

Another feature of the present invention is to provide a normally-off splicing type high electron mobility transistor as described above, wherein the substrate comprises a sapphire substrate, a gallium nitride substrate, a germanium substrate or a tantalum carbide substrate.

Another feature of the present invention is to provide a normally-off spliced high electron mobility transistor as described above, further comprising a dielectric layer disposed between the first gate and the barrier layer.

Another feature of the present invention is to provide a normally-off spliced type high electron mobility transistor as described above, wherein the second source and the channel layer are between the second drain and the first channel layer There is further included a first ohmic contact layer.

Another feature of the present invention is to provide a normally-off spliced type high electron mobility transistor as described above, wherein the first ohmic contact layer comprises an amorphous germanium layer doped with an n-type impurity.

Another feature of the present invention is to provide a normally-off spliced type high electron mobility transistor as described above, further comprising a third protective layer covering the first thin film transistor and the second protective layer, and the above A second thin film transistor connected in parallel with the first thin film transistor is formed on the third protective layer.

Another feature of the present invention is to provide a normally-off splicing type high electron mobility transistor as described above, wherein the second thin film transistor comprises: a third gate formed on the third protective layer; a fourth protective layer covering the third gate and the third protective layer; a third channel layer formed on the fourth protective layer and opposite to the second gate; and a third source and a third The second thin film transistor further includes a third through hole and a fourth through hole, and the third through hole and the fourth through hole are located at the third gate. a third through-hole, and a second drain is exposed and the second source is exposed, the third drain is electrically connected to the second drain through the third through hole, and the third source is connected through the fourth through The hole is electrically connected to the second source.

Another feature of the present invention is to provide a normally-off splicing type high electron mobility transistor as described above, wherein the third through hole and the fourth through hole respectively penetrate the fourth protective layer

Another feature of the present invention is to provide a normally-off spliced high electron mobility transistor as described above, wherein the second channel layer comprises an amorphous germanium layer, a hydrogenated amorphous germanium layer or a low temperature polysilicon layer.

Another feature of the present invention is to provide a normally-off spliced high electron mobility transistor as described above, wherein the third protective layer and/or the fourth protective layer comprise a yttrium oxide or tantalum nitride layer.

Another feature of the present invention is to provide a normally-off spliced high electron mobility transistor as described above, further comprising a dielectric layer disposed between the first gate and the barrier layer.

Another feature of the present invention is to provide a normally-off spliced type high electron mobility transistor as described above, wherein the dielectric layer comprises tantalum nitride, hafnium oxide, hafnium oxynitride or aluminum oxide.

Another feature of the present invention is to provide a normally-off spliced high electron mobility transistor as described above, between the third source and third channel layers and the third and third channel layers There is further included a second ohmic contact layer.

Another feature of the present invention is to provide a normally-off spliced type high electron mobility transistor as described above, wherein the second ohmic contact layer comprises an amorphous germanium layer doped with an n-type impurity.

First, please refer to FIGS. 1A-1B, which illustrate an equivalent circuit of a normally-off spliced high electron mobility transistor 1000 according to an embodiment of the present invention. In the present embodiment, the spliced high electron mobility transistor 1000 includes a depletion type high electron mobility transistor (D-mode HEMT) 20' and a thin film transistor (TFT) 30'. Wherein, a thin film transistor (TFT) 30' serves as a switch for controlling the depletion type high electron mobility transistor 20', and is overlapped with the depletion type high electron mobility transistor 20' to form a stacked high electron mobility transistor 1000. . As shown in FIGS. 1A to 1B, the depletion type high electron mobility transistor 20' is connected in series with the drain D2 of the thin film transistor 30' by its source S1, and the gate of the depletion type high electron mobility transistor 20'. The pole G1 is electrically connected to the source S2 of the thin film transistor 30', so that the V _{D2S2 of the} thin film transistor 30' is equal to -V _{G1S1 of the} depletion type high electron mobility transistor 20', and the depletion type is high due to the grounding relationship. The equivalent voltage of the electron mobility transistor 20'V _G1S2 is 0V.

Referring to FIG. 1A, FIG. 1A shows an equivalent circuit in which the stacked high electron mobility transistor 1000 is in an off state. As shown in FIG. 1A, when the gate voltage V _{G2 of the} thin film transistor 30 ′ is smaller than the threshold value V _{th — TFT} , no channel is generated between the source S 2 and the drain D 2 of the thin film transistor 30 ′, and the thin film transistor 30 is formed. 'Closed, the spliced high electron mobility transistor 1000 is in a non-conducting state. Since the thin film transistor 30' is connected in series with the depletion type high electron mobility transistor 20', even when a higher voltage is applied to the drain D1 of the depletion type high electron mobility transistor 20', the depletion type high electron mobility is The crystal 20' can still withstand without being short-circuited and can serve as a protective element for the spliced high electron mobility transistor 1000. Specifically, in the present embodiment, in the case where the thin film transistor 30' is turned off, when a higher voltage (not reaching a breakdown voltage) is applied to the drain D1 of the depletion type high electron mobility transistor 20' ( For example, 600V), the conductive energy band of the depletion type high electron mobility transistor 20' under the gate G1 will be raised and higher than the Fermi level, and there is no two-dimensional electron gas under the gate G1. The depletion-type high electron mobility transistor 20' is in a closed state, so that the depletion-type high electron mobility transistor 20' blocks current from directly penetrating the thin film transistor 30'.

Please refer to FIG. 1B. FIG. 1B shows the stacked high electron mobility transistor 1000 in an on state. As shown in FIG. 1B, when the gate voltage V _{G2 of the} thin film transistor 30' is greater than or equal to its V _{th — TFT} , a channel is formed between the source S2 of the thin film transistor 30 ′ and the drain D 2 , and the thin film transistor 30 ′ is Turning on, at this time, when the drain input voltage V _D1 of the depletion type high electron mobility transistor 20' is within a certain operating range, (in this embodiment, 20V is taken as an example), the depletion type high electron mobility transistor The conductive energy band under 20' gate G1 will be lower than the Fermi energy level. At this time, there is a two-dimensional electron gas under the gate G1, and the depletion high electron mobility transistor 20' is in an open state, so the splicing The high electron mobility transistor 1000 is in an on state.

FIG. 1C is a top perspective view of a package 150' encapsulating a stacked high electron mobility transistor 1000 as illustrated in FIGS. 1A-1B. As shown in FIG. 1C, the package 150' includes a substrate 15', and the substrate 15' is provided with a stacked high electron mobility transistor 1000, which comprises a depletion type high electron mobility transistor 20' and A thin film transistor 30' overlying the depletion-type high electron mobility transistor 20' and intercalating with the depletion-type high electron mobility transistor 20', wherein the depletion-type high electron mobility is below the thin film transistor 30' The transistor 20' has a source S1 (not shown) connected in series with the drain D2 of the thin film transistor 30', and its gate G1 (not shown) and the source S2 of the thin film transistor 30' are electrically connected. Connected to form a spliced high electron mobility transistor 1000 of a common source. In addition, the substrate 15' further includes a source pin 40', a gate pin 50' and a drain pin 60'. The source S2 of the thin film transistor 30' is provided by the wire 45' and the source. The pin 40' is electrically connected, and the drain S1 of the depletion high electron mobility transistor 20' is electrically connected to the drain pin 60' via the wire 65', and the gate G2 of the thin film transistor 30' is connected by the wire 55' is electrically connected to the gate pin 50'.

In summary, the normally closed splicing type high electron mobility transistor disclosed in the present invention utilizes a thin film transistor that controls a depletion type high electron mobility transistor switch to be integrated into a depletion type high electron mobility transistor. Above, and by the splicing structure, the normally-opening type of high-electron mobility transistor is converted into a normally-closed type high electron mobility transistor, so that it is not necessary to purchase an additional transistor as a control switch. Significantly reduce the cost, and because the size of the package can be reduced by more than half, it can meet the current requirements for component size reduction.

The manner in which the novel embodiments are made and used will be described in detail below. It should be noted, however, that the present invention provides many new concepts that can be applied, which can be implemented in a variety of specific forms. The specific embodiments discussed herein are merely illustrative of specific ways to make and use the present invention and are not intended to limit the scope of the invention. Embodiment 1:

The cross-sectional process of the normally-off spliced high electron mobility transistor 1000 according to the first embodiment of the present invention will be described below in conjunction with the cross-sectional process of FIGS. 2A-2D.

First, referring to FIG. 2A, a semiconductor substrate 200 is first provided, then a buffer layer 210 is deposited on the semiconductor substrate 200, and then a first channel layer 220 and a barrier layer 230 are sequentially deposited on the buffer layer 210. . The semiconductor substrate 200 can be a conductive substrate or an insulating substrate. The material of the conductive substrate can be selected from the group consisting of germanium, tantalum carbide or gallium nitride. The material of the insulating substrate can be selected from sapphire. The material of the buffer layer 210 can be III-V. The material is, for example, aluminum nitride (AlN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), or carbon-doped gallium nitride, etc., which serves to reduce lattice mismatch with the substrate. Lattice defects of the first channel layer 220 and the barrier layer 230. In this embodiment, the first channel layer 220 has a thickness ranging from 50 to 300 nm, is formed on the buffer layer 30, and has a first energy gap. The first channel layer 220 may be an intentionally doped layer (for example, an n-type doped layer) or an intrinsic semiconductor layer, and the material thereof may include indium gallium nitride (In _x Ga _(1-x) N), 0≦x<1 For example, a gallium nitride layer. The barrier layer 230 has a thickness ranging from 20 to 50 nm and has a second energy gap. Generally, the second energy gap is higher than the first energy gap, that is, the lattice constant of the barrier layer 230 is smaller than that of the first channel layer 220. The barrier layer 230 may be an intentionally doped layer or an intrinsic semiconductor layer, and the material thereof may include Al _y In _z Ga _(1-z) N, 0<y<1, 0≦z<1, For example, an aluminum gallium nitride layer. The first channel layer interacts with the spontaneous polarization of the first channel layer 220 and the barrier layer 230, and the piezoelectric polarization caused by lattice mismatch between each other. A portion of the band 220 near the surface of the barrier layer 230 will fall under the Fermi level, thereby generating a two-dimensional electron gas.

After the barrier layer 230 is formed, a first gate G1 and a first source S1 and a first drain D1 are formed on the barrier layer 230 by using a plating or metal sputtering process and a photolithography process. The preparation of the depletion type high electron mobility transistor 20', wherein the first source S1 and the first drain D1 are respectively located on both sides of the first gate G1. In this embodiment, the first gate G1, the first source S1 and the first drain D1 may be composed of a material containing aluminum or aluminum alloy. Then, a first protective layer 250 having a thickness greater than 7000 angstroms is deposited by chemical vapor deposition (CVD) or molecular-beam epitaxy (MBE) to cover the first gate G1 and a first source. S1 and a first drain D1 and the remaining exposed barrier layer 230 are on the surface. In this embodiment, the first protective layer 250 may be a hafnium oxide layer or a tantalum nitride layer.

Next, referring to FIG. 2B, a second gate G2 is formed on the first protective layer 250 by electroplating or metal sputtering and a photolithography process. In the present embodiment, the second gate G2 may be composed of refractory metals such as nickel, platinum, tungsten, molybdenum or the like or alloys thereof.

Next, referring to FIG. 2C, a second protective layer 270 is first deposited by chemical vapor deposition or molecular beam epitaxy to cover the second gate G2 and the remaining bare first protective layer 250. In this embodiment, the second protective layer 270 may be a hafnium oxide layer or a tantalum nitride layer. Then, the second channel layer 280 is formed on the second gate layer 280 corresponding to the second gate layer G2 by the chemical vapor deposition method or the molecular beam epitaxing method and the photolithography etching process. The material of the second channel layer 280 may be composed of amorphous germanium (a-Si), hydrogenated amorphous germanium (a-Si:H) or low temperature polycrystalline germanium. After the second channel layer 280 is formed, a portion of the second gate G2 is exposed as a region after the wire bonding, as needed, by lithography or the like.

Finally, referring to FIG. 2D, the second source S2 and the second drain D2 spaced apart from each other are formed on the second channel layer 280, thereby completing the preparation of the first thin film transistor 30. When the second source S2 and the second drain D2 are formed, the second protective layer 270 and the first protective layer 250 are first etched by the lithography process to form two sides of the second gate 260 and exposed first. The source S1 and the first and second through holes 285 and 286 of the first drain D1. Next, metal is deposited in the first and second through holes 285, 286 and a portion of the second channel layer 280 by electroplating or metal sputtering to form the second source S2 and the second drain D2. In other words, a portion of the second source S2 and the second drain D2 are located in the first and second through holes 285, 286, and the other portions of the second source S2 and the second drain D2 are located in the second channel layer 280. Above. The second source S2 and the second drain D2 in this embodiment may be composed of a composite metal layer such as titanium/aluminum/titanium/gold or titanium/aluminum/nickel/gold, and a part of the second drain D2 is located at the a through hole is electrically connected to the first source S1 exposed by the first through hole 285; a part of the second source S2 is located in the second through hole 286, and is connected to the second through hole 286 The exposed first gate G1 is electrically connected such that the depletion-type high electron mobility transistor 20' is overlapped with the first thin film transistor 30' to form a normally-off spliced high electron mobility transistor 1000. The normally-off splicing type high electron mobility transistor 1000 can be packaged into a package body 150' as shown in FIG. 1C by using a package wire-bonding process. For details, please refer to the foregoing. Embodiment 2:

Due to the depletion-type high electron mobility transistor, its characteristics are closely related to its voltage collapse mechanism and gate leakage current. Therefore, if the gate leakage current can be effectively suppressed, it will improve its potential to remain normally open when the gate voltage is 0V. Shortcomings.

Therefore, according to the normally closed splicing type high electron mobility transistor 1000 obtained in the first embodiment, the first gate G1 of the depletion type high electron mobility transistor 20' can be further as shown in FIG. A dielectric layer 290 having a thickness of about 20 to 30 nm is formed between the barrier layer 230 exposed between the first drain D1 and the first source S1 to complete a better depletion type high electron mobility. The transistor 20", and the depletion-type high electron mobility transistor 20" is overlapped with the first thin film transistor 30' to form a normally-off splicing type high electron mobility transistor 1000 as shown in FIG. '. Embodiment 3:

According to the normally closed splicing type high electron mobility transistor 1000 ′ obtained in the second embodiment, a first ohmic contact layer 295 is formed on the second drain D2 and the second source as shown in FIG. 4 . Between the pole S2 and the second channel layer 280, a more effective first thin film transistor 30" is completed, wherein the first ohmic contact layer 295 in this embodiment is an amorphous germanium layer doped with an n-type impurity. The first thin film transistor 30" is overlapped with the depletion type high electron mobility transistor 20" to form a normally off type high electron mobility transistor 1000" as shown in Fig. 4. Embodiment 4:

According to the normally closed splicing type high electron mobility transistor 1000 obtained in the first embodiment, a second thin film transistor 300 is further formed on the first thin film transistor 30' as shown in FIG. And in parallel with the first thin film transistor 30', the on-resistance R _{on is} lowered to increase the current I _D .

As shown in FIG. 5, the second thin film transistor 300 is over the first thin film transistor 30' and is isolated by a third protective layer 350. The second thin film transistor 300 includes a third gate G3 formed on the third protective layer 350, and a fourth protective layer 370 covering the third gate G3 and the remaining bare third protective layer 350. The third channel layer 380 is formed on the fourth protection layer 370 on the third gate G3, and a third source S3 and a third drain D3 are formed on the third channel layer 380 at intervals. The third protective layer 350 in this embodiment is a ruthenium oxide layer; the fourth protective layer is a tantalum nitride layer; and the third gate electrode may be composed of refractory metals such as nickel, platinum, tungsten, molybdenum or alloys thereof. The third source S3 and the third drain D3 may be composed of a composite metal layer such as titanium/aluminum/titanium/gold or titanium/aluminum/nickel/gold; the material of the third channel layer 380 may be amorphous (a-) Si), hydrogenated amorphous germanium (a-Si: H) or low temperature polycrystalline germanium.

In addition, the third gate G3 further includes a third through hole 385 extending through the fourth protective layer 370 and a portion of the third protective layer 350 and exposing the second drain D2, and a second bare source S2. Four through holes 386. The third drain D3 is located in the third through hole 385 and is electrically connected to the second drain D2 exposed by the third through hole 385. The third source S3 is located in the fourth through hole. The hole 386 is electrically connected to the second source S2 exposed by the fourth through hole 386, so that the first thin film transistor 30' is connected in parallel with the second thin film transistor 300, and the depletion type high electron mobility transistor 20 'Stacking, forming a normally closed splicing type high electron mobility transistor 2000 as shown in FIG. Embodiment 5:

Similarly, according to the normally closed splicing type high electron mobility transistor 1000 ′′ obtained in the third embodiment, a second thin film transistor 300 ′ can be formed on the first thin film as shown in FIG. 6 . Above the crystal 30" and in parallel with the first thin film transistor 30", the on-resistance R _{on is} lowered to increase the current I _D .

As shown in FIG. 6, the second thin film transistor 300' is over the first thin film transistor 30" and is isolated by a third protective layer 350. The second thin film transistor 300' includes a third gate. The electrode G3 is formed on the third protective layer 350, and a fourth protective layer 370 covers the third gate G3 and the remaining bare third protective layer 350 and a third channel layer 380. A fourth protective layer 370 of the third gate G3, a third source S3 and a third drain D3 are formed on the second channel layer 380 spaced apart from each other, and a second ohmic contact layer 395 is disposed on the third drain D3, between the third source S3 and the second channel layer 380. The third protective layer 350 in this embodiment is a ruthenium oxide layer; the fourth protective layer is a tantalum nitride layer; and the third gate may be composed of nickel and platinum. , refractory metals such as tungsten or molybdenum or alloys thereof; the third source S3 and the third drain D3 may be composed of a composite metal layer such as titanium/aluminum/titanium/gold or titanium/aluminum/nickel/gold. The material of the second channel layer 380 may be composed of amorphous germanium (a-Si), hydrogenated amorphous germanium (a-Si:H) or low temperature polycrystalline germanium; second ohmic contact layer 3 95 is an amorphous germanium layer doped with an n-type impurity.

In addition, the third gate G3 further includes a third through hole 385 extending through the fourth protective layer 370 and a portion of the third protective layer 350 and exposing the second drain D2, and a second bare source S2. Four through holes 386. The third drain D3 is located in the third through hole 385 and is electrically connected to the second drain D2 exposed by the third through hole 385. The third source S3 is located in the fourth through hole. 386, and electrically connected to the second source S2 exposed by the fourth through hole 386, so that the first thin film transistor 30" is connected in parallel with the second thin film transistor 300', and is high with the depletion type gallium nitride The mobility transistor 20" is laminated to form a normally-off spliced high electron mobility transistor 3000 as shown in FIG.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can change and combine the various implementations described above without departing from the spirit and scope of the present invention. example.

15'‧‧‧Substrate
20', 20" ‧ ‧ vacant high electron mobility transistor
30', 30"‧‧‧ first film transistor
40'‧‧‧Source pin
45, 55, 65, 45', 55', 65'‧‧‧ wires
50'‧‧‧ gate pin
60'‧‧‧汲pole pin
1000, 1000′, 1000′′, 2000, 3000‧‧‧ spliced high electron mobility transistor
150'‧‧‧ package
200‧‧‧Substrate
210‧‧‧buffer layer
220‧‧‧first channel layer
230‧‧‧Barrier layer
250‧‧‧First protective layer
270‧‧‧Second protective layer
280‧‧‧second channel layer
285‧‧‧first through hole
286‧‧‧Second through hole
290‧‧‧ dielectric layer
295‧‧‧First ohmic contact layer
300, 300'‧‧‧ second thin film transistor
350‧‧‧ third protective layer
370‧‧‧ fourth protective layer
380‧‧‧Second channel layer
385‧‧‧ third through hole
386‧‧‧fourth through hole
395‧‧‧Second ohmic contact layer
G1‧‧‧ first gate
S1‧‧‧first source
D1‧‧‧first source
G2‧‧‧second gate
S2‧‧‧Second source
D2‧‧‧second bungee
G3‧‧‧ third gate
S3‧‧‧ third source
D3‧‧‧third bungee

1A-1B illustrate an equivalent circuit of a normally-off spliced high electron mobility transistor 1000 according to an embodiment of the present invention.

FIG. 1C is a top perspective view of a package 150' encapsulating a normally-off spliced high electron mobility transistor 1000 as illustrated in FIGS. 1A-1B.

2A-2D illustrate a cross-sectional process of the normally-off spliced high electron mobility transistor 1000 according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a normally closed splicing type high electron mobility transistor 1000' according to the second embodiment of the present invention.

Fig. 4 is a view showing a normally closed splicing type high electron mobility transistor 1000" according to the third embodiment of the present invention.

FIG. 5 is a diagram showing a normally closed splicing type high electron mobility transistor 2000 according to the fourth embodiment of the present invention.

FIG. 6 is a diagram showing a normally closed splicing type high electron mobility transistor 3000 according to the fifth embodiment of the present invention.

20 ' ‧‧‧ Vacant High Electron Mobility Transistor

30 ' ‧‧‧First film transistor

1000‧‧‧ spliced high electron mobility transistor

200‧‧‧Substrate

210‧‧‧buffer layer

220‧‧‧first channel layer

230‧‧‧Barrier layer

250‧‧‧First protective layer

270‧‧‧Second protective layer

280‧‧‧second channel layer

285‧‧‧first through hole

286‧‧‧Second through hole

G1‧‧‧ first gate

S1‧‧‧first source

D1‧‧‧first source

G2‧‧‧second gate

S2‧‧‧Second source

D2‧‧‧second bungee

Claims (22)

A normally closed splicing type high electron mobility transistor, comprising: a substrate; a buffer layer formed on the substrate; a depletion type high electron mobility transistor formed on the buffer layer; a layer covering the depletion type high electron mobility transistor; and a first thin film transistor formed on the first protective layer, and the depletion type high electron mobility transistor and the first thin film transistor are stacked Pick up. The normally closed splicing type high electron mobility transistor according to claim 1, wherein the vacant high electron mobility transistor comprises: a first channel layer having a first energy gap formed On the buffer layer; a barrier layer having a second energy gap formed on the first channel layer, wherein the second energy gap is greater than the first energy gap; and a first gate, a first The source and the first drain are respectively formed on the barrier layer, and the first source and the first drain are respectively located on opposite sides of the first gate. The normally closed splicing type high electron mobility transistor according to claim 2, wherein the first thin film transistor comprises: a second gate formed on the first protective layer; a protective layer covering the second gate; a second channel layer formed on the second protective layer and located opposite the second gate; and a second source and a second drain spaced apart from each other Formed on the first channel layer; wherein the first thin film transistor further includes a first through hole and a second through hole, wherein the first through hole and the second through hole are located at the second gate The first source and the first gate are respectively exposed through the first protective layer, and the second drain is electrically connected to the first source via the first through hole, the second source The pole is electrically connected to the first gate through the second through hole. The normally closed splicing type high electron mobility transistor according to the third aspect of the invention, wherein the first through hole and the second through hole respectively penetrate the second protective layer. The normally closed splicing type high electron mobility transistor according to claim 3, wherein the first channel layer comprises a gallium nitride layer, and the barrier layer comprises an aluminum gallium nitride layer. The normally closed splicing type high electron mobility transistor according to claim 3, wherein the second channel layer comprises an amorphous germanium layer, a hydrogenated amorphous germanium layer or a low temperature polycrystalline germanium layer. The normally closed splicing type high electron mobility transistor according to claim 3, wherein the first protective layer comprises a ruthenium oxide layer or a tantalum nitride layer. The normally closed splicing type high electron mobility transistor according to claim 3, wherein the second protective layer comprises a ruthenium oxide layer or a tantalum nitride layer. The normally closed splicing type high electron mobility transistor according to claim 3, wherein the buffer layer comprises a gallium nitride layer containing a carbon dopant. The normally closed splicing type high electron mobility transistor according to claim 3, wherein the substrate comprises a sapphire substrate, a gallium nitride substrate, a germanium substrate or a tantalum carbide substrate. The normally closed splicing type high electron mobility transistor according to any one of claims 1 to 10, further comprising a dielectric layer disposed between the first gate and the barrier layer. The normally closed splicing type high electron mobility transistor according to claim 11, wherein the second source and the second channel layer are between the second drain and the first channel layer. Further comprising a first ohmic contact layer. The normally-off spliced type high electron mobility transistor according to claim 12, wherein the first ohmic contact layer comprises an amorphous germanium layer doped with an n-type impurity. The normally closed splicing type high electron mobility transistor according to any one of claims 1 to 10, further comprising a third protective layer covering the first thin film transistor and the second protection A second thin film transistor connected in parallel with the first thin film transistor is formed on the third protective layer. The normally closed splicing type high electron mobility transistor according to claim 14, wherein the second thin film transistor comprises: a third gate formed on the third protective layer; and a fourth protection a layer covering the third gate and the third protective layer; a third channel layer formed on the fourth protective layer, and the pair is located at the second gate; and a third source and a first The third thin film transistor further includes a third through hole and a fourth through hole, and the third through hole and the fourth through hole are located at the second channel layer. Two sides of the third gate penetrate through the third protective layer, and respectively expose the second drain and expose the second source, and the third drain passes through the third through hole and the second drain The third source is electrically connected to the second source via the fourth through hole. The normally-on splicing type high electron mobility transistor according to claim 15, wherein the third through hole and the fourth through hole respectively penetrate the fourth protective layer. The normally closed splicing type high electron mobility transistor according to claim 15, wherein the second channel layer comprises an amorphous germanium layer, a hydrogenated amorphous germanium layer or a low temperature polycrystalline germanium layer. The normally closed splicing type high electron mobility transistor according to claim 15, wherein the third protective layer and/or the fourth protective layer comprises a yttrium oxide or tantalum nitride layer. The normally closed splicing type high electron mobility transistor according to claim 15, further comprising a dielectric layer disposed between the first gate and the barrier layer. The normally closed splicing type high electron mobility transistor according to claim 19, wherein the dielectric layer comprises tantalum nitride, cerium oxide, cerium oxynitride or aluminum oxide. The normally closed splicing type high electron mobility transistor according to claim 19, wherein the third source and the third channel layer are between the third drain and the third channel layer. Further comprising a second ohmic contact layer. The normally closed splicing type high electron mobility transistor according to claim 21, wherein the second ohmic contact layer comprises an amorphous germanium layer doped with an n-type impurity.