M343792 八、新型說明： 【新型所屬之技術領域】 本創作係提供一種電路測試裝置，尤指一種可用以測 忒待測忒TL件之橋式動態輸出的電路測試裝置。 【先前技術】 隨著科技的進步，積體電路（Integratedcircuit，IC) -的功旎越來越強大，其重要性也與日遽增。除了單純處理 類比訊號的1C以及單純處理數位訊號的IC以外，業界還 陸績研發出多種兼具數位訊號與類比訊號處理能力的IC， 此種1C 一般可稱為混合訊號1C。而不論是數位訊號1C、 類比訊號1C、或混合訊號1C，為了破保1C出貨時的品質， 在完成製造過程之後，一般都會對每一顆IC執行測試，製 造商會依據對1C執行測試的結果，來決定此顆IC是否合 方σ 並據以判斷疋否可將此顆IC供應給下游的廢商。 _ 請參閱第1圖，第1圖為一般混合訊號測試機測試具 有橋是動態輸出之1C的示意圖。如第1圖所示，置放於待 測試元件電路板(DUT Board)14上的測試元件(IC)12接收 到混合訊號測試機(Mixed-Signal Tester) 10所產生的測試訊 说sT後’會於兩個輸出端Νι、&所產生相對應的輸出值， =此兩個相對應的輸出值為橋式動態輸出值v㈤π、 %必須藉由混合訊號測試機1〇分別量測兩個不同的橋式 2態輸出值V〇UT+、V0UT_，最後根據量測到的兩個橋式動 恶輸出值νουτ+、νουτ·，判斷待蜊試元件12的通過測試與 5 M343792 否。然而，上述的測試方式除了專用混合測試機ίο的價格 非常昂貴外，測試時必須分兩次量測橋式動態輸出值 V〇UT+ Λ V〇UT- 5 因此會耗掉冗長的測試時間，而進一步影 響1C測試的效率，這些都是習知使用專用混合訊號測試機 10測量測具有橋式動態輸出值V0UT+、V0UT_i 1C所遭遇 的問題。 【新型内容】 • 因此，本創作的目的之一，在於提供一種可提升1C測 試效率的測試架構，以解決習知技術所面臨的問題。 本創作提供一種電路測試裝置，用來測試一待測試元 件，其中待測試元件包含有一第一輸出端以及一第二輸出 端，該第一輸出端以及該第二輸出端用以分別產生一第一 輸出訊號以及一第二輸出訊號。電路測試裝置用以根據該 第一輸出訊號以及該第二輸出訊號，決定待測試元件的測 試結果。電路測試裝置包含有一量測模組、一處理模組、 ⑩一運算模組以及一微處理器。量測模組耦接於該待測試元 件，用以提供一測試訊號，並接收根據該測試訊號所產生 之一訊號運算結果。處理模組耦接於該待測試元件之該第 - 一輸出端以及該第二輸出端，用以轉換該待測試元件根據 該測試訊號所產生之第一輸出訊號以及該第二輸出訊號， 產生一處理訊號。運算模組耦接於該處理模組以及該量測 模組，用以接收該處理訊號，並對該處理訊號進行運算， 以產生該訊號運算結果。微處理器耦接於該量測模組，用 6 M343792 以根據該訊號運算結果來決定該待測試元件的測試結果。 【實施方式] 請參閱第2圖，第2圖為本創作之電路測試裝置之示 意圖。如第2圖所示，本創作之電路測試裝置2〇用來測試 一待測試元件22，而為了測試方便，待測試元件22通常 係設置於一待測試元件電路板（DUT board) 24上，於〆實 施例中待測試元件22係為一積體電路(Integrated arcuit，1C)。待 • 測試元件22包含有一第一輸出端％以及一第二輸出端 N2 ’第一輸出端％以及第二輸出端n2用以分別產生一第 一輸出訊號S〗以及一第二輸出訊號心。電路測試裝置20 用以根據該第一輸出訊號Si以及該第二輸出訊號s2，決定 該待測試元件22的測試結果。 電路測試裝置20包含有一量測模組32、一處理模組 34、一運算模組36以及一微處理器38。量測模組32耦接 φ 於待測试元件22，用以提供一測試訊號ST，並接收根據該 測試訊號sT所產生之一訊號運算結果Result。處理模組34 耦接於待測試元件22之第一輸出端Νι以及第二輸出端 N2，用以處理待測試元件22根據該測試訊號心所產生之 弟一輸出訊號S〗以及弟一輸出訊號S2，產生一處理訊號 Sp。運异模組36麵接於處理模組34以及量測模組32，用以 接收處理訊號SP ’並對處理訊號sp進行運算，以產生該訊 號運算結果Result。微處理器38耦接於量測模組32，用以 7 M343792 根據訊號運算結果Result來衫該制試元件22的測試結 果0 中 旦34係用以將雙端交流訊號模式之第一輸出 訊號Sl減仁知畴u S2键林端交絲賴紅該處理 訊號心。於一貫施例中’處理模組34為〆差動放大器，用 以將第#出訊魂S!以及第二輪出訊號&進行差動放 大’以產生該處理訊號Sp。M343792 VIII. New description: [New technical field] This creation provides a circuit test device, especially a circuit test device that can be used to measure the bridge dynamic output of the TL component to be tested. [Prior Art] With the advancement of technology, the integrated circuit (IC) - the power of the integrated circuit is becoming more and more powerful, and its importance is increasing. In addition to the 1C for analog signal processing and the IC for digital signal processing alone, the industry has developed a variety of ICs that combine digital signal and analog signal processing capabilities. This type of 1C is generally referred to as mixed signal 1C. Whether it is digital signal 1C, analog signal 1C, or mixed signal 1C, in order to break the quality of 1C shipment, after completing the manufacturing process, each IC is generally tested, and the manufacturer will perform tests based on 1C. As a result, it is determined whether the IC is square σ and it is judged whether or not the IC can be supplied to the downstream waste merchant. _ Please refer to Figure 1. Figure 1 is a schematic diagram of a general mixed-signal tester with a bridge that is a dynamic output of 1C. As shown in FIG. 1, the test component (IC) 12 placed on the DUT Board 14 receives the test sT generated by the Mixed-Signal Tester 10. The corresponding output value will be generated at the two outputs Νι, &, = the corresponding output value is the bridge dynamic output value v (five) π, % must be measured by the mixed signal tester 1 两个Different bridge 2-state output values V〇UT+, VOUT_, and finally, based on the measured two bridge-type moving-motive output values νουτ+, νουτ·, determine the pass test of the test component 12 and 5 M343792. However, in addition to the very expensive price of the dedicated hybrid tester, the above test method must measure the bridge dynamic output value V〇UT+ Λ V〇UT-5 twice, thus consuming a lengthy test time. Further affecting the efficiency of the 1C test, these are conventional problems with the use of the dedicated mixed-signal tester 10 to measure the bridge dynamic output values VOUTE, VOUT_i 1C. [New Content] • Therefore, one of the purposes of this creation is to provide a test architecture that can improve the efficiency of 1C testing to solve the problems faced by the prior art. The present invention provides a circuit testing device for testing a component to be tested, wherein the component to be tested includes a first output end and a second output end, wherein the first output end and the second output end are respectively used to generate a first An output signal and a second output signal. The circuit testing device is configured to determine a test result of the component to be tested according to the first output signal and the second output signal. The circuit testing device comprises a measuring module, a processing module, a computing module and a microprocessor. The measurement module is coupled to the component to be tested for providing a test signal and receiving a signal operation result generated according to the test signal. The processing module is coupled to the first output end and the second output end of the component to be tested, and is configured to convert the first output signal generated by the to-be-tested component according to the test signal and the second output signal to generate A processing signal. The computing module is coupled to the processing module and the measuring module for receiving the processing signal and calculating the processing signal to generate the signal operation result. The microprocessor is coupled to the measurement module, and uses 6 M343792 to determine the test result of the component to be tested according to the result of the signal operation. [Embodiment] Please refer to Fig. 2, and Fig. 2 is a schematic view of the circuit test apparatus of the present invention. As shown in FIG. 2, the circuit test apparatus 2 of the present invention is used to test a component to be tested 22, and for testing convenience, the component 22 to be tested is usually disposed on a DUT board 24 to be tested. In the embodiment, the component to be tested 22 is an integrated circuit (1C). The test component 22 includes a first output terminal % and a second output terminal N2 ′ the first output terminal % and the second output terminal n2 for respectively generating a first output signal S and a second output signal heart. The circuit testing device 20 is configured to determine a test result of the component 22 to be tested according to the first output signal Si and the second output signal s2. The circuit testing device 20 includes a measurement module 32, a processing module 34, an operation module 36, and a microprocessor 38. The measurement module 32 is coupled to the component 22 to be tested for providing a test signal ST and receiving a signal operation result Result generated according to the test signal sT. The processing module 34 is coupled to the first output terminal Ν1 and the second output terminal N2 of the component to be tested 22 for processing the output signal S and the output signal of the device to be tested 22 according to the test signal heart. S2, generating a processing signal Sp. The operation module 36 is connected to the processing module 34 and the measurement module 32 for receiving the processing signal SP ′ and calculating the processing signal sp to generate the signal operation result Result. The microprocessor 38 is coupled to the measurement module 32 for 7 M343792 to test the test result of the test component 22 according to the result of the signal operation. The system is used to transmit the first output signal of the double-ended AC signal mode. Sl 仁仁知域u S2 key Lin Duan 交丝赖红 The processing signal heart. In the conventional embodiment, the processing module 34 is a chirped differential amplifier for differentially amplifying the ##出讯魂S! and the second round of signal & to generate the processing signal Sp.
明爹閱第2 ®及第3圖’第3圖為本創作之電路測試 裝置之處理模組之-貫施例之示意圖。如第2圖及第3圖所 示’處理模組34包含有-放大H 34卜-第-電阻Rl、-第二電阻R2、-第三電阻&以及一第四電阻&。放大器 341包含有-正輸入端、一負輸入端以及一輸出端。放大 器341之負輸入端耦接於待測試元件22之第一輸出端％。 放大器341之正輸入端耦接於待測試元件22之第二輸出端 Ns。放大器341用以將待測試元件22之第一輸出端队所 輸出之第一輸出訊號S!以及待測試元件22之第二輸出端 %所輸出之第二輸出訊號&進行放大，以產生該處理訊號 SP。第一電阻&耦接於待測試元件22之第一輸出端％以 及放大器341之負輸入端之間。第二電阻&耦接於待測試 元件22之第二輸出端沁以及放大器341之該正輸入端之 間。第三電阻Rs耦接於放大器341之該輸出端以及該負輸 入端之間。第四電阻I之一端耦接於第二電阻K以及放 大裔341之負輸入端之間，其另一端則耦接於一接地端 8 M343792 GND 〇 此外，電路測試裝置20另包含有一暫存器（圖未示）以 及一顯示模組（圖未示），暫存器（圖未示）耦接於微處理器 38，用以儲存該測試結果，顯示模組（圖未示）則用以顯示 該待測試元件22的測試結果。此外’電路測試裝置20係 為一邏輯測試機。於另一實施例中，量測模組32以及微處 理器38係設置於該邏輯測試機内。 在本創作的各個實施例中，電路測試裝置使用了處理 • 模組來執行待測試元件之第一輸出訊號以及第二輸出訊號 的差動放大處理，以產生單一輸出訊號的處理訊號，再藉 由運算模組將交流型態之處理訊號轉換為直流型態的訊號 運算結果，故後續微處理器僅需藉由該訊號運算結果，即 可判斷待測試元件是否通過測試，達成測試待測試元件之 橋式動態輸出的目的。相較於習知技術必須使用專用交流 訊號測試機分次測量橋式差動輸出的方式，本創作各實施 0 例的測試架構可以有效提升晶片測試的速度，進一步提升 -測試效率，這些都是本創作優於習知技術的特點。 以上所述僅為本創作之較佳實施例，凡依本創作申請 專利範圍所做之均等變化與修飾，皆應屬本創作之涵蓋範 M343792 【圖式簡單說明】 之1C的 / 1圖為_般混合訊制試機峨具有橋是動態輸出 第2圖為本創作之電路測試裝置之示意圖。 第3圖為本_之電路職裝置之處理顚之—實施例之示The second and third figures of Figure 3 are a schematic diagram of the processing module of the circuit test device of the present invention. As shown in Figs. 2 and 3, the processing module 34 includes - amplification H 34 - a - resistance R1, - a second resistor R2, a third resistor & and a fourth resistor & The amplifier 341 includes a positive input, a negative input, and an output. The negative input terminal of the amplifier 341 is coupled to the first output terminal % of the component 22 to be tested. The positive input terminal of the amplifier 341 is coupled to the second output terminal Ns of the component 22 to be tested. The amplifier 341 is configured to amplify the first output signal S! outputted by the first output end of the component to be tested 22 and the second output signal & outputted by the second output terminal % of the component to be tested 22 to generate the Process the signal SP. The first resistor & is coupled between the first output terminal % of the component under test 22 and the negative input terminal of the amplifier 341. The second resistor & is coupled between the second output terminal 待 of the component to be tested 22 and the positive input terminal of the amplifier 341. The third resistor Rs is coupled between the output of the amplifier 341 and the negative input. One end of the fourth resistor I is coupled between the second resistor K and the negative input terminal of the amplifier 341, and the other end is coupled to a ground terminal 8 M343792 GND. In addition, the circuit testing device 20 further includes a register. (not shown) and a display module (not shown), a register (not shown) coupled to the microprocessor 38 for storing the test result, and a display module (not shown) for The test result of the component 22 to be tested is displayed. Further, the circuit test device 20 is a logic tester. In another embodiment, the measurement module 32 and the microprocessor 38 are disposed in the logic tester. In various embodiments of the present invention, the circuit test apparatus uses a processing module to perform differential amplification processing of the first output signal of the component to be tested and the second output signal to generate a processing signal of a single output signal, and then borrow The operation module converts the processing signal of the AC type into the signal operation result of the DC type, so that the subsequent microprocessor only needs to use the result of the signal operation to determine whether the component to be tested passes the test and achieve the test component to be tested. The purpose of the bridge type dynamic output. Compared with the conventional technology, it is necessary to use a dedicated AC signal tester to measure the bridge differential output in stages. The test architecture of each of the 0 implementations can effectively improve the speed of wafer testing and further improve the test efficiency. This creation is superior to the characteristics of the prior art. The above description is only the preferred embodiment of the present invention. All the equivalent changes and modifications made by the scope of the patent application of this creation should belong to the scope of the creation of the novel M343792 [Simple description of the diagram] 1C / 1 picture is The _-like hybrid test machine has a bridge that is dynamic output. Figure 2 is a schematic diagram of the circuit test device of the present invention. Figure 3 is a diagram of the processing of the circuit device of the present invention - an embodiment
【主要元件符號說明】 10 交流訊號測試機 12、22 待測試元件 14、24 待測試元件電路板 20 電路測試裝置 32 量測模組 34 處理模組 36 運算模組 38 微處理器 341 放大器 R1、R2、R3、R4 電阻 风、n2 輸出端 S!、S2 輸出訊號 St 測試訊號 SP 處理訊號 Vout+ ^ Vout- 橋式動態輸出值 Result 訊號運算結果 10[Main component symbol description] 10 AC signal testing machine 12, 22 Components to be tested 14, 24 Components to be tested Circuit board 20 Circuit testing device 32 Measuring module 34 Processing module 36 Computing module 38 Microprocessor 341 Amplifier R1 R2, R3, R4 resistance wind, n2 output S!, S2 output signal St test signal SP processing signal Vout+ ^ Vout- bridge dynamic output value Result signal operation result 10