TWI830061B - field effect transistor - Google Patents

Abstract

A field effect transistor includes: a first semiconductor structure has a channel layer; a second semiconductor structure is provided on the first semiconductor structure, and the second semiconductor structure stacks a Schott base layer and a first etching layer sequentially from bottom to top. It is composed of a stop layer, a wide concave layer and an ohmic contact layer, and a narrow groove is opened in the wide concave layer and a wide groove is opened in the ohmic contact layer, and the wide groove is located above the narrow groove, so that the wide groove is A wide concave area is formed on the upper surface of the concave layer and a narrow concave area is formed on the upper surface of the Schott base layer; at least one delta doped layer is inserted into a predetermined position in the second semiconductor structure; the gate metal contact is formed in the wide groove and the bottom surface of the narrow groove to a predetermined position within the narrow concave area; the source metal contact is located on the ohmic contact layer, and the source metal contact is located on one side of the gate metal contact; and the drain metal contact It is located on the ohmic contact layer, and the drain metal contact is located on the other side of the gate metal contact.

Description

field effect transistor

The present invention relates to a field effect transistor, in particular to a field effect transistor with a delta doped layer.

According to the field effect transistor, due to the applied voltage, electrons are injected from the source to the drain, and the electrons are transported from the ohmic metal of the source down to the channel layer, transported along the channel to the drain, and in the ohmic metal of the drain Moves upward, and the gate contact regulates the current in the channel, restricting or opening the flow of electrons from source to drain.

Secondly, the transmission time of electrons from source to drain is affected by the channel resistance in the gate area and non-gate area, and the speed of the device is proportional to the transmission time, and the transconductance of the high electron mobility transistor will be affected by the gate -The resistance of the source decreases, and transconductance affects the gain of the device. Parasitic resistance increases I-R losses (voltage drops) in the device. When a high electron mobility transistor is used as a power amplifier, the reduction in the gate-drain electric field allows the device to operate at a higher voltage before avalanche breakdown begins. Higher voltage operation results in higher output power.

The main purpose of the present invention is to provide a field effect transistor that improves large-signal radio frequency performance by reducing parasitic resistance and modifying electric field distribution, thereby improving the efficiency, output energy, and breakdown voltage of radio frequency transistors and power amplifiers. , gain and bandwidth.

Another object of the present invention is to provide a field effect transistor that reduces parasitic resistance and can achieve better performance in high-frequency applications such as millimeter wave 5G and 6G.

To achieve the above object, the technical means adopted in the present invention include: a first semiconductor structure having a channel layer; a second semiconductor structure disposed on the first semiconductor structure, and The second semiconductor structure is composed of a Schottky layer, a first etching stop layer, a wide concave layer, and an ohmic contact layer sequentially stacked from bottom to top, and a narrow groove is opened in the wide concave layer and the The ohmic contact layer is provided with a wide groove, and the wide groove is located above the narrow groove, so that the upper surface of the wide concave layer forms a wide concave area and the upper surface of the Schott base layer forms a narrow concave area; At least one delta doped layer, the delta doped layer is inserted into a predetermined position in the second semiconductor structure; a gate metal contact, the gate metal contact is formed in the wide groove and the bottom surface of the narrow groove to a predetermined position within the narrow concave area; a source metal contact, the source metal contact is provided on the ohmic contact layer, and the source metal contact is located on one side of the gate metal contact; and a drain metal contact, the drain metal contact is disposed on the ohmic contact layer, and the drain metal contact is located on the other side of the gate metal contact.

According to the aforementioned characteristics, the wide concave layer is n-type doped at a uniform constant value or has a gradient doping with a peak doping on the top surface of the wide groove.

According to the aforementioned characteristics, the gradient doping is linear, step gradient, quadratic gradient, exponential or a combination thereof.

According to the aforementioned characteristics, the field effect transistor is a high electron mobility transistor, a pseudo high electron mobility transistor, a heterostructure field effect transistor or a modulated doped FET.

According to the characteristics disclosed above, the field effect transistor is a depletion mode normally on transistor or an enhancement mode normally off transistor.

According to the aforementioned characteristics, the delta doped layer is grown from epitaxial material by molecular beam epitaxy, metal organic chemical vapor deposition or a combination thereof.

According to the aforementioned characteristics, the thickness of the delta doped layer grown by molecular beam epitaxy is 1 to 2 monolayers thick and 0.5 to 1.2 nm.

According to the aforementioned characteristics, the thickness of the delta doped layer grown by the metal organic chemical vapor deposition is 1 to several monolayers thick.

According to the aforementioned characteristics, the epitaxial material is GaAs material.

According to the aforementioned characteristics, the delta doped layer is inserted into the wide concave region in the wide concave layer.

According to the aforementioned characteristics, the wide concave layer includes a first layer and a second layer, the first layer is located between the upper surface of the delta doped layer and the upper surface of the wide concave layer, and the second layer is located between the lower surface of the delta doped layer and the lower surface of the wide concave layer, and the thickness of the first layer is greater than or equal to the thickness of the second layer.

According to the aforementioned characteristics, the material of the first layer and the second layer is n-type AlGaAs.

According to the aforementioned characteristics, the thickness of the first layer is 10~20nm; the thickness of the second layer is 1~10nm, the doping species is Si, and the Si doping concentration is 1~5e17cm-3.

According to the aforementioned characteristics, the thickness of the first layer is 9 nm; the thickness of the second layer is 1 nm, the doping species is Si, and the Si doping concentration is 3e17cm-3.

According to the front-revealing characteristics, the gate metal contact sequentially forms Ti-Pt-Au, Ti-Pt-Au-Ti, Ti-Mo-Au, and Ti- on the surface of the Schott base layer in the narrow concave area. Mo-Au-Ti, Ti-Pd-Au or Ti-Pd-Au-Ti.

According to the front-revealing characteristics, the gate metal contact sequentially forms Pt-Ti-Pt-Au, Pt-Ti-Pt-Au-Ti, Pt-Ti- on the surface of the Schott base layer in the narrow concave area. Mo-Au, Pt-Ti-Mo-Au-Ti, Pt-Ti-Pd-Au or Pt-Ti-Pd-Au-Ti, and perform heat treatment to mix the materials of the first Pt layer and the second semiconductor structure , and from the gate metal contact to the second semiconductor structure to below the upper surface of the Schottky layer in the narrow recessed region.

According to the aforementioned characteristics, the delta doped layer is inserted between the narrow concave region and the lower surface of the Schott base layer, and the gate metal contacts are sequentially formed on the upper surface of the Schott base layer in the narrow concave region. Pt-Ti-Pt-Au, Pt-Ti-Pt-Au-Ti, Pt-Ti-Mo-Au, Pt-Ti-Mo-Au-Ti, Pt-Ti-Pd-Au or Pt-Ti-Pd- Au-Ti, and perform heat treatment to mix the materials of the first Pt layer and the second semiconductor structure, and bond from the gate metal contact in the second semiconductor structure to the Schottky layer in the narrow recessed area Below the upper surface, below the delta doped layer and within the narrow concave region.

According to the aforementioned features, the second semiconductor structure includes a second etch stop layer disposed between the wide concave layer and the ohmic contact layer.

According to the aforementioned characteristics, the material of the Schottky layer is n-type AlGaAs; the material of the first etching stop layer is n-type InGaP or n-type AlAs; the material of the wide concave layer is n-type AlGaAs; the material of the delta doped layer The material is n-type GaAs or n-type AlGaAs; the material of the second etching stop layer is n-type InGaP or n-type AlAs; the material of the ohmic contact layer is n-type GaAs or n-type InGaAs, or a combination thereof.

According to the aforementioned characteristics, the thickness of the Schottky layer is 5~20nm, the doping species is Si, and the Si doping concentration is 1~3e17cm-3; the thickness of the first etching stop layer is 5nm, and the doping species is Si. And the Si doping concentration is greater than 1e19cm-3; the thickness of the delta doping layer is 1ML, the doping species is Si and the Si doping concentration is 0.5~1.5e12cm-2; the thickness of the second etching stop layer is 5nm , the doping species is Si and the Si doping concentration is greater than 1e19cm-3; the thickness of the ohmic contact layer is 20~120nm, the doping species is Si and the Si doping concentration is greater than 5e18cm-3.

According to the aforementioned characteristics, the thickness of the Schottky layer is 10 nm, the doping species is Si, and the Si doping concentration is 3e17cm-3; the thickness of the first etching stop layer is 5 nm, the doping species is Si, and the Si doping concentration is 3e17cm-3. The impurity concentration is greater than 1e19cm-3; the thickness of the delta doped layer is 1ML, the doping species is Si and the Si doping concentration is 1.0e12cm-2; the thickness of the second etching stop layer is 5nm, and the doping species is Si And the Si doping concentration is greater than 1e19cm-3; the thickness of the ohmic contact layer is 50nm, the doping species is Si, and the Si doping concentration is greater than 5e18cm-3.

According to the aforementioned characteristics, the first semiconductor structure includes a substrate, a buffer layer, a supercrystalline buffer layer, a transition layer, a first delta doped layer, a first spacer layer, a second spacer layer, a a second delta doped layer, and the first semiconductor structure stacks the substrate, the buffer layer, the supercrystalline buffer layer, the transition layer, the first delta doped layer, and the first spacer in order from bottom to top. layer, the channel layer, the second spacer layer and the second delta doped layer.

According to the aforementioned characteristics, the material of the substrate is semi-insulating GaAs; the material of the buffer layer is unintentionally doped GaAs; the material of the supercrystalline buffer layer is AlGaAs/GaAs; the material of the transition layer is unintentionally doped GaAs ; The material of the first delta doped layer is n-type GaAs; the material of the first spacer layer is unintentionally doped AlGaAs; the material of the channel layer is unintentionally doped InGaAs; the material of the second spacer layer is unintentionally doped AlGaAs AlGaAs is intentionally doped; the material of the second delta doped layer is n-type GaAs.

By means of the above-mentioned technique, the present invention improves the performance of the field-effect transistor by combining the gate metal contact with the second semiconductor structure and inserting the delta doped layer in the second semiconductor structure, thereby reducing the gate -The resistance between the drain and the gate-source, and inserting the δ-doped layer reduces the electric field at the gate-drain edge, increases the breakdown voltage of the off-state and the on-state, and improves the RF transistor and Power amplifier efficiency, output energy, breakdown voltage, gain and bandwidth.

First, please refer to Figures 1 to 11, which show a field effect transistor 70A, 70B, and 70C of the present invention. The field effect transistors 70A, 70B, and 70C are high electron mobility transistors and pseudo high electron mobility transistors. Or a heterostructure field effect transistor (HFET) or a modulated doped FET (MODFET), and the field effect transistors 70A, 70B, and 70C are depletion mode normally on transistors or enhancement mode normally off transistors, including: a first A semiconductor structure 10. The first semiconductor structure 10 has a channel layer 11. In this embodiment, the first semiconductor structure 10 includes a substrate 12, a buffer layer 13, a supercrystalline buffer layer 14, and a transition layer. 15. A first delta doped layer 16, a first spacer layer 17, a second spacer layer 18, a second delta doped layer 19, and the first semiconductor structure 10 is stacked on the substrate in sequence from bottom to top. 12. The buffer layer 13, the supercrystalline buffer layer 14, the transition layer 15, the first delta doped layer 16, the first spacer layer 17, the channel layer 11, the second spacer layer 18 and the third It is composed of two delta doped layers 19, but is not limited to this.

Following the above, the material of the substrate 12 is semi-insulating GaAs; the material of the buffer layer 13 is unintentionally doped GaAs; the material of the supercrystalline buffer layer 14 is AlGaAs/GaAs; the material of the transition layer 15 is unintentionally doped GaAs. doped GaAs; the material of the first delta doped layer 16 is n-type GaAs; the material of the first spacer layer 17 is unintentionally doped AlGaAs; the material of the channel layer 11 is unintentionally doped InGaAs; the second spacer The material of the layer 18 is unintentionally doped AlGaAs; the material of the second delta doped layer 19 is n-type GaAs, but is not limited thereto.

A second semiconductor structure 20 is provided on the first semiconductor structure 10, and the second semiconductor structure 20 is sequentially stacked with a Schottky layer 21 and a first etching stop layer 22 from bottom to top. , composed of a wide concave layer 23 and an ohmic contact layer 25, and a narrow groove 26 is opened in the wide concave layer 23 and a wide groove 27 is opened in the ohmic contact layer 25, and the wide groove 27 is located at Above the narrow groove 26, a wide concave area W is formed on the upper surface of the wide concave layer 27 and a narrow concave area N is formed on the upper surface of the Schottky layer 21. In this embodiment, the second semiconductor structure 20 includes a second etching stop layer 24 disposed between the wide concave layer 23 and the ohmic contact layer 25, but is not limited thereto.

Following the above, the material of the Schottky layer 21 is n-type AlGaAs; the material of the first etching stop layer 22 is n-type InGaP or n-type AlAs; the material of the wide concave layer 23 is n-type AlGaAs; the δ-doped layer The material of 30 is n-type GaAs or n-type AlGaAs; the material of the second etching stop layer 24 is n-type InGaP or n-type AlAs; the material of the ohmic contact layer 25 is n-type GaAs or n-type InGaAs, or a combination thereof, But it is not limited to this.

Following the above, the thickness of the Schottky layer 21 is 5~20nm, the doping species is Si, and the Si doping concentration is 1~3e17cm-3; the thickness of the first etching stop layer 22 is 5nm, and the doping species is Si. And the Si doping concentration is greater than 1e19cm-3; the thickness of the delta doping layer 30 is 1ML, the doping species is Si and the Si doping concentration is 0.5~1.5e12cm-2; the thickness of the second etching stop layer 24 is 5nm, the doping species is Si and the Si doping concentration is greater than 1e19cm-3; the thickness of the ohmic contact layer 25 is 20~120nm, the doping species is Si and the Si doping concentration is greater than 5e18cm-3, but is not limited Here it is.

Following the above, the thickness of the Schottky layer 21 is 10 nm, the doping species is Si, and the Si doping concentration is 3e17cm-3; the thickness of the first etching stop layer 22 is 5 nm, the doping species is Si, and the Si doping concentration is 5 nm. The impurity concentration is greater than 1e19cm-3; the thickness of the delta doped layer 30 is 1ML, the doping species is Si, and the Si doping concentration is 1.0e12cm-2; the thickness of the second etching stop layer 24 is 5nm, and the doping species It is Si and the Si doping concentration is greater than 1e19cm-3; the thickness of the ohmic contact layer 25 is 50nm, the doping species is Si and the Si doping concentration is greater than 5e18cm-3, but is not limited thereto.

At least one δ-doped layer 30 is inserted into a predetermined position in the second semiconductor structure 20. In this embodiment, the δ-doped layer 30 is grown by epitaxial material through molecular beam epitaxy (MBE). ), metal organic chemical vapor deposition (MOCVD) or a combination thereof; the thickness of the delta doped layer 30 is 1 to 2 monolayers (ML) thick and 0.5 to 1.2 nm grown by molecular beam epitaxy; the delta doped layer The thickness of the layer 30 is 1 to several single layers grown by metal organic chemical vapor deposition; the epitaxial material is GaAs material, but is not limited thereto.

a gate metal contact 40, the gate metal contact 40 is formed in the wide groove 27 and the bottom surface of the narrow groove 26 to a predetermined place in the narrow concave area N; a source metal contact 50, The source metal contact 50 is disposed on the ohmic contact layer 25, and the source metal contact 50 is located on one side of the gate metal contact 40; a drain metal contact 60, the drain metal contact Point 60 is provided on the ohmic contact layer 25 , and the drain metal contact 60 is located on the other side of the gate metal contact 40 .

As shown in FIGS. 1 to 4 , which is a field effect transistor 70A of the first embodiment, the delta doped layer 30 is inserted into the wide concave region W of the wide concave layer 23 , and the wide concave layer 23 includes a A first layer 231 and a second layer 232. The first layer 231 is located between the upper surface of the δ-doped layer 30 and the upper surface of the wide concave layer 23, and the second layer 232 is located between the δ-doped layer 30 and the upper surface of the wide concave layer 23. between the lower surface of the hybrid layer 30 and the lower surface of the wide concave layer 23, and the thickness B of the first layer 231 is greater than or equal to the thickness A of the second layer 232. In this embodiment, the first layer 231 The material of the second layer 232 is n-type AlGaAs; the thickness of the first layer 231 is 10~20nm; the thickness of the second layer 232 is 1~10nm, the doping species is Si, and the Si doping concentration is 1 ~5e17cm-3; the thickness of the first layer 231 is 9nm; the thickness of the second layer 232 is 1nm, the doping species is Si and the Si doping concentration is 3e17cm-3, but is not limited thereto.

As shown in Figure 2, it reduces the electric field distribution in the gate-drain region GD under the applied voltage, and the electric field will reach a peak in the gate-drain region GD, and due to impact ionization caused by the higher electric field, The breakdown of the field effect transistor 70A is initially limited, and the breakdown voltage is extended so that the field effect transistor 70A can operate at high power density, and the gate-source region GS and the gate-drain region GD The resistance is reduced. The reduction of these parasitic resistances increases the gain, output energy, bandwidth and efficiency of the transistor and power amplifier, and improves the noise characteristics of the low-noise amplifier, allowing electrons to be effectively injected from the source metal contact 50 into the The channel layer 11 to the drain metal contact 60 improves the resistance of the ohmic contact layer 25, and the wide concave layer 23 has electrons e and traps D at the interface and along the sidewall. The trap D will affect the device performance, but The trap D is also isolated from the channel layer 11 below the Schottky layer 21 by using the delta doped layer 30 in the wide concave layer 23 .

As shown in FIG. 4 , the gate metal contact 40 is sequentially formed with Pt-Ti-Pt-Au, Pt-Ti-Pt-Au-Ti, Pt-Ti-Mo-Au, Pt-Ti-Mo-Au-Ti, Pt-Ti-Pd-Au or Pt-Ti-Pd-Au-Ti, and perform heat treatment to mix the first Pt layer 41 and the The material of the second semiconductor structure 20 is bonded from the gate metal contact 40 to the bottom of the upper surface of the Schottky layer 21 in the narrow concave region N from the second semiconductor structure 20. In this embodiment, the The first Pt layer 41 is mixed with the n-type AlGaAs material of the Schott base layer 21 at a heat treatment temperature of 300°C to 400°C, and further illustrates that the gate metal contact 40 forms Pt-Ti-Pt-Au-Ti. , as if the gate metal contact 40 is composed of the first Pt layer 41, the first Ti layer 42, the second Pt layer 43, the Au layer 44, and the second Ti layer 45 in sequence, and is composed of the The bottom Lg of the first Pt layer 41 has a rounded interface, but is not limited thereto.

As shown in FIGS. 5 to 6 , this is a field effect transistor 70B of the second embodiment. The difference from the field effect transistor 70A of the first embodiment lies in the position of the gate metal contact 40 in the narrow concave area N. The upper surface of the Schott base layer 21 is sequentially formed with Ti-Pt-Au, Ti-Pt-Au-Ti, Ti-Mo-Au, Ti-Mo-Au-Ti, Ti-Pd-Au or Ti-Pd-Au. -Ti, and the bottom Lg of the first Pt layer 41 is a flat-angle interface, but is not limited to this.

As shown in Figures 7 to 10, it is a field effect transistor 70C of the third embodiment. The difference from the field effect transistors 70A and 70B of the first and second embodiments is that the delta doped layer 30 is inserted into the narrow recess. Between the area N and the lower surface of the Schottky layer 21, and the gate metal contact 40 is sequentially formed on the upper surface of the Schottky layer 21 in the narrow concave area N, Pt-Ti-Pt-Au, Pt -Ti-Pt-Au-Ti, Pt-Ti-Mo-Au, Pt-Ti-Mo-Au-Ti, Pt-Ti-Pd-Au or Pt-Ti-Pd-Au-Ti and perform heat treatment to mix The materials of the first Pt layer 41 and the second semiconductor structure 20 are combined from the gate metal contact 40 in the second semiconductor structure 20 to the upper surface of the Schottky layer 21 in the narrow concave region N. Below, below the delta doped layer 30 and in the narrow concave region N, and with the bottom Lg of the first Pt layer 41 as a rounded interface, but is not limited thereto.

As shown in FIGS. 10 to 13 , it is a field effect transistor 70D of the fourth embodiment. The difference from the field effect transistor 70C of the third embodiment is that it does not include the wide concave layer 23 and the first etching stop layer. 22. The field effect transistor 70D has a single-layer structure.

In addition, the thickness of the buffer layer 13 is 200nm; the thickness of the supercrystalline buffer layer 14 is 18.5/1.5nm; the thickness of the transition layer 15 is 10~80nm; the thickness of the first δ doped layer 16 is 1ML. The doping species is Si and the Si doping concentration is 0.5~1.5e12cm-2; the thickness of the first spacer layer 17 is 3.5~4.0nm; the thickness of the channel layer (11) is 8~15nm; the second spacer The material of layer 18 is 3.5~4.5nm; the thickness of the second delta doped layer 19 is 1ML, the doping species is Si and the Si doping concentration is 3.5~5e12cm-2, or the thickness of the buffer layer 13 is 200nm ; The thickness of the supercrystal buffer layer 14 is 18.5/1.5nm; the thickness of the transition layer 15 is 40nm; the thickness of the first δ doped layer 16 is 1ML, the doping species is Si and the Si doping concentration is 0.8e12cm-2; the thickness of the first spacer layer 17 is 4.5nm; the thickness of the channel layer 11 is 13nm; the material of the second spacer layer 18 is 4.5nm; the thickness of the second δ doped layer 19 is 1ML , the doping species is Si and the Si doping concentration is 4.2e12cm-2. The period of the supercrystalline buffer layer (14) is 15.

Based on this structure, the wide concave layer 23 is gradually doped with n-type doping at a uniform constant value or with a peak doping at the top surface of the wide groove. The gradient doping is linear, step gradient, quadratic gradient, exponential or a combination thereof. As shown in Figure 14, the doping curve distribution of the wide concave layer 23 is a first curve C ₁ , a second curve C ₂ , A third curve C ₃ and a fourth curve C ₄ further illustrate that the first curve C ₁ is a constant and uniform profile, the second curve C ₂ is a linear gradient profile, and the third curve C ₃ is an exponential or quadratic profile. The secondary gradient curve and a fourth curve C ₄ are stepped. In this way, the delta doped layer 30 in the wide concave layer 23 has the function of connecting the source metal contact 50 and the drain metal Under the ohmic contact layer 25 of the contact 60, electrons e are effectively injected from the source metal contact 50 to the channel layer 11 to the drain metal contact 60, and in the gate-source region GS, the electric field is The δ-doped layer 30 is lowered, allowing electrons e to flow freely in the channel layer, reducing the electron confinement of the trap D, and the resistivity of the gate-source region GS is also reduced. As shown in Figures 3 and 9 Show.

To sum up, the technical means disclosed in the present invention indeed meet the requirements for invention patents such as "novelty", "progressivity" and "available for industrial utilization". We pray that the Jun Bureau will grant patents to encourage creation without any restrictions. Sense of morality.

However, the above disclosed drawings and descriptions are only preferred embodiments of the present invention. Modifications or equivalent changes made by those familiar with the art in accordance with the spirit and scope of this case should still be included in the patent application scope of this case.

70A, 70B, 70C: field effect transistor 10: first semiconductor structure 11: channel layer 12: substrate 13: buffer layer 14: super crystal buffer layer 15: transition layer 16: first δ doping layer 17: first Spacer layer 18: second spacer layer 19: second delta doped layer 20: second semiconductor structure 21: Schottky layer 22: first etching stop layer 23: wide concave layer 231: first layer 232: second layer 24 : Second etch stop layer 25: Ohmic contact layer 26: Narrow groove 27: Wide groove 30: Delta doping layer 40: Gate metal contact 50: Source metal contact 60: Drain metal contact A: Thickness of the second layer B: Thickness of the first layer C ₁ : First curve C ₂ : Second curve C ₃ : Third curve C ₄ : Fourth curve D: Defect GS: Gate-source area GD: Gate Pole-drain region Lg: bottom N: narrow concave region W: wide concave region e: electrons

FIG. 1 is a schematic diagram of a field effect transistor according to the first embodiment of the present invention. FIG. 2 is a schematic diagram of the structure of the gate metal contact and the second semiconductor according to the first embodiment of the present invention. Figure 3 is a schematic diagram of electrons passing through the channel layer according to the first embodiment of the present invention. FIG. 4 is a schematic diagram of the gate metal contact bonded to the Schott base layer according to the first embodiment of the present invention. FIG. 5 is a schematic diagram of a field effect transistor according to a second embodiment of the present invention. FIG. 6 is a schematic diagram of the gate metal contact bonded to the Schott base layer according to the second embodiment of the present invention. FIG. 7 is a schematic diagram of a field effect transistor according to a third embodiment of the present invention. FIG. 8 is a schematic diagram of the structure of the gate metal contact and the second semiconductor according to the third embodiment of the present invention. Figure 9 is a schematic diagram of electrons passing through the channel layer according to the third embodiment of the present invention. FIG. 10 is a schematic diagram of the gate metal contact bonded to the Schott base layer according to the third embodiment of the present invention. Figure 11 is a schematic diagram of a field effect transistor according to the fourth embodiment of the present invention. FIG. 12 is a schematic diagram of the structure of the gate metal contact and the second semiconductor according to the fourth embodiment of the present invention. Figure 13 is a schematic diagram of electrons passing through the channel layer according to the fourth embodiment of the present invention. Figure 14 is a schematic diagram of the n-type doping curve of the wide concave layer of the present invention.

70A: Field effect transistor

10: First semiconductor structure

11: Channel layer

12:Substrate

13: Buffer layer

14:Super crystal buffer layer

15: Transition layer

16: First delta doped layer

17:First spacer layer

18:Second spacer layer

19: Second delta doped layer

20: Second semiconductor structure

21: Schott grassroots

22: First etch stop layer

23:Wide concave layer

231:First floor

232:Second floor

24: Second etch stop layer

25: Ohmic contact layer

26: Narrow groove

27:Wide groove

30: δ doping layer

40: Gate metal contact

50: Source metal contact

60: Drain metal contact

A:Thickness of the second layer

B:Thickness of the first layer

N: Narrow concave area

W: wide concave area

Claims (19)

A field effect transistor includes: a first semiconductor structure having a channel layer; a second semiconductor structure disposed on the first semiconductor structure, and the second semiconductor structure It consists of sequentially stacking a Schottky layer, a first etching stop layer, a wide concave layer, and an ohmic contact layer from bottom to top, and a narrow groove is opened in the wide concave layer and a narrow groove is opened in the ohmic contact layer. A wide groove is located above the narrow groove, so that the upper surface of the wide concave layer forms a wide concave area and the upper surface of the Schott base layer forms a narrow concave area. The doping method is gradient doping with peak doping on the top surface of the wide groove or within 5 nanometers of the top surface of the wide groove. The gradient doping includes linear, step gradient, quadratic gradient, and exponential. One or a combination thereof; at least one delta doped layer, the delta doped layer is inserted into the second semiconductor structure at a predetermined location; a gate metal contact, the gate metal contact is formed in the wide groove and from the bottom surface of the narrow groove to a predetermined position within the narrow concave area; a source metal contact, the source metal contact is provided on the ohmic contact layer, and the source metal contact is located on the gate metal contact one side of the point; and a drain metal contact, the drain metal contact is provided on the ohmic contact layer, and the drain metal contact is located on the other side of the gate metal contact. The field effect transistor of claim 1, wherein the field effect transistor includes a high electron mobility transistor, a pseudo high electron mobility transistor, a heterostructure field effect transistor or a modulated doped FET. The field effect transistor according to claim 2, wherein the field effect transistor includes a depletion mode normally on transistor or an enhancement mode normally off transistor. The field effect transistor of claim 3, wherein the δ-doped layer is grown from an epitaxial material by molecular beam epitaxy, metal-organic chemical vapor deposition or a combination thereof. The field effect transistor of claim 4, wherein the thickness of the delta doped layer is 1 to 2 single layers thick and 0.5 to 1.2 nm grown by the molecular beam epitaxy. The field effect transistor of claim 4, wherein the thickness of the delta doped layer is grown by the metal organic chemical vapor deposition to be 1 to several single layer thicknesses. The field effect transistor of claim 4, wherein the epitaxial material is GaAs material. The field effect transistor of claim 4, wherein the delta doped layer is inserted into the wide concave region of the wide concave layer. The field effect transistor of claim 8, wherein the wide concave layer includes a first layer and a second layer, and the first layer is located on the upper surface of the delta doped layer and the wide concave layer. between the surfaces, and the second layer is between the lower surface of the delta doped layer and the lower surface of the wide concave layer, and the thickness of the first layer is greater than or equal to the thickness of the second layer. The field effect transistor according to claim 9, wherein the material of the first layer and the second layer is n-type AlGaAs. The field effect transistor as described in claim 9, wherein the thickness of the first layer is 10~20nm; the thickness of the second layer is 1~10nm, the doping species is Si, and the Si doping concentration is 1~ 5e17cm-3. The field effect transistor of claim 9, wherein the thickness of the first layer is 9 nm; the thickness of the second layer is 1 nm, the doping species is Si, and the Si doping concentration is 3e17cm-3. The field effect transistor of claim 9, wherein the gate metal contact is sequentially formed with Ti-Pt-Au, Ti-Pt-Au-Ti on the surface of the Schott base layer in the narrow concave area. , Ti-Mo-Au, Ti-Mo-Au-Ti, Ti-Pd-Au or Ti-Pd-Au-Ti. The field effect transistor according to claim 8, wherein the gate metal contact is sequentially formed on the surface of the Schott base layer in the narrow concave area by Pt-Ti-Pt-Au, Pt-Ti-Pt -Au-Ti, Pt-Ti-Mo-Au, Pt-Ti-Mo-Au-Ti, Pt-Ti-Pd-Au or Pt-Ti-Pd-Au-Ti and perform heat treatment to mix the A Pt layer is bonded to the material of the second semiconductor structure from the gate metal contact below the upper surface of the Schottky layer in the narrow recessed region from the second semiconductor structure. The field effect transistor of claim 4, wherein the delta doped layer is inserted between the narrow concave region and the lower surface of the Schottky layer, and the gate metal contact is in the narrow concave region. The surface above the Schott base layer forms Pt-Ti-Pt-Au, Pt-Ti-Pt-Au-Ti, Pt-Ti-Mo-Au, Pt-Ti-Mo-Au-Ti, and Pt-Ti-Pd in sequence. -Au or Pt-Ti-Pd-Au-Ti, and perform heat treatment to mix the materials of the first Pt layer and the second semiconductor structure, and bond from the gate metal contact to the second semiconductor structure to the narrow Below the upper surface of the Schottky layer in the concave region, below the delta doped layer and within the narrow concave region. The field effect transistor of claim 1, wherein the second semiconductor structure further includes a second etching stop layer disposed between the wide concave layer and the ohmic contact layer. The field effect transistor of claim 16, wherein the material of the Schottky layer is n-type AlGaAs; the material of the first etching stop layer is n-type InGaP or n-type AlAs; the material of the wide concave layer is n-type Type AlGaAs; the material of the delta doped layer is n-type GaAs or n-type AlGaAs; the material of the second etching stop layer is n-type InGaP or n-type AlAs; the material of the ohmic contact layer is n-type GaAs or n-type InGaAs , or a combination thereof. The field effect transistor of claim 16, wherein the thickness of the Schottky layer is 5~20nm, the doping species is Si, and the Si doping concentration is 1~3e17cm-3; the first etching stop layer is The thickness is 5nm, the doping species is Si and the Si doping concentration is greater than 1e19cm-3; the thickness of the delta doped layer is 1ML, the doping species is Si and the Si doping concentration is 0.5~1.5e12cm-2; the The thickness of the second etching stop layer is 5nm, the doping species is Si, and the Si doping concentration is greater than 1e19cm-3; the thickness of the ohmic contact layer is 20~120nm, the doping species is Si, and the Si doping concentration is greater than 5e18cm -3. The field effect transistor of claim 16, wherein the thickness of the Schottky layer is 10 nm, the doping species is Si, and the Si doping concentration is 3e17cm-3; the thickness of the first etching stop layer is 5nm, the doping species is Si and the Si doping concentration is greater than 1e19cm-3; the thickness of the delta doping layer is 1ML, the doping species is Si and the Si doping concentration is 1.0e12cm-2; the second etching The thickness of the stop layer is 5nm, the doping species is Si, and the Si doping concentration is greater than 1e19cm-3; the thickness of the ohmic contact layer is 50nm, the doping species is Si, and the Si doping concentration is greater than 5e18cm-3.

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