TWI828185B - Three-dimensional convolution device and three-dimensional convolution method - Google Patents

Abstract

A three-dimensional convolution method includes the following operations: performing a dimeson transposing operation on input data to consecutively arrange elements of the input data in depth and channel dimensions, in order to generate first data; performing a convolution on the first data and second data that corresponds to first weight data in blocks, in order to generate arithmetic data; and rearranging the arithmetic data according to an original dimensional format of the input data to generate output data.

Description

Three-dimensional convolution operation device and three-dimensional convolution operation method

This case relates to a convolution operation device, in particular to a three-dimensional convolution operation device and its method that performs a three-dimensional convolution operation by reordering the data dimension form.

Convolution operations are commonly used in artificial neural network models to determine whether multiple data have similar features. In the prior art, when calculating the three-dimensional convolution operation, multiple data values in the depth dimension and the channel dimension are accumulated. In the existing data format, multiple data values in the depth dimension and multiple data values in the channel dimension are stored in memory dispersedly. In this way, the complexity of the three-dimensional convolution operation will become higher. In addition, when performing a three-dimensional convolution operation, the convolution operation device needs to spend more time to read out multiple scattered data values, resulting in a low efficiency of the convolution operation device in accessing data, which makes the three-dimensional convolution operation more difficult. Processing efficiency is poor.

In some embodiments, one of the purposes of the present invention is to provide a three-dimensional convolution operation device and method that can improve the processing efficiency of the convolution operation, so as to improve the shortcomings of the previous technology.

In some implementations, the three-dimensional convolution operation method includes the following operations: performing dimensional conversion on the input data to continuously arrange multiple elements of the input data in the depth dimension and channel dimension together to generate a first data; Perform a convolution operation on the first data and a second data corresponding to the first weight data in blocks to generate an operation data; and reorder the operation data according to the original dimension form of the input data to generate an operation data. Output data.

In some implementations, the three-dimensional convolution operation device includes a buffer, a direct memory access circuit, a dimension switching circuit, and a convolution operation circuit. The direct memory access circuit reads input data from an external memory and stores the input data into the buffer. The dimension switching circuit reads the input data from the buffer and performs dimension conversion on the input data to continuously arrange multiple elements of the input data in the depth dimension and channel dimension together to generate a first data. The convolution operation circuit performs a convolution operation on the first data and a second data corresponding to a first weight data in blocks to generate an operation data. The dimension switching circuit further reorders the operation data according to an original dimensional form of the input data to generate an output data.

Regarding the characteristics, implementation and functions of this case, the preferred embodiments are described in detail below with reference to the drawings.

All words used in this article have their ordinary meanings. The definitions of the above words in commonly used dictionaries, and the use examples of any of the words discussed here in the content of this case are only examples and should not limit the scope and meaning of this case. Likewise, this case is not limited to the various embodiments shown in this specification.

As used in this article, "coupling" or "connection" can refer to two or more components that are in direct physical or electrical contact with each other, or that are in indirect physical or electrical contact with each other. It can also refer to two or more components. Components interact or act with each other. As used herein, the term "circuit" may refer to a device consisting of at least one transistor and/or at least one active and passive component connected in a certain manner to process signals.

In some embodiments, one of the goals of this approach is to allow the direct access memory circuit to read the input data and weight data more efficiently by reordering the dimensional form of the data, thereby improving the overall efficiency of the convolution operation.

Figure 1 is a schematic diagram of a three-dimensional convolution operation device 100 drawn according to some embodiments of the present application. In some embodiments, the three-dimensional convolution operation device 100 can be controlled by a computing platform (running on at least one computer host). In some embodiments, the three-dimensional convolution operation device 100 may include a processor (not shown), and other circuits in the three-dimensional convolution operation device 100 may be controlled by the processor.

The three-dimensional convolution operation device 100 includes a direct memory access circuit 110 , a buffer 120 , a dimension exchange circuit 130 and a convolution operation circuit 140 . The direct memory access circuit 110 can read the input data DIN and the weight data DW1 from the external memory 100A, and store the above two data in the buffer 120 . In some embodiments, the external memory 100A may be (but is not limited to) dynamic random access memory. In some embodiments, buffer 120 may be implemented by, but is not limited to, static random access memory.

In some embodiments, the convolution operation performed by the three-dimensional convolution operation device 100 is a three-dimensional convolution operation. Correspondingly, the input data DIN can be a five-dimensional tensor, and its original dimension form is a five-dimensional form. For example, the arrangement order of the original dimension form can be expressed as (N, Di, Hi, Wi, Ci), where N is the batch (batch) and can be the dimension value of the highest dimension in the input data DIN, Di is the depth dimension, Hi is the height dimension, Wi is the width dimension, and Ci is the channel dimension. For example, in the example of Figure 3 described below, the original dimension form (N, Di, Hi, Wi, Ci) of the input data DIN is (1, 3, 2, 2, 5), which represents the depth dimension of the input data DIN. The number of elements (or data values) is 3), the number of elements in the height dimension is 2, the number of elements in the width dimension is 2, and the number of elements in the channel dimension is 5. Similarly, the original dimension form of weight data DW1 can be expressed as (Dk, Hk, Wk, Ck, Co), where Dk is the depth dimension, Hk is the height dimension, Wk is the width dimension, C is the channel dimension, and Co is the weight The dimension value of the highest dimension of data DW1 (which is the same as the value of the channel dimension of output data DO).

The dimension exchange circuit 130 reads the input data DIN and the weight data DW1 from the buffer 120, and performs dimension exchange on the input data DIN according to a preset dimension form (which can be standardized by the computing platform), so as to convert the input data DIN in the depth dimension and channel Multiple elements in the dimension are continuously arranged together to generate data D1, and store the data D1 in the buffer 120. In some embodiments, the dimension exchange circuit 130 further performs dimension exchange on the weight data DW1 according to a preset dimension form to continuously arrange multiple elements of the weight data DW1 in the depth dimension and the channel dimension together to generate data D2, and Store data D2 in buffer 120. The direct memory access circuit 110 can read data D1 and data D2 from the buffer 110 and transfer the data to the external memory 100A. Through the above operations, the input data DIN in the original dimension form and the weight data DW1 in the original dimension form will be reordered into data D1 in the default dimension form and data D2 in the default dimension form respectively. In this way, the efficiency of the convolution operation can be improved. The operation of dimensional form conversion will be described in detail later with reference to Figure 3 . In some embodiments, dimension switching circuit 130 may be implemented by data processing circuitry executing specific processes or software. In some embodiments, if the weight data DW1 is constant data, the computing platform can store the data D2 corresponding to the weight data DW1 in the external memory 100A in advance to further accelerate the processing efficiency of the convolution operation.

The direct memory access circuit 110 can read data D1 and data D2 from the external memory 100A into the buffer 120 in blocks. The convolution operation circuit 140 can read data D1 and data D2 from the buffer 120 and perform convolution operations on the data D1 and data D2 in blocks to generate operation data DC. In some embodiments, the computing platform (or the processor of the convolution operation device 100) divides the data D1 and the data D2 into Multiple data blocks. In this way, the computing platform (or the processor of the three-dimensional convolution computing device 100) can control the direct access memory circuit 110 to sequentially read the data blocks of the data D1 and the data blocks of the data D2 into the buffer 120, and The convolution operation circuit 140 is controlled to sequentially read out the data blocks of the data D1 and the data blocks of the data D2 from the buffer 120 and perform the convolution operation block by block. After the convolution operation circuit 140 completes the convolution operation of all data blocks, the convolution operation circuit 140 can generate the operation data DC and store it in the external memory 100A through the buffer 120 and the direct memory access circuit 110 . In some embodiments, the convolution operation circuit 140 may be implemented by a digital signal processing circuit.

The dimension exchange circuit 130 can read the operation data DC through the direct memory access circuit 110 and the buffer 120, and reorder the operation data DC according to the original dimension form of the input data DIN to generate the output data DO. The dimension switching circuit 130 can transfer the output data DO to the external memory 100A via the buffer 120 and the direct memory access circuit 110 . In this way, other devices in the computing platform can correctly access the output data DO for subsequent applications.

Figure 2 is a flow chart of a three-dimensional convolution operation method 200 according to some embodiments of this case. In some embodiments, the three-dimensional convolution operation method 200 may be executed by (but not limited to) the three-dimensional convolution operation device 100 of FIG. 1 . In order to easily explain the relevant operations of the three-dimensional convolution operation device 100, please refer to FIG. 1 and FIG. 2 together.

In operation S205, dimension exchange is performed on the input data to continuously arrange multiple elements of the input data in the depth dimension and the channel dimension, thereby generating first data. In operation S210, the weight data is dimensionally exchanged to continuously arrange multiple elements of the weight data in the depth dimension and the channel dimension together to generate second data. As mentioned above, the direct memory access circuit 110 can read the input data DIN and the weight data DW1 from the external memory 100A, and store these data in the buffer 120 . The dimension switching circuit 130 can read the data DIN and the weight data DW1 from the buffer 120, and continuously arrange the multiple elements of the input data DIN in the depth dimension and the channel dimension together to generate the data D1, and put the weight data DW1 in Multiple elements in the depth and channel dimensions are continuously arranged together to generate data D2. Then, the dimension exchange circuit 130 transfers the data D1 and the data D2 to the external memory 100A via the buffer 120 and the direct memory access circuit 110 .

Figure 3 is a schematic diagram of performing dimension exchange on the input data DIN in Figure 1 to generate data D1 according to some embodiments of this case. As mentioned before, the original dimensional form of the input data DIN can be expressed as (N, Di, Hi, Wi, Ci). In the example in Figure 3, the original dimension form (N, Di, Hi, Wi, Ci) is (1, 2, 3, 2, 5). In other words, the input data DIN can be divided into three data groups in the height dimension Hi (ie, multiple data corresponding to Hi=0, 1, 2). Each data group can be further divided into two sub-data groups in the width dimension Wi (that is, multiple data corresponding to Wi=0, 1), and each sub-data group can be further divided in the depth dimension Di. It is divided into two pieces of data (that is, multiple data corresponding to Di=0, 1), and each piece of data contains 5 elements (or called data value; that is, corresponding to Ci=5). Specifically, the input data DIN includes multiple pieces of data D000, D001, D010, D011,..., D210 and D211. Data D000 represents that its corresponding height dimension Hi, width dimension Wi and depth dimension Di are all 0, and data D001 represents The corresponding height dimension Hi, width dimension Wi and depth dimension Di are 0, 0 and 1 in order. By analogy, it should be possible to understand the correspondence between the above-mentioned multiple pieces of information and their original dimensional forms.

As shown in Figure 3, data D1 can be generated by continuously arranging multiple elements of the input data DIN in the depth dimension Di and channel dimension Ci. The default dimension form of the data D1 includes batch, The height dimension, width dimension, depth dimension and channel dimension can be noted in sequence as (N, H, W, D, C). Among them, different from the original dimension form of the input data DIN, in the default dimension form, depth Dimension D and channel dimension C are adjacent settings. Through the aforementioned dimension exchange, it can be seen that the multiple pieces of data in data D1 (ie, data D000, D001, D010, D011,..., D210 and D211) are continuously arranged. In other words, these data can be continuously stored in the external memory 100A (and/or the buffer 120). In this way, during the convolution operation, the direct memory circuit 110 can continuously read out multiple pieces of data in the data D1 from the external memory 100A to perform the convolution operation.

To explain it another way, in the two-dimensional convolution operation, the convolution kernel (equivalent to the weight data DW1) slides in the width and height dimensions of the input data and multiplies and adds corresponding multiple elements in the channel dimension at the same time. Operation to produce the result of the convolution operation. In contrast, in a three-dimensional convolution operation, the convolution kernel will further perform multiplication and addition operations with corresponding multiple elements in the depth dimension of the input data to generate a convolution operation result. Since the three-dimensional convolution operation accumulates in both the depth dimension and the channel dimension, multiple elements in the depth dimension and channel dimension in the input data DIN can be continuously arranged together to generate data D1. In this way, the three-dimensional convolution operation can be simplified into an operation similar to the two-dimensional convolution operation, thereby reducing the complexity of the three-dimensional convolution operation and increasing the processing efficiency.

Specifically, during the convolution operation, the convolution operation circuit 140 can continuously read two pieces of data in the data D1 through the direct memory access circuit 110 and the buffer 120 to perform a convolution operation. For example, the two pieces of data can be data D000 and D0001, which contain multiple (for example, 10) elements corresponding to different depths (Di is 0 or 1), and these elements correspond to the same width (Wi is 0). with the same height (Hi is 0). Through dimension exchange and continuous reading, not only can multiple pieces of data be continuously arranged together, but the number of depth dimensions can also be effectively reduced. For example, the dimension form (N, H, W, D, C) presented by data D1 during the continuous reading process is equivalent to (1, 3, 2, 1, 10), in which the number of dimensions of the depth dimension D is equivalent The ground drops to 1, and the dimension number of the channel dimension becomes 10. In this way, the number of elements read by the direct memory access circuit 110 each time can be increased, thereby improving the working efficiency of the direct memory access circuit 110, thereby improving the calculation efficiency of the convolution operation. Figure 3 only takes the input data DIN and data D1 as an example. It should be understood that the same operations in Figure 3 are also applicable to the weight data DW1 and data D2 (or the weight data DW2 and data D3 mentioned later), so here No more details will be given.

Continuing to refer to Figures 1 and 2, in operation S215, the first data and the second data are each divided into a plurality of data blocks according to the capacity of the buffer. In operation S220, one data block among the plurality of data blocks corresponding to the first data is read into the buffer. In operation S225, one data block among the plurality of data blocks corresponding to the second data is read into the buffer. In operation S230, a convolution operation is performed according to a plurality of data blocks stored in the buffer to generate part of the operation data. In operation S235, the part of data is stored in the external memory.

As mentioned above, the computing platform (or the processor of the convolution computing device 100) can divide the data D1 and the data D2 into multiple data according to the access bandwidth, the capacity of the buffer 120, the size of the data D1 and the size of the data D2. data block. In some embodiments, the segmented data blocks meet the following conditions: the value of the channel dimension of data D1 is equal to the value of the channel dimension of data D2; and the sliding (or offset) value of data D2 on the channel dimension The value is equal to the channel dimension of the output data DO, but this case is not limited to this. After dividing the data D1 and the data D2 into multiple data blocks, the direct memory access circuit 110 can read the data D1 and the data D2 into the buffer 120 in blocks (that is, reading one data block of the data D1 at a time). and a data block of data D2 to the buffer 120) to provide these data blocks to the convolution operation circuit 140 to perform a convolution operation and generate part of the operation data DC (equivalent to the result of the convolution operation) ). The direct memory access circuit 110 can read the part of the data from the buffer 120 and transfer it to the external memory 100A. In some embodiments, data D1 and data D2 can be divided into multiple data blocks through existing scheduling algorithms or block convolution algorithms.

FIG. 4A is a schematic diagram of drawing the block data D1 according to some embodiments of the present case. In Figure 4A, a square in the channel dimension Ci represents a tensor data in the data D1. Since the channel dimension Ci and the depth dimension Di are merged into the same dimension (in this example, the value of the channel dimension Ci is 8), the data D1 is divided into blocks based on the dividing line BL1 (represented by a dotted line) in this dimension, and in the height dimension Hi and the width dimension Wi are divided into blocks based on the dividing line BL2 and the dividing line BL3 (indicated by a dotted line) respectively. In this way, the data D1 can be divided into 16 data blocks. For easy understanding, the corresponding arrangements of the four data blocks are shown with dots and slashes in FIG. 4A , and the positions of the remaining data blocks can be deduced by analogy. In practical applications, the size of the data D1 is usually larger than the capacity of the buffer 120 . Therefore, the direct memory access circuit 110 can read a data block of the data D1 into the buffer 120 in blocks for the convolution operation circuit 140 to perform the convolution operation.

Figure 4B is a schematic diagram of drawing the block data D2 according to some embodiments of the present case. In this example, the data D2 is divided into multiple data blocks based on the dividing line BL4 (drawn with a dotted line) in the channel dimension Ck (or the depth dimension Ck; the two are merged into the same dimension). Since the size of the data D2 is usually small, it does not need to be further divided in the height dimension Hk and the width dimension Wk in this example, but this case is not limited to this. For ease of understanding, the corresponding arrangements of multiple data blocks are shown with dots and slashes in FIG. 4B . The direct memory access circuit 110 may read a data block of the data D2 into the buffer 120 in blocks for the convolution operation circuit 140 to perform the convolution operation.

Continuing to refer to FIG. 2 , in operation S240, it is confirmed whether the convolution operation is completed. If the convolution operation is completed (that is, all data blocks are calculated), operation S245 is performed. Or, if the convolution operation is not completed, perform operation S215 again to read the next data block of data D1 and data D2 to continue performing the convolution operation. By repeating the above steps, the complete calculation data DC can be obtained. In operation S245, it is confirmed whether the next layer network is still a convolution operation. If the network of the next layer is still a convolution operation, perform operation S210 again, and use the aforementioned multiple operations to perform the convolution operation of the next layer again. The description of operation S245 will be described later with reference to FIG. 5A and FIG. 5B . Or, if the next layer network is not a convolution operation, perform operation S250. In operation S250, the operation data is reordered according to the original dimension form to generate output data.

For example, if the next layer network does not perform convolution operation, the direct access memory circuit 110 can read the operation data DC from the external memory 100A and transfer the operation data DC to the buffer 120 . The dimension switching circuit 130 can read the operation data DC from the buffer 120, reorder the operation data DC according to the original dimension form of the input data DIN to generate the output data DO, and store the output data DO in the buffer 120. The direct access memory circuit 110 can read the output data DO from the buffer 120 and transfer it to the external memory 100A. In this way, the computing platform or other devices in the system can use the output data DO to perform subsequent data processing. In other words, by operating S250, the dimensional form of the output data DO can be restored to the original dimensional form suitable for the computing platform, so that other networks in the neural network model can correctly use the output data DO.

The multiple operations of the above three-dimensional convolution operation method 200 are only examples, and are not limited to be performed in the order in this example. Without violating the operation mode and scope of each embodiment of the present application, various operations under the three-dimensional convolution operation method 200 can be appropriately added, replaced, omitted, or performed in a different order (for example, they can be performed simultaneously or partially simultaneously. implement).

FIG. 5A is a data flow diagram illustrating the operation of a single convolution operation layer according to some embodiments of the present invention. In this example, the neural network model run by the three-dimensional convolution operation device 100 includes a single convolution layer (that is, the aforementioned convolution operation includes a single convolution operation layer). In operation S501, the input data DIN is dimensionally exchanged (that is, multiple elements of the input data DIN in the depth dimension and the channel dimension are continuously arranged together) to generate data D1. In operation S502, the weight data DW1 is dimensionally exchanged (that is, multiple elements of the weight data DW1 in the depth dimension and the channel dimension are continuously arranged together) to generate data D2. In operation S503, a single convolution operation layer operation is performed on the data D1 and the data D2 in blocks to generate operation data DC (equivalent to operations S215 to S240 in Figure 2). In operation S504, the operation data DC is reordered according to the original dimension form to generate the output data DO.

For the multiple operations in FIG. 5A , reference can be made to the aforementioned description of the multiple operations in FIG. 2 , so the details are not repeated here. As mentioned above, in this example, the convolution operation only includes one convolution operation layer, so after the operation S503 is performed, the dimensions of the operation data DC can be restored according to the original dimension form to generate the output data DO.

FIG. 5B is a data flow chart for executing operations of multiple convolutional operation layers according to some embodiments of the present case. Compared with FIG. 5A , in the example of FIG. 5B , the neural network model run by the three-dimensional convolution operation device 100 includes a multi-layer convolution network. For example, the aforementioned convolution operation includes a first convolution operation layer and a second convolution operation layer. Convolutional operation layer.

In operation S511, dimension exchange is performed on the input data DIN to generate data D1. In operation S512, dimension exchange is performed on the weight data DW1 to generate data D2. In operation S513, the operation of the first convolution operation layer is performed on the data D1 and the data D2 in blocks to generate temporary data DC' (which can be stored in the buffer 120 of FIG. 1). In operation S514, the weight data DW2 is dimensionally exchanged (that is, multiple elements of the weight data DW2 in the depth dimension and the channel dimension are continuously arranged together, where the weight data DW2 is equivalent to the convolution kernel of the second convolution layer) to Data D3 is generated (which can be stored in the external memory 100A of FIG. 1 and transferred to the buffer 120 via the direct memory read circuit 110 ). In operation S515, the operation of the second convolution operation layer is performed on the temporary data DC' and the data D3 in blocks to generate the operation data DC. In operation S516, the operation data DC is reordered according to the original dimension form to generate the output data DO. For the multiple operations of FIG. 5B , reference can be made to the aforementioned description of the multiple operations of FIG. 2 , so the details are not repeated here. For example, operations S513 and S515 may refer to the description of operations S215 to S240 in FIG. 2 . In some other embodiments, if the weight data DW2 is constant data, the computing platform can store the data D3 corresponding to the weight data DW2 in the external memory 100A in advance.

As mentioned before, in this case the convolution operation consists of two convolution operation layers. Therefore, the calculation result obtained through the first convolution operation layer (i.e., the temporary data DC’) can be directly input to the second convolution operation layer without reordering the dimensions. In other words, in a neural network model containing multiple convolutional operation layers, it can be set to reorder the calculation results of the last convolutional operation layer (in this case, the second convolutional operation layer) according to the original dimensional form ( That is, the operation data DC) is used to obtain the output data DO without having to restore the results obtained through each convolutional operation layer back to the original dimensional form. In this way, the overall processing efficiency of the convolution operation can be further accelerated.

The above-mentioned embodiments are described using three-dimensional convolution operations, but the present case is not limited to this. It should be understood that the operation of reordering the dimensions of the data can be generalized to higher-dimensional convolution operations.

In summary, the three-dimensional convolution operation device and the three-dimensional operation method in some embodiments of the present application can reorder the dimensional form of data to improve the access efficiency of the direct memory circuit. Furthermore, through the above reordering, the complexity of the three-dimensional convolution operation can be reduced, thereby allowing the three-dimensional convolution device to implement the three-dimensional convolution operation by performing operations similar or identical to the two-dimensional convolution operation. In this way, the processing efficiency of three-dimensional convolution operations can be improved.

Although the embodiments of this case are as described above, these embodiments are not intended to limit this case. Those with ordinary knowledge in the technical field can make changes to the technical features of this case based on the explicit or implicit contents of this case. All these changes All may fall within the scope of patent protection sought in this case. In other words, the scope of patent protection in this case must be determined by the scope of the patent application in this specification.

100: Three-dimensional convolution operation device 100A: External memory 110: Direct memory access circuit 120:Buffer 130:Dimension switching circuit 140: Convolution operation circuit 200: Three-dimensional convolution operation method BL1~BL4: dividing line C, Ci, Ck, Co: channel dimensions D000, D001, D010, D011, D100, D101: Information D110, D111, D200, D201, D210, D211: Information D1~D3: information DC: calculation data DC’: Temporarily stored data DIN: input data DO: Output data DW1, DW2: weight data D, Di, Dk: depth dimension, H, Hi, Hk: height dimension S205, S210, S215, S220, S225, S230, S235, S240, S245, S250: Operation S501~S504, S511~S516: Operation W, Wi, Wk: width dimension

[Figure 1] is a schematic diagram of a three-dimensional convolution operation device drawn according to some embodiments of this case; [Figure 2] is a flow chart of a three-dimensional convolution operation method according to some embodiments of this case; [Figure 3] is a schematic diagram of dimensional exchange of the input data in Figure 1 to generate the first data according to some embodiments of this case; [Figure 4A] is a schematic diagram of drawing the first data divided into blocks according to some embodiments of this case; [Figure 4B] is a schematic diagram of drawing the second data divided into blocks according to some embodiments of this case; [Figure 5A] is a data flow chart for executing operations of a single convolutional operation layer according to some embodiments of this case; and [Figure 5B] is a data flow chart for executing operations of multiple convolutional operation layers according to some embodiments of this case.

200: Three-dimensional convolution operation method S205, S210, S215, S220, S225, S230, S235, S240, S245, S250: Operation

Claims (11)

A three-dimensional convolution operation method, including: Perform dimension exchange on an input data to continuously arrange a plurality of elements of the input data in the depth dimension and channel dimension together, thereby generating a first data; Perform a convolution operation on the first data and a second data corresponding to a first weight data in blocks to generate an operation data; and Reordering the operation data according to the original dimensional form of the input data to generate an output data. For example, the three-dimensional convolution operation method of claim 1, wherein the convolution operation is performed on the first data and the second data in blocks to generate the operation data includes: A plurality of elements corresponding to different depths in the first data are continuously read to perform the convolution operation, wherein the elements correspond to the same width and the same height. For example, the three-dimensional convolution operation method of request item 1 further includes: Dimension exchange is performed on the first weight data to continuously arrange a plurality of elements of the first weight data in the depth dimension and the channel dimension together, thereby generating the second data. The three-dimensional convolution operation method of claim 1, wherein the convolution operation includes a first convolution operation layer and a second convolution operation layer, and the first data is read in blocks and corresponds to a first weight A second data of data is used to perform a convolution operation to generate the operation data including: Perform the operation of the first convolution operation layer on the first data and the second data in blocks to generate temporary data; Perform dimension exchange on a second weight data to continuously arrange a plurality of elements of the second weight data in the depth dimension and channel dimension together to generate a third data; and Perform the operation of the second convolution operation layer on the temporarily stored data and the third data in blocks to generate the operation data. A three-dimensional convolution operation device, including: a buffer; A direct memory access circuit reads input data from an external memory and stores the input data into the buffer; A one-dimensional switching circuit that reads the input data from the buffer and performs dimension switching on the input data to continuously arrange a plurality of elements of the input data in the depth dimension and the channel dimension together to generate a first data; as well as a convolution operation circuit that performs a convolution operation on the first data and a second data corresponding to a first weight data in blocks to generate an operation data; Wherein, the dimension switching circuit further reorders the operation data according to an original dimension form of the input data to generate an output data. The three-dimensional convolution operation device of claim 5, wherein the external memory further stores the second data, and a plurality of elements of the second data in the depth dimension and the width dimension are continuously arranged together. As claimed in claim 5, the three-dimensional convolution operation device, wherein the direct memory access circuit further reads the first weight data from the external memory to the buffer, and the dimension exchange circuit further reads the third weight data from the buffer. A weighting data and performing dimension exchange on the first weighting data to continuously arrange a plurality of elements of the first weighting data in the depth dimension and the channel dimension together to generate the second data. As claimed in claim 5, the three-dimensional convolution operation device, wherein the convolution operation circuit continuously reads a plurality of elements corresponding to different depths in the first data to perform the convolution operation, wherein these elements correspond to the same width and same height. The three-dimensional convolution operation device of claim 5, wherein the convolution operation includes a first convolution operation layer and a second convolution operation layer, and the convolution operation circuit performs block processing on the first data and the third convolution operation layer. Perform the operation of the first convolution operation layer on the two data to generate a temporary storage data, and perform the operation of the second convolution operation layer on the temporary storage data and a third data corresponding to a second weight data in blocks. Compute to generate the computation data. The three-dimensional convolution operation device of claim 9, wherein the direct memory access circuit further reads the second weight data from the external memory to the buffer, and the dimension exchange circuit further reads the second weight data from the buffer. The second weight data is dimensionally exchanged and a plurality of elements of the second weight data in the depth dimension and the channel dimension are continuously arranged together to generate the third data. The three-dimensional convolution operation device of claim 5, wherein the first data generated by the dimension exchange circuit is stored in the external memory through the buffer and the direct memory access circuit, and the convolution operation circuit passes through The direct memory access circuit and the buffer read the first data in blocks.