TWI827169B - Manufacturing method of electronic device - Google Patents

Abstract

The present disclosure discloses a manufacturing method of an electronic device. A seed layer is formed on a substrate. After patterning the seed layer to form a plurality of sub-seed layers and a plurality of conductive lines, a metal layer is formed on a plurality of the sub-seed layers. The sub-seed layers include a first sub-seed layer and a second sub-seed layer, and the first sub-seed layer and the second sub-seed layer are separated from each other.

Description

Manufacturing method of electronic device

The present disclosure relates to a manufacturing method of an electronic device, particularly a manufacturing method of an electronic device that can improve the electrical reliability of the electronic device.

In the manufacturing process of electronic devices, it is necessary to form conductive materials on the substrate. For example, the conductive materials can be formed on the substrate through an electroplating process. When electroplating copper, uneven plating solution, uneven current density or uneven electric field may cause uneven thickness of the electroplated copper layer, affecting the warpage of the substrate or further affecting the reliability of the electronic device.

In view of this, the art needs to continue to study the manufacturing method of electronic devices to improve the uneven thickness of the electroplating layer.

Some embodiments of the present disclosure provide a method of manufacturing an electronic device. First, a substrate is provided. Then, a seed layer is formed on the substrate. Next, the seed layer is patterned to form a plurality of sub-seed layers and a plurality of conductive lines. Continue to form a metal layer on at least one of the plurality of sub-seed layers. Wherein, the plurality of sub-seed layers include a first sub-seed layer and a second sub-seed layer, and the first sub-seed layer and the second sub-seed layer are separated from each other.

100: Electronic devices

110: Provide substrate

120: Forming a seed layer on the substrate

130: Patterning the seed layer to form multiple sub-seed layers and multiple conductive lines

140: Forming a metal layer on at least one of the plurality of sub-seed layers

150:Patterned metal layer

160: Forming an insulating layer

170: Form another set of seed layer and metal layer

180: Remove the substrate and release layer, form the bonding material, and make electrical connections with the chip

201:Substrate

202: Release layer

203:Seed layer

203’:Seed layer

204:Patterned photoresist layer

205:Metal layer

205’: Patterned metal layer

205A:Main area

205B:Main area

210: First sub-seed layer

210A: Main area

210A-1:Protrusion

210A-2:Protrusion

210A-3:Protrusion

210A-4:Protrusion

210A-5:Protrusion

210A-6:Protrusion

210A-7:Protrusion

210A-8:Protrusion

210B:Main area

210B-1:Protrusion

210B-2:Protrusion

210B-3:Protrusion

210B-4:Protrusion

210B-5:Protrusion

210B-6:Protrusion

210B-7:Protrusion

210B-8:Protrusion

210L-1A:Turning

210L-1B:Turning

220: Second sub-seed layer

220A: Surrounding area

220B: Surrounding area

220C: Surrounding area

220D: Surrounding area

220e: Blank area

220f: Blank area

220g: Blank area

220h: Blank area

230: Conductive thread

230D-1: Conductive thread

230D-2: Conductive thread

230D-3: Conductive thread

230D-4: Conductive thread

230D-5: Conductive thread

230D-6: Conductive thread

230D-7: Conductive thread

230D-8: Conductive thread

230L-1: Conductive thread

230L-2: Conductive thread

230L-3: Conductive thread

230L-4: Conductive thread

230L-5: Conductive thread

230L-6: Conductive thread

230L-7: Conductive thread

230L-8: Conductive thread

235: The third sub-seed layer

240: Routing

250: The first layer of line redistribution layer

260:Insulation layer

261:Open your mouth

270: The second layer of line redistribution layer

271:Seed layer

272:Metal layer

280:Joining materials

281: First joining material

282: Second joining material

290:Chip

291: First protective layer

292:Second protective layer

L1:Length

L2: length

L3: length

L4:Length

P1: interval

P2: interval

S: edge

FIG. 1 illustrates a flowchart of some embodiments of a method of forming an electronic device according to the present disclosure.

FIG. 2A is a schematic cross-sectional view of a substrate corresponding to the steps of FIG. 1 according to the method of forming an electronic device according to the present disclosure.

FIG. 2B is a schematic cross-sectional view of the substrate corresponding to the steps of FIG. 1 according to the method of forming an electronic device according to the present disclosure.

FIG. 2C is a schematic cross-sectional view of the substrate corresponding to the steps of FIG. 1 according to the method of forming an electronic device according to the present disclosure.

FIG. 2D is a schematic cross-sectional view of the substrate corresponding to the steps of FIG. 1 according to the method of forming an electronic device according to the present disclosure.

FIG. 2E is a schematic cross-sectional view of the substrate corresponding to the steps of FIG. 1 according to the method of forming an electronic device according to the present disclosure.

3 , 3A and 3B respectively illustrate a method for forming an electronic device according to the present disclosure, a top view of the substrate corresponding to FIG. 2A after removing the patterned photoresist layer and leaving a patterned seed layer.

4 and 4A are schematic top views of the substrate and its upper film layer corresponding to FIG. 2B according to the method of forming an electronic device according to the present disclosure.

The present disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in order to make it easy for readers to understand and for the simplicity of the drawings, many of the drawings in the present disclosure only depict a part of the electronic device. And certain elements in the drawings are not drawn to actual scale. In addition, the number and size of components in the figures are only for illustration and are not intended to limit the scope of the present disclosure.

Throughout this disclosure and the appended claims, certain words are used to refer to certain element. Those skilled in the art will understand that electronic device manufacturers may refer to the same component by different names. This article is not intended to differentiate between components that have the same function but have different names.

In the following description and claims, the words "including" and "include" are open-ended words, and therefore they should be interpreted to mean "including but not limited to...".

It should be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or directly connected to the other element or layer. to another element or layer, or there is an intervening element or layer between the two (indirect cases). In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present.

In some embodiments of the present disclosure, terms related to joining and connecting, such as "connection", "interconnection", etc., unless otherwise defined, may mean that two structures are in direct contact, or may also mean that two structures are not in direct contact. There are other structures located between these two structures. And the terms about joining and connecting can also include the situation where both structures are movable, or both structures are fixed. In addition, the terms "electrical connection" or "electrical coupling" include any direct and indirect means of electrical connection.

Although the terms first, second, third... may be used to describe various constituent elements, the constituent elements are not limited to these terms. This term is only used to distinguish a single component from other components in the specification. The same terms may not be used in the claims, but may be replaced by first, second, third... according to the order in which the elements are declared in the claims. Therefore, in the following description, a first constituent element may be a second constituent element in the claims.

It should be noted that the following embodiments can be replaced, reorganized, and mixed with technical features in several different embodiments without departing from the spirit of the present disclosure to complete other embodiments.

FIG. 1 illustrates a flowchart of some embodiments of a method of forming an electronic device 100 according to the present disclosure. 2A to 2E respectively illustrate a process diagram of a method of forming an electronic device according to the present disclosure, and The component structure is represented by a schematic cross-sectional view, and FIGS. 2A to 2E roughly correspond to the cross-sectional view of the flowchart shown in FIG. 1 . In the present disclosure, the electronic device 100 may include various electronic components, semiconductor packaging components, display devices, lighting devices, sensing devices, antenna devices, bendable electronic devices, spliced electronic devices, or flexible Electronic devices, etc., but this disclosure is not limited thereto. The electronic device 100 may also include semiconductor dies, or functional stacks formed by staggered stacks of multiple metal layers (copper layers and seed layers) and multiple insulating layers, such as redistribution layers (RDL). However, the present disclosure Not limited to this. "Flexible/bendable" here means that the material can be curved, bent, folded, rolled, flexible, stretched and /or other similar deformations to represent at least one of the above possible deformation methods, and "flexible/bendable" is not limited to the above-mentioned deformation methods. The antenna device may be a liquid crystal type antenna device or a non-liquid crystal type antenna device, and the sensing device may be a sensing device that senses capacitance, light, heat energy or ultrasonic waves, but is not limited thereto. In the present disclosure, electronic components may include passive components and active components, such as capacitors, resistors, inductors, diodes, thin film transistors, electrostatic discharge (ESD) protection components, etc. Diodes may include light emitting diodes or photodiodes. The light emitting diodes may include, for example, organic light emitting diodes (OLEDs), sub-millimeter light emitting diodes (mini LEDs), micro light emitting diodes (micro LEDs) or quantum dot light emitting diodes (quantum dots). dot LED), but not limited to this. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device of the present disclosure can be in any of the above-mentioned permutations and combinations, but is not limited thereto.

Please refer to FIG. 1 and compare FIGS. 2A to 2E , which are schematic structural cross-sectional views of a method of forming an electronic device 100 according to the present disclosure. The Z direction in FIG. 2A is the normal direction of the electronic device 100, or can be regarded as the stacking direction of multiple metal layers and insulating layers in the device, and the X direction is perpendicular to the Z direction. Step 110 in Figure 1 shows that a substrate 201 is first provided. The substrate 201 may be a supporting carrier plate used to support a combination of one or more electronic units, release layers, insulation layers, material layers and/or circuit layers. For example, in some embodiments, the substrate 201 may include organic materials, inorganic materials, or combinations thereof. Silicon, plastic, glass and other materials that require electroplating metal layers, but the present disclosure is not limited thereto. According to some embodiments, the substrate 201 may be a temporarily supported carrier. According to some embodiments of the disclosure, at least the release layer 202 may be stacked on the substrate 201, but the disclosure is not limited thereto. The release layer 202 can be a temporary adhesive layer that allows components such as multiple electronic units, insulation layers, material layers, and/or circuit layers to be temporarily attached to the substrate 201, and the substrate 201 can be separated from the above components when necessary. Release layer 202 may include any suitable adhesive material. In some embodiments, when it is necessary to separate the substrate 201 from the above-mentioned components, the release layer 202 can be processed by, for example, thermal cracking, laser removal, or other suitable methods, so that the substrate 201 is separated from the above-mentioned components. However, this disclosure does not Limited to this. In this embodiment, the release layer 202 can be formed entirely on the surface of the substrate 201 .

Next, step 120 in FIG. 1 shows providing a seed layer 203 on the substrate 201 . For example, the entire seed layer 203 can be formed on the substrate 201 so that subsequent conductive materials can be formed on the substrate 201 . The seed layer 203 may be a single layer or a multi-layer stack of inorganic materials. The material of the seed layer 203 may include conductive materials, such as titanium, copper, aluminum, zinc, platinum, combinations of the above and oxides/alloys thereof, or other suitable materials, but is not limited thereto. The seed layer 203 may be formed by sputtering, for example, but the present disclosure is not limited thereto. In some embodiments, an optional insulating layer (not shown) may be disposed between the seed layer 203 and the release layer 202 , but the present disclosure is not limited thereto.

Next, step 130 of FIG. 1 is performed to pattern the seed layer 203 to form a patterned seed layer including a plurality of specific patterns. In some embodiments, the photoresist layer 204 can be formed on the seed layer 203, so that the release layer 202 can be located between the seed layer 203 and the substrate 201, and the seed layer 203 can be located between the release layer 202 and the photoresist. between layers 204, but the present disclosure is not limited thereto. The photoresist layer 204 may include positive photoresist or negative photoresist. Positive photoresist is used as an example, but is not limited thereto. The photoresist layer 204 can be formed on the entire surface of the seed layer 203 first, and a patterning process is used to remove part of the photoresist layer 204 to pattern the photoresist layer 204 first, covering part of the seed layer 203 and exposing other parts. A portion of the seed layer 203 is shown in Figure 2A. The method of patterning the photoresist layer 204 is, for example, a photolithography etching process, but is not limited thereto. The patterned photoresist layer 204 can It is used to define a predetermined pattern of the seed layer 203. For example, the pattern may correspond to a predetermined pattern design of multiple sub-seed layers and multiple conductive lines. Next, the patterned photoresist layer 204 can be used as a mask to remove part of the seed layer 203 to perform the step of patterning the seed layer 203 to form a pattern including a plurality of sub-seed layers and a plurality of conductive line patterns. The seed layer 203'. For example, in some embodiments, in the presence of the patterned photoresist layer 204, etching may be used to remove the seed layer 203 that is not covered by the patterned photoresist layer 204 to obtain the patterned seed layer 203'. (As shown in FIG. 2B ), it can expose part of the release layer 202 . After completing the etching step, the patterned photoresist layer 204 can be removed, leaving the patterned seed layer 203'.

Please continue to refer to Figures 2A to 2E and Figure 3, Figure 3A and Figure 3B. 3 and 3B respectively illustrate two embodiments of the method of forming the electronic device 100 according to the present disclosure, corresponding to the substrate 201 in which the patterned photoresist layer 204 is removed and the patterned seed layer 203' is left in FIG. 2A. Schematic diagram from above. The X direction is perpendicular to the Y direction, and the X direction and the Y direction are respectively perpendicular to the Z direction shown in Figure 2A. Forming the patterned seed layer 203' on the substrate 201 may include forming a plurality of sub-seed layers and a plurality of conductive lines. For example, please refer to FIG. 3, FIG. 3A and FIG. 3B. In the top view (Z direction), the patterned seed layer 203' can have various shapes, such as rectangle, circle, square, triangle, line, The above combination or other suitable shapes, but not limited to this. In other words, the patterned seed layer 203' may include at least the first sub-seed layer 210 and the second sub-seed layer 220 and a plurality of conductive lines 230. However, this disclosure is not limited to this. According to some embodiments of the present disclosure, the first sub-seed layer 210 and the second sub-seed layer 220 may be separated from each other. Being separated from each other can be regarded as, for example, that the first sub-seed layer 210 and the second sub-seed layer 220 can be physically separated from each other and not connected, or can also be regarded as being separated by an appropriate distance from each other, but this disclosure does not This is the limit.

According to some embodiments of the present disclosure, the first sub-seed layer 210 may include at least one main region and at least one protruding part, for example, may include one or more main regions and one or more protruding parts. For example, in some embodiments, the first sub-seed layer 210 may include only one main region. Or as shown in FIG. 3 , the first sub-seed layer 210 may include two main areas (ie, main area 210A and main area 210B). embodiment, but the first sub-seed layer 210 of the present disclosure is not limited to two main areas, and may also include implementations with more than two main areas. According to some embodiments of the present disclosure, the second sub-seed layer 220 may include a plurality of peripheral areas, such as peripheral areas 220A, 220B, 220C, and 220D, but the disclosure is not limited thereto. For example, the peripheral area 220A, the peripheral area 220B, the peripheral area 220C, and the peripheral area 220D can be located at the edge of the substrate 201 respectively. The above "located at the edge of the substrate 201" can mean that in the top view (Z direction), the peripheral area 220A and the peripheral area 220B, peripheral area 220C, and peripheral area 220D are respectively adjacent to one edge (side) S of the substrate 201, or one side of each peripheral area 220A, peripheral area 220B, peripheral area 220C, and peripheral area 220D is substantially flush with each other. The edge S of the substrate 201 is not limited to the above. In some embodiments, the second sub-seed layer 220 may connect the electroplated electrode plate during the electroplating process.

θ

150°)，例如導角θ可以介於45°至135°(45°

θ

135°)，或是導角θ可以介於60°至120°(60°

θ

120°)，或是導角θ可以介於80°至100°(80°

θ

100°)，但本揭露不以此為限。舉例而言，可透過自動光學系統(Auto-Optical Inspection,AOI)檢測導角θ，當導角θ大於等於30°且小於150°時，有助於降低晶種層的電流密度，可以改善基板201邊緣電力線不均勻造成的電場不均勻，有利於提升其上電鍍層(例如電鍍銅層)的厚度 的均勻程度，所以有利於增進電子裝置100的電性可靠度。在一些實施方式中，一個或多個突出部也可以具有一鈍圓形，舉例而言，請參考圖3A，例如從上視圖觀之，一個或多個突出部210A-1、突出部210A-2、突出部210A-3、突出部210A-4、突出部210A-5、突出部210A-6、突出部210A-7、突出部210A-8、突出部210B-1、突出部210B-2、突出部210B-3、突出部210B-4、突出部210B-5、突出部210B-6、突出部210B-7、突出部210B-8可以分別包括弧形邊緣/邊角或弧形轉角等多種不同的實施方式，但本揭露不以此為限。當突出部具有鈍圓的形狀時，也有助於改善基板201邊緣電力線不均勻造成的電場不均勻，有利於提升電鍍層的厚度的均勻程度，所以也有利於增進電子裝置100的電性可靠度。在一些實施方式中，一個或多個突出部彼此間的形狀可以相同也可以不同。 According to some embodiments of the present disclosure, each main area may be connected to at least one protrusion, for example, one or more protrusions may extend outward from one main area. According to some embodiments of the present disclosure, each side of the main area may include at least one protrusion, for example, each side may include one or more protrusions. Figure 3 shows that the main area 210A includes protrusions 210A-1, protrusions 210A-2, protrusions 210A-3, protrusions 210A-4, protrusions 210A-5, protrusions 210A-6, protrusions 210A-7, Embodiment of protrusion 210A-8; main area 210B includes protrusion 210B-1, protrusion 210B-2, protrusion 210B-3, protrusion 210B-4, protrusion 210B-5, protrusion 210B-6, protrusion 210B-7 and protruding portion 210B-8, but the present disclosure is not limited thereto. According to some embodiments of the present disclosure, at least one of the plurality of protruding parts may have a leading angle, for example, one protruding part may independently have a leading angle θ. The lead angle θ of the protrusion can range from 30° to 150° (30°

θ

150°), for example, the lead angle θ can range from 45° to 135° (45°

θ

135°), or the lead angle θ can be between 60° and 120° (60°

θ

120°), or the lead angle θ can be between 80° and 100° (80°

θ

100°), but this disclosure is not limited to this. For example, the lead angle θ can be detected through an Auto-Optical Inspection (AOI). When the lead angle θ is greater than or equal to 30° and less than 150°, it helps to reduce the current density of the seed layer and improves the substrate. The uneven electric field caused by the uneven power lines at the edge of 201 is beneficial to improving the uniformity of the thickness of the electroplating layer (such as the electroplated copper layer) thereon, so it is beneficial to improve the electrical reliability of the electronic device 100 . In some embodiments, one or more protrusions may also have an obtuse shape. For example, please refer to FIG. 3A . For example, from a top view, one or more protrusions 210A-1, 210A- 2. Protruding portion 210A-3, protruding portion 210A-4, protruding portion 210A-5, protruding portion 210A-6, protruding portion 210A-7, protruding portion 210A-8, protruding portion 210B-1, protruding portion 210B-2, The protruding portions 210B-3, 210B-4, 210B-5, 210B-6, 210B-7, and 210B-8 can respectively include arcuate edges/corners or arcuate corners. Different implementations, but the present disclosure is not limited thereto. When the protrusion has a blunt round shape, it also helps to improve the uneven electric field caused by uneven power lines at the edge of the substrate 201, and helps to improve the uniformity of the thickness of the electroplating layer, so it also helps to improve the electrical reliability of the electronic device 100. . In some embodiments, the shape of one or more protrusions may be the same or different from each other.

Viewed from a top view, there is an interval between adjacent protrusions, which means that there is an interval between two adjacent extending sides of two adjacent protrusions on the same side of the substrate 201 along the X direction or the Y direction. the shortest distance on. According to some embodiments of the present disclosure, the spacing between adjacent protrusions can be variable and designed as needed, for example, they can be exactly the same, not exactly the same, or all different. For example, there is a gap P1 between two adjacent extending sides of the adjacent protruding portion 210A-1 and the protruding portion 210A-2 along the There is a gap P2 between two adjacent extended sides of the portion 210A-4 along the X direction or the Y direction. The length of the gap P1 may be the same as or different from the length of the gap P2. FIG. 3 illustrates an embodiment in which the length of the interval P1 is different from the length of the interval P2 (P1≠P2), but the disclosure is not limited thereto. Designing with different intervals between the protrusions can reduce the current density concentrated in the corners and improve the problem of uneven thickness of the electroplating layer.

(M-m)/M

0.15，或者同一個主要區連接的最長導電線的長度M與最短導電線的長度m之間的長度差異值可以不大於10%，也就是說0

(M-m)/M

0.10，或者同一個主要區連接的最長導電線的長度M與最短導電線的長度m之間的長度差異值可以不大於5%，也就是說0

(M-m)/M

0.05。導電線230長度的計算方式，可以是一條給定的導電線從第一子晶種層210到第二子晶種層220間沿著平行於X方向或Y方向上所有的長度的總和。圖3繪示主要區210A的連接導電線230L-1、導電線230L-2、導電線230L-3、導電線230L-4、導電線230L-5、導電線230L-6、導電線230L-7、導電線230L-8；主要區210B的連接導電線230D-1、導電線230D-2、導電線230D-3、導電線230D-4、導電線230D-5、導電線230D-6、導電線230D-7、導電線230D-8的實施例，但本揭露不以此為限。舉例而言，導電線230L-1可以包括轉折210L-1A與轉折210L-1B的實施例，但本揭露不以此為限。透過上述設計，可以降低電極板所提供的不同電流傳導至主要區的路徑差異，進而提升電鍍層的厚度均勻性或降低基板的翹曲。 According to some embodiments of the present disclosure, a plurality of conductive lines 230 may be disposed between the first sub-seed layer 210 and the second sub-seed layer 220 , for example, may be disposed on a plurality of protrusions of the first sub-seed layer 210 and the second sub-seed layer 220 as electrically connected conductive lines between the first sub-seed layer 210 and the second sub-seed layer 220. That is to say, one of the plurality of protrusions can pass through multiple At least one of the conductive lines 230 is electrically connected to the second sub-seed layer 220 . According to some embodiments of the present disclosure, the conductive line 230 may have a transition. The conductive lines 230 having turns help reduce the difference in length of different conductive lines at different locations. According to some embodiments of the present disclosure, the length difference between the conductive lines 230 at different positions may not be greater than 15%, or the length difference between the conductive lines 230 at different positions may not be greater than 10%, or the length difference between the conductive lines 230 at different positions may be no more than 10%. The length difference between the lines 230 may not be greater than 5%. For example, the length difference between the length M of the longest conductive line and the length m of the shortest conductive line connected to the same main area may not be greater than 15%, that is, 0

(Mm)/M

0.15, or the length difference between the length M of the longest conductive line and the length m of the shortest conductive line connected to the same main area can not be greater than 10%, that is to say 0

(Mm)/M

0.10, or the length difference between the length M of the longest conductive line and the length m of the shortest conductive line connected to the same main area can not be greater than 5%, that is to say 0

(Mm)/M

0.05. The length of the conductive line 230 can be calculated as the sum of all the lengths of a given conductive line from the first sub-seed layer 210 to the second sub-seed layer 220 parallel to the X direction or the Y direction. Figure 3 illustrates main area 210A connecting conductive lines 230L-1, 230L-2, 230L-3, 230L-4, 230L-5, 230L-6, 230L-7 , conductive wire 230L-8; main area 210B connects conductive wire 230D-1, conductive wire 230D-2, conductive wire 230D-3, conductive wire 230D-4, conductive wire 230D-5, conductive wire 230D-6, conductive wire 230D-7 and conductive wire 230D-8, but the present disclosure is not limited thereto. For example, the conductive line 230L-1 may include an embodiment of a turning point 210L-1A and a turning point 210L-1B, but the present disclosure is not limited thereto. Through the above design, it is possible to reduce the path difference in the conduction of different currents provided by the electrode plate to the main area, thereby improving the thickness uniformity of the electroplating layer or reducing the warpage of the substrate.

In some embodiments, a blank area, such as but not limited to a blank area, may be arranged between multiple adjacent peripheral areas, such as between adjacent peripheral areas 220A, 220B, 220C or 220D. 220e, blank area 220f, blank area 220g, blank area 220h. The blank area may represent an area on the substrate 201 where the patterned seed layer 203' is not provided, or it may also be considered that the substrate 201 may include a blank area and a patterned seed layer 203', but the disclosure is not limited thereto. . For example, in some embodiments , the blank area may be provided at the corner of the substrate 201 or between adjacent peripheral areas, but the disclosure is not limited thereto. The shape of the blank area may be determined based on the shape of the substrate 201 or the shape of the peripheral area. For example, the shape of the blank area may be a polygon, but the disclosure is not limited thereto. The design of the blank area can reduce the uneven thickness of the electroplating layer caused by the concentration of current density in the corners, and help maintain the electrical reliability of the electronic device.

According to some embodiments of the present disclosure, the patterned seed layer 203' may further include one or more third sub-seed layers 235. In some embodiments, the third sub-seed layer 235 may be disposed between adjacent first sub-seed layers. For example, one or more third sub-seed layers 235 may be located in adjacent ones of multiple main regions. between two main districts. The shape of the third sub-seed layer 235 may include a variety of different implementations such as polygons, arc-shaped edges, or arc-shaped corners, but the disclosure is not limited thereto. For example, as shown in FIG. 3B , the third sub-seed layer 235 may be disposed between two adjacent main areas of the first sub-seed layer 210 , such as the main area 210A and the main area 210B shown in FIG. 3B . between, but this disclosure is not limited to this. According to some embodiments of the present disclosure, the third sub-seed layer 235 may be connected to at least one of a plurality of conductive lines. According to some embodiments of the present disclosure, the first sub-seed layer 210 may be electrically connected to the third sub-seed layer 235 via at least one of a plurality of conductive lines, such as the protruding portion 210A- of the first sub-seed layer. 8 may be electrically connected to the third sub-seed layer 235 via conductive lines 230L-8. According to some embodiments, the third sub-seed layer 235 may be a current transfer portion, for example. According to some embodiments of the present disclosure, the third sub-seed layer 235 may be electrically connected to the second sub-seed layer 220 via at least one of a plurality of conductive lines. For example, the third sub-seed layer 235 may be electrically connected to the second sub-seed layer 220 via at least one of a plurality of conductive lines. 230D-3 is electrically connected to the second sub-seed layer 220A. The calculation method of the length of the conductive line when the third sub-seed layer 235 exists can be that a given conductive line runs parallel to the X direction or the Y direction from the first sub-seed layer 210 to the second sub-seed layer 220 The sum of all lengths passing through the third sub-seed layer 235. For example, please refer to FIG. 3B . The calculation of the length of the conductive line 230L-8 can be regarded as the sum of the length L1 + the length L2 + the length L3 + the length L4 (L1 + L2 + L3 + L4), but the disclosure is not limited thereto. Adding the third sub-seed layer 235 can reduce the impact of interruption of any conductive line during the turning process. to the electrical reliability of the electronic device 100 . Specifically, if the third sub-seed layer 235 is not provided, the line segment corresponding to the length L4 of the conductive line 230L-8 and the line segment corresponding to the length L3 may have a 90-degree turning point at the connecting turning point, and the turning point of the The line width is the line width of the conductive line, and the line width is very thin; and in this embodiment, the position of the third sub-seed layer 235 in FIG. 3B can overlap with the predetermined position at the turning point. The three sub-seed layer 235 replaces the turning point of the original conductive line which only has a thin line width, thereby improving the disconnection problem. Because the first sub-seed layer 210 can be electrically connected to the second sub-seed layer 230 through a conductive line 230, and the conductive line 230 can first pass through the third sub-seed layer 235, or the third sub-seed The layer 235 may overlap a portion of the conductive lines 230 (for example, the conductive lines 230L-8). Therefore, in some embodiments, the first sub-seed layer 210 and the third sub-seed layer 235 can also be regarded as passing through the conductive lines 230. electrically connected to the second sub-seed layer 230.

FIG. 2B is a schematic cross-sectional view of the substrate 201 corresponding to step 140 of FIG. 1 in the method of forming the electronic device 100 according to the present disclosure. 4 and 4A are schematic top views of the substrate 201 and its upper film layer corresponding to FIG. 2B. Step 140 in Figure 1 corresponds to that shown in Figure 2B. The metal layer 205 can be formed in the presence of the patterned seed layer 203'. For example, the metal layer 205 can be formed in at least one of the plurality of sub-seed layers through an electroplating step. On the one hand, the metal layer 205 can cover the patterned seed layer 203'. In some embodiments, the metal layer 205 can be selectively formed on one or more first sub-seed layers 210 such that the metal layer 205 can cover the one or more first sub-seed layers 210 and/or the second sub-seed layer 210 . Three seed crystal layers (not shown). In some embodiments, the method further includes forming a metal layer 205 on the plurality of conductive lines 230 to form a plurality of traces 240 . Or in some embodiments, the metal layer 205 is formed but the metal layer 205 does not cover the second sub-seed layer 220, so that from a top view, the substrate 201 includes the metal layer 205 covering the first sub-seed layer 210 and The second sub-seed layer 220 is exposed. The patterned seed layer 203' can also expose part of the release layer 202.

According to some embodiments of the present disclosure, the metal layer 205 may include at least one main area when viewed from above, for example, may include one or more main areas. FIG. 4 illustrates an embodiment of the electronic device 100 according to the present disclosure, in which the metal layer 205 includes a main region 205A. 4A illustrates an embodiment of the electronic device 100 according to the present disclosure. The metal layer 205 includes a main area 205A and a main area 205B. However, the metal layer of the present disclosure 205 is not limited to two main zones and may also include implementations with more than two main zones. The main area 205A or the main area 205B may be electrically connected to the peripheral areas of one or more second sub-seed layers 220 via a plurality of traces 240 respectively.

FIG. 2C is a schematic cross-sectional view of the substrate 201 corresponding to step 150 of FIG. 1 in the method of forming the electronic device 100 according to the present disclosure. Step 150 in Figure 1 corresponds to that shown in Figure 2C. The step of patterning the metal layer 205 can be performed to obtain a patterned metal layer, and this step can simultaneously pattern the seed layer 203'. In some embodiments, one or more etching steps may be performed to pattern the metal layer 205 and the patterned seed layer 203'. For example, the metal layer 205 can be patterned first, and then the first sub-seed layer located under the patterned metal layer 205' is patterned accordingly in the presence of the patterned metal layer 205' (for example, the seed layer 203 in FIG. 2C ' means), completing one or more etching steps, but the disclosure is not limited thereto. In some embodiments, an electroplated photoresist can be provided on the seed layer 203' to define the area where the metal layer 205 is formed. After the metal layer 205 is formed, the electroplated photoresist is removed to obtain a patterned metal layer 205'. The metal layer 205' may expose a portion of the seed layer 203', and then one or more etching steps are performed to remove the exposed seed layer 203'. In some embodiments, the patterned metal layer 205' and the second patterned seed layer 203' can be used together as the first layer of redistribution layer (RDL) 250, for example, as an under-bump metal layer. (UBM, under bump metallization) connection pad, but the disclosure is not limited thereto. According to the present disclosure, the circuit redistribution layer may include a stacking layer composed of multiple layers of metal layers, seed layers and insulating layers (not shown), such as insulating layers (not shown) and patterned metal layers. Layers can be taken together to form functional stacks. The circuit redistribution layer may further include electronic components such as thin film transistors, electrostatic discharge (ESD) components, or capacitors as necessary, but the disclosure is not limited thereto.

FIG. 2C is a schematic cross-sectional view of the substrate 201 corresponding to step 160 of FIG. 1 in the method of forming the electronic device 100 according to the present disclosure. Step 160 in FIG. 1 corresponds to that shown in FIG. 2C , and may be performed to form an insulating layer 260 as needed. In some embodiments, the insulating layer 260 may be formed on the patterned metal layer. 205', so that the insulating layer 260 can cover the patterned metal layer 205' and the first sub-seed layer (represented by the seed layer 203' in Figure 2C) as a protective layer. Or in some embodiments, the insulating layer 260 may be formed between the release layer 202 and the seed layer 203 . The insulating layer 260 can cover the patterned metal layer 205' and the seed layer 203', reducing the possibility of moisture or oxygen affecting the patterned metal layer 205' and the seed layer 203', so it is beneficial to improve the performance of the electronic device 100. electrical reliability. In some embodiments, the insulating layer 260 may include a dielectric material, such as an organic insulating material, an inorganic insulating material, a filler, or any suitable dielectric material. For example, the insulating layer 260 may include polyimide (PI), polystyrene (PS), silicon oxynitride material, ABF film (Ajinomoto build-up film), etc., but the present disclosure is not limited thereto. In some embodiments, the insulating layer 260 may be formed using slit coating, but the present disclosure is not limited thereto. In some embodiments, the step of forming the insulating layer 260 may also include a process of patterning the insulating layer 260, so that the patterned insulating layer 260 facilitates subsequent steps. The patterned metal layer 205', the seed layer 203' and the insulating layer 260 in the first redistribution layer 250 may together form a functional stack.

FIG. 2D is a schematic cross-sectional view of the substrate 201 corresponding to step 170 of FIG. 1 in the method of forming the electronic device 100 according to the present disclosure. Step 170 in FIG. 1 corresponds to that shown in FIG. 2D , and another set of forming steps of the seed layer 271 and the metal layer 272 may be performed. In some embodiments, another set of seed layer 271 and metal layer 272 formed together can be used as the second layer of circuit redistribution layer 270, but the present disclosure is not limited thereto. The second layer of circuit redistribution layer 270 can pass through the opening 261 formed by the patterned insulating layer 260 covering the patterned metal layer 205' and the first sub-seed layer (not labeled) of the seed layer 203', and pass through The opening 261 is electrically connected to the first layer of circuit redistribution layer 250 . For example, the seed layer 271 of the second layer of wire redistribution layer 270 can be electrically connected to the patterned metal layer 205' of the first layer of wire redistribution layer 250, so that the second layer of wire redistribution layer 270 can be connected to the first layer of wire redistribution layer 270. The redistribution layer 250 is electrically connected. For the materials or formation methods of the seed layer 271 and the metal layer 272 of the second layer of circuit redistribution layer 270, please refer to the above and will not be described again.

FIG. 2E illustrates the basic steps of the method for forming the electronic device 100 according to the present disclosure corresponding to step 180 of FIG. 1 . Schematic cross-section of plate 201. Step 180 in FIG. 1 corresponds to that shown in FIG. 2E. The steps of removing the substrate 201 and the release layer 202, forming the bonding material 280, and electrically connecting the chip 290 can be performed. For example, the temporary substrate 201 can be separated from the first layer of circuit redistribution layer 250 by using the release layer 202 to remove the substrate 201 . In some embodiments, a bonding material 280 electrically connected to the first layer of wiring redistribution layer 250 may be formed, such as forming a patterned seed layer 203' with the first layer of wiring redistribution layer 250 (shown in FIG. 2D) The first bonding material 281 is electrically connected. In some embodiments, a bonding material 280 electrically connected to the second layer of wiring redistribution layer 270 may be formed, for example, a second bonding material 282 electrically connected to the metal layer 272 of the second layer of wiring redistribution layer 270 may be formed. In some embodiments, the wafer 290 can be electrically connected to the second bonding material 282, so that the wafer 290 can be electrically connected to each other via the second bonding material 282, the second layer of wiring redistribution layer 270, and the first layer of wiring redistribution. Layer 250 is electrically connected to first bonding material 281 . The bonding material 280 may include conductive materials, such as conductive bumps, solder balls, combinations of the above, or other suitable materials, but the present disclosure is not limited thereto. The wafer 290 may include an electronic component, such as a diode or a semiconductor die, but the disclosure is not limited thereto. In some embodiments, before bonding the wafer 290 to the second layer of circuit redistribution layer 270, a cutting process can be selectively performed to separate the entire surface of the second layer of circuit redistribution layer 270 in Figure 2D from the second layer of circuit redistribution layer 270. A circuit redistribution layer 250 is cut into several parts so that each part can correspond to the pre-bonded chip 290 respectively, but the present disclosure is not limited to the above. After the wafer 290 is bonded to the redistribution layer, the first protective layer 291 and the second protective layer 292 can be formed. The first protective layer 291 can be formed between the chip 290, the redistribution layer 270 and the bonding material to improve the reliability of the electronic device. The first protective layer 291 can be, for example, an underfill or other suitable material, but Not limited to this. The second protective layer 292 can surround the wafer 290 or the redistribution layer 270 or the redistribution layer 250. The second protective layer 292 can reduce the impact of water and oxygen in the environment on the electronic device 100. The second protective layer can be, for example, an encapsulating epoxy resin ( epoxy molding compound (EMC) or other suitable materials, but not limited to this.

It should be noted that in the manufacturing method of the disclosed electronic device shown in FIG. 1 , step 150 Step 180 is optional, that is, these steps may be partially or completely omitted in some embodiments. For example, in some embodiments, the manufacturing method of the electronic device of the present disclosure may include step 110 to step 160 and step 180 while omitting step 170, but the present disclosure is not limited to the above.

According to some embodiments of the present disclosure, the present disclosure provides a method of manufacturing an electronic device by first forming a patterned partitioned seed layer, and then conformally forming a patterned metal layer on the patterned partitioned seed layer. Coupled with the design of the blank area, it can reduce the warping of the conductive layer caused by uneven current density or uneven electric field at edges or corners, and help maintain the electrical reliability of electronic devices. In some embodiments, the protruding portion of the main area can have an appropriate lead angle θ or a shape, which helps to reduce the current density of the seed layer, can improve the uneven electric field caused by uneven power lines at the edge of the substrate, and can improve the substrate. The uneven electric field caused by the uneven edge power lines is conducive to improving the uniformity of the thickness of the electroplated copper layer, so it is conducive to improving the electrical reliability of the electronic device. Optionally, after a metal layer is formed on the patterned partitioned seed layer through an electroplating process, a patterning process can be performed on the metal layer, and the partitioned seed layer below it can also be patterned accordingly. Therefore, the seed layer can be patterned twice.

The above are only embodiments of the present disclosure, and all equivalent changes and modifications made based on the patent scope of the present disclosure shall be within the scope of the present disclosure.

110: Provide substrate

120: Forming a seed layer on the substrate

130: Patterning the seed layer to form multiple sub-seed layers and multiple conductive lines

140: Forming a metal layer on at least one of the plurality of sub-seed layers

150:Patterned metal layer

160: Forming an insulating layer

170: Form another set of seed layer and metal layer

180: Remove the substrate and release layer, form the bonding material, and make electrical connections with the chip

Claims (9)

A method of manufacturing an electronic device, including: providing a substrate; forming a seed layer on the substrate; patterning the seed layer to form a plurality of sub-seed layers and a plurality of conductive lines, wherein the plurality of conductive lines respectively have a turning; and forming a metal layer on at least one of the plurality of sub-seed layers, wherein the plurality of sub-seed layers include a first sub-seed layer and a second sub-seed layer, and the third sub-seed layer A sub-seed layer and the second sub-seed layer are separated from each other. The method of manufacturing an electronic device according to claim 1, wherein the metal layer is formed on the plurality of conductive lines to form a plurality of traces. According to the manufacturing method of an electronic device according to claim 1, the length difference between the plurality of conductive lines is not greater than 15%. The method of manufacturing an electronic device according to claim 1, wherein the metal layer is formed on the first sub-seed layer. The method of manufacturing an electronic device according to claim 1, wherein the first sub-seed layer includes at least one main region. The method for manufacturing an electronic device according to claim 1, wherein the first sub-seed layer includes a plurality of a protrusion. The method for manufacturing an electronic device according to claim 6, wherein at least one of the plurality of protrusions has a leading angle. According to the manufacturing method of an electronic device according to claim 7, the lead angle is between 30° and 150°. The manufacturing method of an electronic device according to claim 6, wherein there is a gap between any two adjacent ones of the plurality of protrusions.

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