TWI825822B - Semiconductor structure with a porous structure - Google Patents

Abstract

The present application provides a semiconductor structure having a porous structure between a conductive pad and a metal layer. The semiconductor structure includes a substrate including an interconnection structure; a dielectric layer disposed over the substrate; a conductive pad disposed over the dielectric layer; a passivation layer, disposed over the dielectric layer and partially exposing the conductive pad; and a porous layer, surrounded by the dielectric layer and extending between the substrate and the conductive pad.

Description

Semiconductor structure with porous structure

This application claims priority to U.S. Patent Application Nos. 17/742,541 and 17/742,612 (that is, the priority date is "May 12, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor structure, and in particular, to a semiconductor structure having a porous structure.

Semiconductor components are used in various electronic applications such as personal computers, mobile phones, digital cameras and other electronic devices. Semiconductor components are continuously shrinking in size to meet growing demands for computing power. However, various problems arise during the downsizing process, and these problems continue to increase in number and complexity. Therefore, challenges remain in achieving improvements in quality, yield, performance and reliability, and in reducing complexity.

The above description of "prior art" is only to provide background technology, and does not admit that the above description of "prior art" reveals the subject matter of the present disclosure. It does not constitute prior art of the present disclosure, and any description of the above "prior art" None should form any part of this case.

One aspect of the present disclosure provides a semiconductor structure. The semiconductor structure includes: a substrate including an interconnection structure; a dielectric layer disposed on the substrate; a conductive pad, disposed on the dielectric layer; a passivation layer disposed on the dielectric layer and partially exposing the conductive pad; and a porous layer surrounded by the dielectric layer and extending between the substrate and the conductive pad.

In some embodiments, the semiconductor structure further includes: a first liner surrounding the porous layer and disposed in the dielectric layer.

In some embodiments, the first liner at least partially surrounds a side wall and a bottom surface of the porous layer.

In some embodiments, the first liner surrounds a side wall of the porous layer and the porous layer is in contact with the substrate.

In some embodiments, the semiconductor structure further includes: a conductive via disposed adjacent to the porous layer and electrically connected to the conductive pad and the interconnect structure.

In some embodiments, a portion of the dielectric layer is disposed between the conductive via and the porous layer.

In some embodiments, a top cross-sectional area of the conductive via is substantially larger than a top cross-sectional area of the porous layer.

In some embodiments, the conductive via extends through the dielectric layer.

In some embodiments, the conductive via includes a plurality of conductive vias, and the plurality of conductive vias are separated from each other.

In some embodiments, the plurality of conductive vias are covered by the conductive pad.

In some embodiments, the porous layer has a porosity between 5% and 30%.

In some embodiments, the porous layer has a porosity between 10% and 15%.

In some embodiments, the semiconductor structure further includes: a second pad disposed between the porous layer and the conductive pad.

In some embodiments, the porous layer is surrounded by the first liner and the second liner.

In some embodiments, the porous layer is disposed in a central area of the conductive pad when viewed from a top view.

Another aspect of the present disclosure provides a semiconductor structure. The semiconductor structure includes: a substrate including an interconnection structure; a dielectric layer disposed on the substrate; a porous pillar disposed on the substrate and extending through the dielectric layer; a first moisture-proof layer, Surrounding the porous pillar and disposed in the dielectric layer; a conductive via extending in the dielectric layer and disposed adjacent to the porous post; and a conductive pad disposed on the dielectric layer and covering the conductive via and the porous column.

In some embodiments, the semiconductor structure further includes: a second moisture-proof layer disposed between the porous pillar and the conductive pad.

In some embodiments, the conductive via penetrates the second moisture barrier layer and contacts the conductive pad.

In some embodiments, the semiconductor structure further includes: a passivation layer disposed on the dielectric layer and separated from the dielectric layer by the second moisture-proof layer.

In some embodiments, the porous pillars include one or more low-k (dielectric constant) materials.

In some embodiments, the conductive vias include tungsten, copper, cobalt, ruthenium, molybdenum, or combinations thereof.

In some embodiments, the conductive via includes: a barrier component and a conductive component surrounded by the conductive via.

In some embodiments, the barrier layer includes titanium, tantalum, titanium nitride, tantalum nitride, or combinations thereof.

In some embodiments, the first moisture barrier layer includes nitride, high-k material, or combinations thereof.

Another aspect of the present disclosure provides a method of fabricating a semiconductor structure. The preparation method includes: forming a dielectric layer on a substrate; forming an opening in the dielectric layer; forming a first pad conforming to the opening; forming a porous layer in the opening and being covered by the opening. The first liner surrounds; forming a conductive via hole penetrating the dielectric layer; and forming a conductive pad on the dielectric layer, wherein the conductive pad covers the porous layer and the conductive via hole.

In some embodiments, the preparation method further includes: forming a second liner on the dielectric layer before forming the conductive via hole, wherein the conductive via hole penetrates the second liner.

In some embodiments, a top surface of the porous layer is substantially aligned with a top surface of the first liner.

In some embodiments, forming the first liner includes: depositing a first nitride layer conformable to the dielectric layer and the opening; and removing the first nitride layer above the dielectric layer and in the opening. The horizontal portion of the nitride layer.

In some embodiments, forming the conductive pad includes: depositing a conductive layer on the dielectric layer; forming a photoresist layer on the conductive layer; removing a portion of the conductive layer exposed through the photoresist layer. forming the conductive pad; and removing the photoresist layer.

In some embodiments, the preparation method further includes: forming a passivation material on the dielectric layer and the conductive pad; and exposing at least a portion of the conductive pad.

In some embodiments, forming the porous layer includes: forming an energy-removable material on the dielectric layer and in the opening; performing an energy treatment on the energy-removable material; and removing the energy-removable material disposed in the medium. This energy above the electrical layer can remove part of the material.

In some embodiments, the energy-removable material includes a thermally decomposable material, A photon decomposes the material, an electron beam decomposes the material, or a combination thereof.

In some embodiments, the energy-removable material includes a base material and a decomposable porogen material.

In some embodiments, the base material includes a silyl-based material and the decomposable porogen material includes a porogenic organic compound.

In some embodiments, the energy treatment includes applying a heat source or a light source to the energy-removable material.

The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be readily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

10: Base

11: Basal layer

12:Interconnect structure

21: Dielectric layer

31: first liner

32: Energy removable materials

33: Porous layer

34:Second pad

35:Third pad

41:Barrier layer

42: Conductive materials

43:Barrier components

44: Conductive parts

45:Conductive vias

51:Contact materials

52:Conductive pad

53: Passivation material

54: Passivation layer

61: Photoresist layer

62: Photoresist layer

63: Photoresist layer

71:Energy processing

81: Dry etching operation

82: Erosion back operation

83: Fixed graphics operation

84:Etching operation

91:Open your mouth

92:Open your mouth

93:Open your mouth

100:Semiconductor Structure

101: Top surface

121: Intermetal dielectric (IMD) layer

122:Through hole

123:IMD layer

124:Metal wire

200:Semiconductor Structure

211: Top surface

300:Semiconductor Structure

321:Top surface

331:Top surface

332: Bottom surface

341:Top surface

351:Top surface

451:Top surface

521:Top surface

522:Side wall

523:Central area

524: Surrounding area

525:center

531: Top surface

911:Side wall

912: Bottom surface

A-A': line

B-B': line

C-C': line

M1: metal layer

Mn: metal layer

S1: Preparation method

S11: Operation

S12: Operation

S13: Operation

S14: Operation

S15: Operation

S16: Operation

The disclosure content of this application can be more fully understood by referring to the embodiments and the patent scope combined with the drawings. The same element symbols in the drawings refer to the same elements.

FIG. 1 is a cross-sectional view illustrating a semiconductor structure according to some embodiments of the present disclosure.

FIG. 2 is a top view illustrating a semiconductor structure according to some embodiments of the present disclosure.

FIG. 3 is a flow chart illustrating a method of manufacturing a semiconductor structure according to some embodiments of the present disclosure.

4-26 are cross-sectional views illustrating intermediate stages of fabrication of semiconductor structures according to some embodiments of the present disclosure.

27 is a top view illustrating a semiconductor structure according to some embodiments of the present disclosure.

28-31 are cross-sectional views illustrating intermediate stages of fabrication of semiconductor structures according to some embodiments of the present disclosure.

32 is a top view illustrating a semiconductor structure according to some embodiments of the present disclosure.

Specific language will now be used to describe the embodiments, or examples, of the present disclosure illustrated in the drawings. It should be understood that there is no intention to limit the scope of the present disclosure. Any changes or modifications to the described embodiments, and any further applications of the principles described herein, are deemed to be commonly made by one of ordinary skill in the art to which this disclosure relates. Reference numbers may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment apply to another embodiment, even if they share the same reference number.

It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers or sections, these elements, elements, regions, layers or sections are not limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the inventive concept.

The terminology used herein is for describing particular embodiments only and is not intended to limit the concepts of the invention. As used herein, the singular forms "a", "an" and "the" include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and "includes", when used in this specification, indicate the presence of stated features, integers, steps, operations, elements or components, but do not exclude the presence or addition of one or more other Characteristic, integer, step, operation, element, component, or group thereof.

1 is a cross-sectional view illustrating a semiconductor structure of some embodiments of the present disclosure. 100. The semiconductor structure 100 may include a substrate 10 , a dielectric layer 21 , a conductive pad 52 , a passivation layer 54 and a porous layer 33 . In some embodiments, substrate 10 includes interconnect structure 12 . In order to facilitate explanation and simplify the drawings, only the uppermost metal layer Mn is depicted in FIG. 1 . In some embodiments, the metal layer Mn includes a plurality of metal lines 124 and an inter-metal dielectric (IMD) layer 123 surrounding the metal lines 124 . The metal lines 124 may be separated and electrically isolated from each other by the IMD layer 123 . In some embodiments, the dielectric layer 21 is disposed on the substrate 10 . In some embodiments, the conductive pad 52 is disposed on the dielectric layer 21 . In some embodiments, passivation layer 54 is disposed on dielectric layer 21 . In some embodiments, passivation layer 54 covers conductive pad 52 . In some embodiments, conductive pad 52 is at least partially exposed through passivation layer 54 . In some embodiments, porous layer 33 extends between conductive pad 52 and substrate 10 . In some embodiments, porous layer 33 is sandwiched between conductive pad 52 and substrate 10 . In some embodiments, porous layer 33 is surrounded by dielectric layer 21 . In some embodiments, porous layer 33 has a porosity between 5% and 30%. In some embodiments, porous layer 33 has a porosity between 10% and 15%. In some embodiments, porous layer 33 includes a low-k (dielectric constant) material. In some embodiments, porous layer 33 has a columnar configuration. In some embodiments, porous layer 33 may be referred to as porous pillars 33.

Fabrication techniques for porous layer 33 may include energy removable materials, as described below. In some embodiments, energy removable materials may include, for example, thermal decomposition materials, photon decomposition materials, electron beam decomposition materials, or combinations thereof. For example, energy-removable materials may include a base material and a decomposable porogen material that is sacrificed upon exposure to an energy source.

The porous layer 33 may include a skeleton and a plurality of vacancies disposed between the skeleton. Multiple vacancies can be connected to each other and filled with air. The backbone may include, for example, silicon oxide or methylsilsesquioxane. The porous layer 33 may act as a force absorber during the processing of the semiconductor structure 100 or when the semiconductor structure 100 is used. In some embodiments, Due to the characteristics of the porous structure, the porous layer 33 can absorb the bonding force of the semiconductor structure 100 or the conductive pad 52 during the process. Therefore, defects or damage to the semiconductor structure 100 may be reduced, and the performance and production yield of the semiconductor structure 100 or its application may be improved.

The semiconductor structure 100 may further include a first liner 31 surrounding the porous layer 33 . In some embodiments, first pad 31 extends through dielectric layer 21 . In some embodiments, at least a portion of the first pad 31 is disposed within the dielectric layer 21 . In some embodiments, the first pad 31 is also disposed on the dielectric layer 21 . In some embodiments, first liner 31 only surrounds the sidewalls of porous layer 33 (not shown in Figure 1). In some embodiments, first liner 31 surrounds sidewalls and bottom surface 332 of porous layer 33 . In some embodiments, first liner 31 includes nitride, a high-k material, or a combination thereof. In some embodiments, first liner 31 includes silicon nitride.

The semiconductor structure 100 may further include a second pad 34 disposed between the porous layer 33 and the conductive pad 52 . In some embodiments, the second pad 34 is further disposed between the dielectric layer 21 and the conductive pad 52 . In some embodiments, the second pad 34 is further disposed between the dielectric layer 21 and the passivation layer 54 . In some embodiments, porous layer 33 is surrounded by first liner 31 and second liner 34 . In some embodiments, second liner 34 is a planar layer. In some embodiments, second liner 34 includes nitride. In some embodiments, second gasket 34 includes the same material as first gasket 31 . The first liner 31 and the second liner 34 are configured to prevent moisture from entering the porous layer 33 . In some embodiments, the first liner 31 and the second liner 34 are referred to as the first moisture-proof layer 31 and the second moisture-proof layer 34 .

Semiconductor structure 100 may also include at least one conductive via 45 . The conductive vias 45 can electrically connect the conductive pads 52 to the interconnect structure 12 . More specifically, the conductive vias 45 can electrically connect the conductive pads 52 to the metal lines 124 in the uppermost metal layer Mn of the interconnect structure 12 . In some embodiments, the conductive via 45 is disposed in the dielectric layer 21 on the substrate 10 . In some practical In the embodiment, the conductive via 45 is adjacent to the porous layer 33 . In some embodiments, a portion of dielectric layer 21 is disposed between conductive via 45 and porous layer 33 . In some embodiments, conductive vias 45 are physically isolated from porous layer 33 by dielectric layer 21 . In some embodiments, conductive vias 45 extend through dielectric layer 21 . In some embodiments, conductive via 45 extends through first pad 31 . In some embodiments, conductive via 45 extends through second pad 34 . In some embodiments, conductive vias 45 include tungsten, copper, cobalt, ruthenium, molybdenum, or combinations thereof.

FIG. 2 is a top view illustrating the conductive pads 52 , conductive vias 45 and porous layer 33 according to some embodiments of the present disclosure. In some embodiments, FIG. 1 is a cross-sectional view along line AA' in FIG. 2 . In some embodiments, the semiconductor structure 100 includes a plurality of conductive vias 45 as shown in FIGS. 1 and 2 . In some embodiments, conductive vias 45 are separate from each other. In some embodiments, conductive vias 45 are entirely covered by conductive pads 52 . In some embodiments, the porous layer 33 is disposed in the central region 523 of the conductive pad 52 . In some embodiments, porous layer 33 overlaps center 525 (indicated by a dot) of conductive pad 52 . In some embodiments, as shown in FIG. 2 , conductive vias 45 surround porous layer 33 . However, the arrangement of the conductive vias 45 is not limited as long as the conductive pads 52 can be electrically connected to the interconnection structure 12 of the substrate 10 . In some embodiments, the top cross-sectional area of the conductive vias 45 (the area seen from the top view of FIG. 2 ) is substantially larger than the top cross-sectional area of the porous layer 33 (the area as seen from the top view of FIG. 2 area) to achieve the purpose of reducing resistance and improving conductivity. In some embodiments, the top cross-sectional area of conductive via 45 is the total area of the top surface of conductive via 45 . In some embodiments, the top cross-sectional area of porous layer 33 is the area of the top surface of porous layer 33 .

FIG. 3 is a flowchart illustrating a method S1 for fabricating a semiconductor structure (similar to the semiconductor structure 100 ) according to some embodiments of the present disclosure. Preparation method S1 includes some operations (S11, S12, S13, S14, S15 and S16), and the description and explanation should not be regarded as limiting the order of operations. in operation In S11, a dielectric layer is formed on a substrate. In operation S12, an opening is formed in the dielectric layer. In operation S13, a first pad conforming to the opening is formed. In operation S14, a porous layer is formed in the opening and surrounded by the first liner. In operation S15, a conductive via hole is formed penetrating the dielectric layer. In operation S16, a conductive pad is formed on the dielectric layer, wherein the conductive pad covers the porous layer and the conductive via hole. It should be noted that the operations of preparation method S1 may be rearranged or otherwise modified within various aspects. Additional processes may be provided before, during and after preparation method S1, and some other processes may be briefly described here. Accordingly, other implementations are possible within the scope of the aspects described herein.

4 to 26 are cross-sectional views illustrating various fabrication stages constructed by the fabrication method S1 of the semiconductor structure 200 according to some embodiments of the present disclosure. The stages shown in FIGS. 4 to 26 are also schematically illustrated in the preparation sequence of FIG. 3 . In the ensuing discussion, the preparation stages shown in FIGS. 4 to 26 are discussed with reference to the preparation operations in FIG. 3 .

Referring to FIG. 4 , FIG. 4 is a cross-sectional view illustrating the preparation stage of the preparation method S1 of some embodiments of the present disclosure. Before operation S11, a substrate 10 is provided, received or formed.

The substrate 10 may include an interconnect structure 12 disposed or formed on the base layer 11 . The base layer 11 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, or the like. The base layer 11 may include a first conductivity type, such as a P-type substrate (electron acceptor type), or a second conductivity type, such as an N-type semiconductor substrate (electron donor type). In addition, the base layer 11 may include elemental semiconductors, including silicon or germanium in single crystal form, polycrystalline form or amorphous form; composite semiconductor materials, including silicon carbide, gallium arsenide, gallium phosphide, At least one of indium phosphide, indium arsenide and indium antimonide; alloy semiconductor materials including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and GaInAsP At least one of; any other suitable materials; or a combination thereof. In some embodiments, the alloy semiconductor substrate may be a SiGe alloy having a gradient Si:Ge feature, where the compositions of Si and Ge change from a ratio at one location of the gradient SiGe feature to a ratio at another location. In another embodiment, the SiGe alloy is formed on a silicon substrate. In some embodiments, the SiGe alloy can be mechanically strained by another material in contact with the SiGe alloy.

In some embodiments, the base layer 11 may be a multi-layer structure, or the base layer 11 may include a multi-layer compound semiconductor structure. In some embodiments, the base layer 11 includes a semiconductor element, an electrical component, an electrical element, or a combination thereof. In some embodiments, the base layer 11 includes a transistor or a functional unit of a transistor. Semiconductor elements, electrical components or electrical elements may be formed in the base layer 11 according to conventional semiconductor manufacturing methods. Semiconductor components, electrical components or electrical elements may be active components or components, and may include different types or generations of components. Semiconductor components, electrical components or electrical elements may include planar transistors, multi-gate transistors, gate surround field effect transistors (GAAFET), fin field effect transistors (FinFET), vertical transistors, nanosheet transistors, Nanowire transistors, passive components, capacitors, memory components or combinations thereof.

The interconnect structure 12 may include a plurality of metal layers M1 to Mn, where n is a positive integer greater than 1. The interconnect structure 12 may also include a plurality of via layers alternately arranged between the metal layers for electrical connection between the metal layers. In some embodiments, each metal layer includes a metal line and an inter-metal dielectric (IMD) layer surrounding the metal line. In some embodiments, each via layer includes a metal via and an IMD layer surrounding the metal via. In some embodiments, metal layer M1 of interconnect structure 12 is the first metal layer above base layer 11 . In some embodiments, metal layer Mn represents the uppermost metal layer of interconnect structure 12 . In some embodiments, the metal layer Mn includes an IMD layer 123 and a plurality of metal lines 124 surrounded by the IMD layer 123 . In some embodiments, the uppermost via layer contains It includes an IMD layer 121 and a plurality of through holes 122 to electrically connect the metal lines 124 to the underlying metal layer. For the sake of simplicity, only the metal layer Mn of the substrate 10 is described and illustrated in the following description and related numbers, but this description is not intended to limit the disclosure. In some embodiments, metal wire 124 includes one or more metals, such as tungsten, copper, cobalt, ruthenium, molybdenum, titanium, tantalum, nickel, platinum, erbium, combinations thereof, alloys thereof, or combinations of alloys thereof. In some embodiments, metal lines 124 include tungsten, copper, platinum, or combinations thereof.

Referring to FIG. 5 , FIG. 5 is a cross-sectional view illustrating the preparation stage of the preparation method S1 of some embodiments of the present disclosure. After the substrate 10 is provided, received or formed, a dielectric layer 21 is formed on the substrate 10 in operation S11. In some embodiments, dielectric layer 21 is formed on top surface 101 of substrate 10 . In some embodiments, dielectric layer 21 is an interlayer dielectric (ILD) layer. In some embodiments, dielectric layer 21 includes one or more dielectric materials. In some embodiments, the dielectric material includes silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), or combinations thereof. In some embodiments, dielectric layer 21 includes silicon dioxide (SiO2).

In some embodiments, the dielectric material includes polymeric materials, organic materials, inorganic materials, photoresist materials, or combinations thereof. In some embodiments, the dielectric material includes one or more low-k dielectric materials with a dielectric constant (k value) less than 3.9. In some embodiments, low-k dielectric materials include fluorine-doped silicon dioxide, organosilicon glass (OSG), carbon-doped oxide (CDO), porous silicon dioxide, spin-on organic polymer dielectrics , spin-on silicone-based polymer dielectrics, or combinations thereof. In some embodiments, the dielectric material includes one or more high-k dielectric materials with a dielectric constant (k value) greater than 3.9. High-k dielectric materials may include hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), titanium oxide (TiO2), or other suitable materials. Other suitable materials are contemplated by this disclosure.

In some embodiments, the fabrication technique of dielectric layer 21 includes blanket deposition. exist In some embodiments, the manufacturing technology of the dielectric layer 21 includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced CVD ( PECVD) or a combination thereof.

Referring to FIG. 6 , FIG. 6 is a cross-sectional view illustrating the preparation stage of the preparation method S1 of some embodiments of the present disclosure. Before operation S12, a photoresist layer 61 is formed on the dielectric layer 21. In some embodiments, a portion of dielectric layer 21 is bounded by and exposed through photoresist layer 61 . Photoresist layer 61 is configured to protect portions of dielectric layer 21 covered by photoresist layer 61 during subsequent patterning operations.

Referring to FIG. 7 , FIG. 7 is a cross-sectional view illustrating the preparation stage of the preparation method S1 of some embodiments of the present disclosure. In operation S12 , the dielectric layer 21 is patterned to expose a portion of the substrate 10 and form the opening 91 . In some embodiments, a portion of substrate 10 is exposed in opening 91 through dielectric layer 21 . In some embodiments, opening 91 is defined by dielectric layer 21 and substrate 10 . In some embodiments, patterning dielectric layer 21 includes ion beam etching, directional dry etching, reactive ion etching, or a combination thereof. In some embodiments, patterning of dielectric layer 21 includes a dry etching operation 81 , and dry etching operation 81 stops at the exposure of substrate 10 . In some embodiments, opening 91 exposes a portion of metal line 124 in substrate 10 . In some embodiments, after operation S11 and before operation S12 , a pre-cleaning operation, photoresist application (formation of the photoresist layer 21 ), exposure, development and etching are performed sequentially to form the opening 91 .

Referring to FIG. 8 , FIG. 8 is a cross-sectional view illustrating the preparation stage of the preparation method S1 of some embodiments of the present disclosure. After operation S12, the photoresist layer 61 is removed. In some embodiments, a wet etching operation is performed to remove the photoresist layer 61 . In some embodiments, after removing the photoresist layer 61, a post-cleaning operation may be optionally performed.

Referring to Figure 9, Figure 9 is a cross-sectional view illustrating the preparation of some embodiments of the present disclosure. Preparation stage of method S1. In operation S13, the first pad 31 is formed on the dielectric layer 21. In some embodiments, the first liner 31 lines the opening 91 and the top surface 211 of the dielectric layer 21 . In some embodiments, the contour of the first pad 31 is conformal to the contours of the dielectric layer 21 and the substrate 10 . In some embodiments, deposition is performed to form first liner 31 . In some embodiments, the manufacturing technology of the first liner 31 includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD) or combination thereof. In some embodiments, first pad 31 includes one or more dielectric materials. In some embodiments, first liner 31 includes nitride, oxide, high-k material, or combinations thereof. In some embodiments, first liner 31 includes silicon nitride. In some embodiments, the thickness of the first liner 31 is between 1 and 50 nanometers to prevent moisture. In some embodiments, the thickness of first liner 31 is substantially uniform throughout first liner 31 .

Referring to FIG. 10 , FIG. 10 is a cross-sectional view illustrating the preparation stage of the preparation method S1 of some embodiments of the present disclosure. Before operation S14 , energy removable material 32 is formed on dielectric layer 21 and in opening 91 . More specifically, energy removable material 32 is formed on first pad 31 and in opening 91 . In some embodiments, the fabrication technique for energy removable material 32 includes blanket deposition. In some embodiments, energy removable material 32 fills at least opening 91 . In some embodiments, top surface 321 of energy removable material 32 is located above first pad 31 . In some embodiments, top surface 321 of energy removable material 32 is substantially planar. Energy removable material 32 may include a material such as a thermal decomposition material, a photon decomposition material, an electron beam decomposition material, or a combination thereof. For example, energy removable material 32 may include a base material and a decomposable porogenic material that is sacrificed when exposed to an energy source. The base material may include a silyl-based material. The decomposable porogenic material may include a porogenic organic compound that provides porosity to the base material of energy removable material 32 upon exposure to an energy source. Or, in another embodiment, The base material may be silicon oxide. The decomposable porogenic material may include unsaturated bonded compounds, such as double bonded or triple bonded compounds.

Referring to FIGS. 11 and 12 , FIGS. 11 and 12 are cross-sectional views illustrating different preparation stages of the preparation method S1 of some embodiments of the present disclosure. In operation S14, energy treatment 71 is performed on the energy-removable material 32 as shown in FIG. 11 to form the porous layer 33 as shown in FIG. 12. Energy treatment 71 may be performed by applying an energy source to the intermediate semiconductor structure as shown in FIG. 11 . The energy source may include heat, light, or a combination thereof. When heat is used as the energy source, the temperature of the energy treatment 71 can be between about 800°C and about 1000°C. When light is used as the energy source, ultraviolet light can be used. Energy treatment 71 may remove decomposable porogenic material from energy removable material 32 to create voids or pores while the base material remains in place. In other embodiments as described above, the base material may be silicon oxide, and the decomposable porogenic material may include compounds with unsaturated bonds, such as double or triple bond compounds. In such embodiments, during energy treatment 71, the unsaturated bonds of the decomposable porogenic material may be cross-linked with the silicon oxide of the base material. Therefore, the decomposable porogenic material may shrink and create voids or pores, while the base material remains in place. The empty voids or pores can be filled with air so that the porous layer 33 can provide support for the conductive pad to be formed over the porous layer 33 and can also serve as a cushion or buffer zone to absorb forces on the semiconductor structure 100 without being damaged. . In some embodiments, porous layer 33 has a porosity between 5% and 30%. In some embodiments, porous layer 33 has a porosity between 10% and 15%. In some embodiments, porous layer 33 includes a low-k material.

The porosity of the porous layer 33 may be determined by the concentration of the base material of the decomposable porogenic material and the energy removable material 32 . To form porous layer 33 with a porosity of 5% to 30% (or 10% to 15% as described above), energy removable material 32 may include a relatively low concentration of decomposable porogenic material and a relatively high concentration of basic materials. For example, energy removable material 32 may include Includes approximately 5% or more decomposable porogen material and approximately 95% or less base material. In another example, the energy removable material 32 may include about 10% or more decomposable porogenic material and about 90% or less base material. In another example, energy removable material 32 may include about 15% decomposable porogen material, and about 85% base material.

Referring to FIG. 13 , FIG. 13 is a cross-sectional view illustrating the preparation stage of the preparation method S1 according to some embodiments of the present disclosure. After operation S14, as shown in FIG. 12, an etch-back operation 81 is performed on the porous layer 33. In some embodiments, a portion of the porous layer 33 above the first liner 31 or dielectric layer 21 is removed. In some embodiments, the etchback operation 81 stops when exposure of the first pad 31 is detected. In some embodiments, after the etch back operation 81, a portion of the porous layer 33 in the opening 91 remains. In some embodiments, the top surface 331 of the remaining portion of the porous layer 33 is substantially aligned with the top surface 311 of the first liner 31 . In some embodiments, the top surface 331 of the remaining portion of the porous layer 33 is substantially coplanar with the top surface 311 of the first liner 31 . In some embodiments, porous layer 33 has a columnar configuration after etchback operation 81 . In some embodiments, porous layer 33 is referred to as porous pillar 33 after etchback operation 81 .

It should be noted that the order of operations shown in Figures 9 to 11 can be changed to achieve the same results with the structure shown in Figure 11. In some embodiments, energy processing 71 may be performed after etchback operation 81 . A portion of the energy-removable material 32 above the first liner 31 or dielectric layer 21 may be removed by an etchback operation 81 . Energy treatment 71 is then performed on the remaining portion of energy removable material 32 disposed in opening 91 to form porous pillars 33 as shown in FIG. 13 .

Referring to FIG. 14 , FIG. 14 is a cross-sectional view illustrating the preparation stage of the preparation method S1 of some embodiments of the present disclosure. Before operation S15, a second liner 34 is formed on the porous pillar 33. In some embodiments, deposition is performed to form second liner 34 . In some embodiments, the manufacturing technology of the second liner 34 includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD) or a combination thereof. In some embodiments, the fabrication technique for the second pad 34 includes blanket deposition. In some embodiments, the second liner 34 is disposed on the porous column 33 and the first liner 31 . In some embodiments, the second liner 34 is in contact with the top surface 331 of the porous post 33 and the top surface 311 of the first liner 31 . In some embodiments, second pad 34 includes one or more dielectric materials. In some embodiments, second liner 34 includes nitride, oxide, high-k material, or combinations thereof. In some embodiments, second liner 34 includes silicon nitride. In some embodiments, the thickness of the second liner 34 ranges from 1 to 50 nanometers to achieve moisture resistance. In some embodiments, the thickness of second liner 34 is substantially uniform throughout second liner 34 . In some embodiments, the dielectric material of the second pad 34 is the same as the dielectric material of the first pad 31 so that conductive vias can be formed by etching in subsequent processes. In some embodiments, porous column 33 is surrounded by first liner 31 and second liner 34 .

Referring to FIG. 15 , FIG. 15 is a cross-sectional view illustrating the preparation stage of the preparation method S1 of some embodiments of the present disclosure. After the formation of the second liner 34 and before operation S15, a portion of the substrate 10 is exposed. In some embodiments, an etching operation is performed on the second liner 34 , the first liner 31 and the dielectric layer 21 . In some embodiments, portions of the second liner 34 , the first liner 31 and the dielectric layer 21 are removed by the etching operation. Fabrication techniques for one or more openings 92 include etching operations. In some embodiments, one or more portions of metal line 124 are exposed by one or more openings 92 . In some embodiments, one or more openings 92 are defined by the substrate 10 , the dielectric layer 21 , the first pad 31 and the second pad 34 . In some embodiments, one or more openings 92 are separate from the porous column 33 . In some embodiments, one or more openings 92 extend through dielectric layer 21 . In some embodiments, one or more openings 92 penetrate the dielectric layer 21 , the first pad 31 and the second pad 34 . In some embodiments having one opening 92, the opening 92 is adjacent to or surrounding the porous post 33. Around the porous column 3. In some embodiments with multiple openings 92, the openings 92 are spaced apart from each other.

In some embodiments, the fabrication technique of opening 92 includes one or more etching operations. In some embodiments, the fabrication technique of the opening 92 includes an etching operation, and the etchant used in the etching operation has low selectivity to the first liner 31 , the second liner 34 and the dielectric layer 21 . In some embodiments, the first liner 31 and the second liner 34 include the same material, which may facilitate etchant selection for the etching operation. In some embodiments, the first liner 31 , the second liner 34 and the dielectric layer 21 may be removed through a series of different etching operations. In some embodiments, each different etching operation is highly selective to a corresponding target layer (eg, first liner 31, second liner 34, or dielectric layer 21).

Referring to FIG. 16 , FIG. 16 is a cross-sectional view illustrating the preparation stage of the preparation method S1 of some embodiments of the present disclosure. After the opening 92 is formed, the barrier layer 41 is formed conforming to the opening 92 . In some embodiments, barrier layer 41 lines opening 92. In some embodiments, barrier layer 41 covers second liner 34 . In some embodiments, the fabrication technique of barrier layer 41 includes conformal deposition. In some embodiments, the barrier layer 41 is fabricated using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), and plasma enhanced CVD. (PECVD), or a combination thereof. In some embodiments, barrier layer 41 includes titanium, tantalum, nitrides thereof, alloys thereof, or combinations thereof. In some embodiments, barrier layer 41 may be a multi-layer structure. In some embodiments, barrier layer 41 includes a titanium sublayer and a titanium nitride sublayer. However, the present invention is not limited to this.

Referring to FIG. 17 , FIG. 17 is a cross-sectional view illustrating the preparation stage of the preparation method S1 of some embodiments of the present disclosure. After the barrier layer 41 is formed, the conductive material 42 is formed on the barrier layer 41 . In some embodiments, conductive material 42 fills opening 92 and is disposed on barrier layer 41 . In some embodiments, conductive material 42 includes one or more metals, such as tungsten, copper, cobalt, ruthenium, Molybdenum, titanium, tantalum, nickel, platinum, erbium, combinations thereof, alloys thereof or combinations of alloys thereof. In some embodiments, conductive material 42 includes tungsten, copper, or combinations thereof. In some embodiments, the manufacturing technology of the conductive material 42 includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced CVD ( PECVD), electroplating, electroless plating, sputtering or combinations thereof.

Referring to FIG. 18 , FIG. 18 is a cross-sectional view illustrating the preparation stage of the preparation method S1 of some embodiments of the present disclosure. In operation S15, an etchback operation 82 is performed on the conductive material 42 and the barrier layer 41 shown in FIG. 17 to form one or more conductive vias 45 shown in FIG. 18. In some embodiments, portions of the conductive material 42 and barrier layer 41 above the second pad 34 are removed by an etch back operation 82 . In some embodiments, one or more portions of conductive material 42 remaining in opening 92 become one or more conductive features 44 . In some embodiments, the portion of barrier layer 41 that remains in opening 92 becomes one or more barrier features 43 . In some embodiments, the barrier component 43 and the conductive component 44 together form one or more conductive vias 45 . In some embodiments, each conductive via 45 includes a conductive component 44 and a barrier component 43 . In some embodiments, barrier component 43 surrounds conductive component 44 . In some embodiments, the conductive component 44 is separated from the dielectric layer 21 , the first pad 31 or the second pad 34 by the barrier component 43 . In some embodiments, the top surface 451 of the conductive via 45 is located at an elevation above the top surface 211 of the dielectric layer 21 or the top surface 311 of the first pad 31 . In some embodiments, the top surface 451 of the conductive via 45 is substantially aligned with the top surface 341 of the second pad 34 .

Referring to FIG. 19 , FIG. 19 is a cross-sectional view illustrating the preparation stage of the preparation method S1 of some embodiments of the present disclosure. Before operation S16, contact material 51 is formed on dielectric layer 21. In some embodiments, the contact material 51 is disposed on the porous pillar 33 , the conductive via 45 and the second pad 34 . In some embodiments, contact material 51 includes one or more metals, such as tungsten, copper, Aluminum, cobalt, ruthenium, molybdenum, titanium, tantalum, nickel, platinum, erbium, combinations thereof, alloys thereof or combinations of alloys thereof. In some embodiments, contact material 51 includes aluminum. In some embodiments, the manufacturing technology of the contact material 51 includes chemical vapor deposition (CVD), physical vapor deposition (PVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), electroplating, electroless plating, sputtering or a combination thereof. In some embodiments, contact material 51 is separated from porous post 33 by second liner 34 .

Referring to FIG. 20 , FIG. 20 is a cross-sectional view illustrating the preparation stage of the preparation method S1 of some embodiments of the present disclosure. Before operation S16, a photoresist layer 62 is formed on the contact material 51. In some embodiments, a portion of contact material 51 is bounded by and exposed through photoresist layer 62 . Photoresist layer 62 is configured to protect portions of dielectric layer 21 covered by photoresist layer 62 during subsequent patterning operations.

Referring to FIG. 21 , FIG. 21 is a cross-sectional view illustrating the preparation stage of the preparation method S1 of some embodiments of the present disclosure. In operation S16, contact material 51 is patterned to form conductive pads 52. In some embodiments, a portion of contact material 51 exposed through photoresist layer 62 is removed through patterning operation 82 . In some embodiments, patterning operation 82 includes ion beam etching, directional dry etching, reactive ion etching, or a combination thereof. In some embodiments, patterning operation 82 of contact material 51 includes a dry etching operation. In some embodiments, the dry etching operation stops at the exposure of second liner 34 (or the exposure of the material of second liner 34 ).

In some embodiments, the conductive pad 52 covers at least the porous pillar 33 and the conductive via 45 . In some embodiments, the conductive pad 52 covers all of the porous posts 33 and all of the conductive vias 45 . In some embodiments, the conductive pad 52 is electrically connected to the conductive via 45 . In some embodiments, conductive pad 52 is in physical contact with conductive via 45 . In some embodiments, the conductive pads 52 are electrically connected to the metal lines 124 of the interconnect structure 12 of the substrate 10 through the conductive vias 45 .

Referring to FIG. 22 , FIG. 22 is a cross-sectional view illustrating the preparation stage of the preparation method S1 of some embodiments of the present disclosure. After operation S16, the photoresist layer 62 is removed. In some embodiments, a wet etching operation is performed to remove photoresist layer 62 . In some embodiments, after removing the photoresist layer 62, a post-cleaning operation may optionally be performed.

Referring to FIG. 23, FIG. 23 is a cross-sectional view illustrating the preparation stage of the preparation method S1 of some embodiments of the present disclosure. After the photoresist layer 62 is removed, a passivation material 53 is formed on the conductive pad 52 . In some embodiments, passivation material 53 is disposed on conductive pad 52 and second pad 34 . In some embodiments, passivation material 53 contacts conductive pad 52 and second pad 34 . In some embodiments, passivation material 53 is in contact with conductive pad 52 and second pad 34 . In some embodiments, passivation material 53 covers all of conductive pad 52 . In some embodiments, top surface 531 of passivation material 53 is substantially planar. In other embodiments, the top surface 531 of the passivation material 53 conforms to the contours of the conductive pad 52 and the second pad 34 , depending on how the passivation material 53 is made.

Referring to FIG. 24 , FIG. 24 is a cross-sectional view illustrating the preparation stage of the preparation method S1 of some embodiments of the present disclosure. After the passivation material 53 is formed, a photoresist layer 63 is formed on the passivation material 53 . In some embodiments, a portion of passivation material 53 is bounded by and exposed through photoresist layer 63 . Photoresist layer 63 is configured to protect portions of passivation material 53 covered by photoresist layer 63 during subsequent patterning operations.

Referring to FIG. 25 , FIG. 25 is a cross-sectional view illustrating the preparation stage of the preparation method S1 of some embodiments of the present disclosure. After photoresist layer 63 is formed, passivation material 53 is patterned to form passivation layer 54 . In some embodiments, a portion of passivation material 53 exposed through photoresist layer 63 is removed via patterning operation 83 . In some embodiments, patterning operation 83 includes ion beam etching, directional dry etching, reactive ion etching, or a combination thereof. In some embodiments, patterning operation 83 on passivation material 53 includes a dry etching operation. In some embodiments, dry The etching operation stops at the exposure of passivation material 53 (or passivation layer 54).

In some embodiments, at least a portion of conductive pad 52 is exposed through passivation layer 54 . In some embodiments, at least a portion of the top surface 521 of the conductive pad 52 is exposed through the passivation layer 54 . As shown in FIG. 25 , passivation layer 54 covers the perimeter of top surface 521 of conductive pad 52 . In other embodiments, the entire top surface 521 of conductive pad 52 is exposed through passivation layer 54 . In some embodiments, passivation layer 54 covers at least sidewalls 522 of conductive pad 52 . At least a portion of the top surface 521 of the conductive pad 52 is exposed for electrical connection with other electrical components or components.

Referring to FIG. 26 , FIG. 26 is a cross-sectional view illustrating the preparation stage of the preparation method S1 of some embodiments of the present disclosure. After the patterning operation 83 shown in Figure 25, the photoresist layer 63 is removed. In some embodiments, a wet etching operation is performed to remove the photoresist layer 63 . In some embodiments, after removing the photoresist layer 63, a post-cleaning operation may be optionally performed.

As shown in FIG. 26, a semiconductor structure 200 similar to semiconductor structure 100 is thus formed. In some embodiments, the porous pillars 33 are designed to be in the central region 523 of the conductive pad 52 and the conductive vias 45 are designed to be in the peripheral region 524 of the conductive pad 52 . In some embodiments, the top view of the conductive pad 52 of the semiconductor structure 200 shown in FIG. 26 may be similar to that shown in FIG. 2 , wherein the configuration shown in FIG. 26 may be a cross-section along line AA'. However, from a top view, the configuration of the conductive vias 45 is not limited here.

Referring to FIG. 27 , FIG. 27 is a top view illustrating the conductive pad 52 , the porous pillar 33 , the first pad 31 and the conductive via 45 of the semiconductor structure 200 according to some embodiments of the present disclosure. In some embodiments, the semiconductor structure 200 shown in FIG. 26 may be a cross-section along line BB′ shown in FIG. 27 . In some embodiments, each conductive via 45 has an annular shape. In some embodiments, each of the conductive vias 45 has a square ring configuration. In some embodiments, each conductive pass The holes 45 surround the porous pillar 33 and/or the first pad 31 . In some embodiments, each conductive via 45 surrounds the porous pillar 33 and/or the first pad 31 . In some embodiments, the top cross-sectional area of the conductive vias 45 is substantially larger than the top cross-sectional area of the porous pillars 33 to achieve the purpose of reducing resistance and improving conductivity.

The present disclosure provides a semiconductor structure and a method of manufacturing the structure. The semiconductor structure of the present disclosure includes a porous structure, particularly between the uppermost metal layer of the interconnect structure and the conductive pad covered by the passivation layer. The porous structure has the function of absorbing stress on the semiconductor structure (eg, bonding stress during the manufacturing process) and can improve the force tolerance of the semiconductor structure. Therefore, damage or defects caused by forces or stresses on the semiconductor structure (eg, during a bonding process of the semiconductor structure to another wafer, wafer, or electrical structure) may be prevented. Product yield and performance can be improved as a result.

FIGS. 28 to 31 are schematic diagrams illustrating various manufacturing stages constructed by the manufacturing method S1 of the semiconductor structure 300 according to an alternative embodiment of the present disclosure. The stages shown in FIGS. 28 to 31 are also schematically illustrated in the preparation flow chart of FIG. 3 . In the ensuing discussion, the preparation stages shown in FIGS. 28 to 31 are discussed with reference to the preparation steps in FIG. 3 .

For ease of explanation, reference numerals with similar or identical functions and characteristics are repeated in different embodiments and figures. For the sake of brevity, in the following description, only the differences from the above-described embodiments are emphasized, and descriptions of similar or identical elements, functions, characteristics and/or processes are omitted.

Referring to FIG. 28 , FIG. 28 is a cross-sectional view illustrating the preparation stage of the preparation method S1 of some embodiments of the present disclosure. In some embodiments, an etching operation 84 is performed on the first liner 31 of the intermediate structure shown in FIG. 9 prior to forming the energy removable material 32 . In some embodiments, etch operation 84 includes a directional etch operation. In some embodiments, above dielectric layer 21 and The horizontal portion of the first pad 31 in the opening 91 is removed. In some embodiments, the remaining portion of first pad 31 becomes third pad 35 . In some embodiments, third gasket 35 lines sidewall 911 of opening 91 . In some embodiments, after etching operation 84, a portion of substrate 10 (or metal lines 124 of substrate 10) is exposed. In other words, after the etching operation 84, the bottom surface 912 of the opening 91 may be exposed.

Referring to FIG. 29, FIG. 29 is a cross-sectional view illustrating the preparation stage of the preparation method S1 of some embodiments of the present disclosure. Operations similar to those shown in FIGS. 10 to 14 are applied to the intermediate structure shown in FIG. 28 , and the second liner 34 is formed on the porous pillar 33 , the third liner 35 and the dielectric layer 21 . In some embodiments, the top surface 331 of the porous pillar 33 is substantially aligned with the top surface 211 of the dielectric layer 21 and/or the top surface 351 of the third pad 35 . In some embodiments, the top surface 331 of the porous pillar 33 is substantially coplanar with the top surface 211 of the dielectric layer 21 and/or the top surface 351 of the third pad 35 . In some embodiments, second pad 34 is in contact with top surface 211 of dielectric layer 21 .

Referring to FIG. 30 , FIG. 30 is a cross-sectional view illustrating the preparation stage of the preparation method S1 of some embodiments of the present disclosure. An operation similar to that shown in Figure 15 is applied to the intermediate structure shown in Figure 29, and openings 93 are formed. In some embodiments, opening 93 surrounds porous post 33 and third liner 35 (further explanation is provided in the description below). In some embodiments, opening 93 is defined by dielectric layer 21 and second pad 34 .

Referring to FIG. 31 , FIG. 31 is a cross-sectional view illustrating the preparation stage of the preparation method S1 of some embodiments of the present disclosure. Operations similar to those shown in FIGS. 16 to 26 are applied to the intermediate structure shown in FIG. 30 , and the semiconductor structure 300 is thereby formed. In some embodiments, a conductive via 45 is formed surrounding the porous post 33 .

Referring to FIG. 32, FIG. 32 is a top view illustrating a semiconductor device according to some embodiments of the present disclosure. The conductive pad 52, the porous pillar 33, the third pad 35 and the conductive via 45 of the bulk structure 300. In some embodiments, the semiconductor structure 300 shown in FIG. 31 may be a cross-section along line CC′ shown in FIG. 32 . In some embodiments, semiconductor structure 300 includes only a single conductive via 45 . In some embodiments, conductive vias 45 surround or surround porous posts 33 and third pad 35 . It should be noted that the structures of the conductive vias 45 and the porous pillars 33 are not limited here. In the embodiment shown in FIG. 32 , the conductive vias 45 are rectangular rings surrounding the rectangular porous posts 33 . In other embodiments, both the conductive via 45 and the porous pillar 33 may be circular, and the conductive via 45 may be a circular ring or a polygonal ring. In some embodiments, the shape of conductive vias 45 may correspond to the shape of porous pillars 33 shown in FIG. 32 . In other embodiments, the shapes of the conductive vias 45 and the porous pillars 33 may be different.

One aspect of the present disclosure provides a semiconductor structure. The semiconductor structure includes: a substrate including an interconnection structure; a dielectric layer disposed on the substrate; a porous pillar disposed on the substrate and extending through the dielectric layer; a first moisture-proof layer, Surrounding the porous pillar and disposed in the dielectric layer; a conductive via extending in the dielectric layer and disposed adjacent to the porous post; and a conductive pad disposed on the dielectric layer and covering the conductive via and the porous column.

Another aspect of the present disclosure provides a method of fabricating a semiconductor structure. The preparation method includes: forming a dielectric layer on a substrate; forming an opening in the dielectric layer; forming a first pad conforming to the opening; forming a porous layer in the opening and being covered by the opening. The first liner surrounds; forming a conductive via hole penetrating the dielectric layer; and forming a conductive pad on the dielectric layer, wherein the conductive pad covers the porous layer and the conductive via hole.

In summary, this application discloses a method for preparing a semiconductor structure and a semiconductor structure thereof. The semiconductor structure disclosed herein includes a porous structure, particularly between the uppermost metal layer of the interconnect structure and the conductive pad covered by the passivation layer. The porous structure has an absorbing semiconductor Stress on the structure (eg, bonding stress during processing) and can improve the force tolerance of the semiconductor structure. Thus, damage or defects caused by forces or stresses on the semiconductor structure (eg, during bonding of the semiconductor structure to another wafer, wafer, or electrical structure) may be prevented. Product yield and performance can be improved as a result.

Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as claimed. For example, many of the processes described above may be implemented in different ways and may be substituted for many of the processes described above with other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. Those skilled in the art will understand from the disclosure of this disclosure that existing or future developed processes, machines, manufacturing, etc. can be used in accordance with the disclosure to have the same function or achieve substantially the same results as the corresponding embodiments described herein. A material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patentable scope of this application.

10: Base 12:Interconnect structure 21: Dielectric layer 31: first liner 33: Porous layer 34:Second pad 45:Conductive vias 52:Conductive pad 54: Passivation layer 100:Semiconductor Structure 123: Intermetal dielectric (IMD) layer 124:Metal wire 331:Top surface 332: Bottom surface Mn: metal layer

Claims (18)

A semiconductor structure includes: a substrate including an interconnection structure; a dielectric layer disposed on the substrate; a conductive pad disposed on the dielectric layer; a passivation layer disposed on the dielectric layer and The conductive pad is partially exposed; and a porous layer is surrounded by the dielectric layer and extends between the substrate and the conductive pad; wherein from a top view, the porous layer is disposed in a central area of the conductive pad . The semiconductor structure of claim 1, further comprising: a first liner surrounding the porous layer and disposed in the dielectric layer, wherein the first liner at least partially surrounds one side wall of the porous layer and a bottom surface. The semiconductor structure of claim 2, wherein the first liner surrounds a side wall of the porous layer, and the porous layer is in contact with the substrate. The semiconductor structure of claim 1, further comprising: a conductive via disposed adjacent to the porous layer and electrically connected to the conductive pad and the interconnect structure. The semiconductor structure of claim 4, wherein a portion of the dielectric layer is disposed between the conductive via and the porous layer. The semiconductor structure of claim 4, wherein a top cross-sectional area of the conductive via hole is substantially larger than a top cross-sectional area of the porous layer. The semiconductor structure of claim 4, wherein the conductive via extends through the dielectric layer. The semiconductor structure of claim 4, wherein the conductive vias include a plurality of conductive vias, the plurality of conductive vias are separated from each other, and the plurality of conductive vias are covered by the conductive pad. The semiconductor structure of claim 1, wherein the porous layer has a porosity between 5% and 30%. The semiconductor structure as claimed in claim 1, wherein the porous layer has a porosity between 10% and 15%. The semiconductor structure of claim 2, further comprising: a second liner disposed between the porous layer and the conductive pad, wherein the porous layer is surrounded by the first liner and the second liner. A semiconductor structure includes: a substrate including an interconnect structure; a dielectric layer disposed on the substrate; a porous pillar disposed on the substrate and extending through the dielectric layer; a first moisture-proof layer surrounding the porous column and disposed in the dielectric layer; a conductive via extending in the dielectric layer and disposed adjacent to the porous column; and a conductive pad disposed on the dielectric layer , covering the conductive via and the porous pillar; wherein the first moisture-proof layer includes nitride, high-k material or a combination thereof. The semiconductor structure of claim 12, further comprising: a second moisture-proof layer disposed between the porous pillar and the conductive pad. The semiconductor structure of claim 13, wherein the conductive via penetrates the second moisture-proof layer and contacts the conductive pad. The semiconductor structure of claim 13, further comprising: a passivation layer disposed on the dielectric layer and separated from the dielectric layer by the second moisture-proof layer. The semiconductor structure of claim 12, wherein the porous pillars include one or more low-k (dielectric constant) materials. The semiconductor structure of claim 12, wherein the conductive via includes tungsten, copper, cobalt, ruthenium, molybdenum or a combination thereof. The semiconductor structure of claim 12, wherein the conductive via hole includes a barrier component and a conductive component surrounded by the conductive via hole, and the barrier component includes titanium, tantalum, titanium nitride, nitride Tantalum or combinations thereof.