TWI825802B - A method for controlling data storage device - Google Patents

Abstract

The present disclosure provides a method for controlling a data storage device. The method includes: storing a first data in a first area of a memory module of the data storage device; storing a second data in a second area of the memory module, wherein the second data is associated with the first; reading the first data and the second data via a first communication interface; and in response to the read first data and second data, generating a first output signal.

Description

A method of controlling data storage device

This application claims priority to U.S. Patent Application Nos. 17/737,726 and 17/737,689 (that is, the priority date is "May 5, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a control method for a data storage device, and in particular, to a control method for a data storage device to store associated data in at least two areas.

Error correction code (ECC) is widely used in data storage technology to detect or correct data corruption. However, some controllers will not enable the ECC function until data is received. Any data corruption that occurs in the received data will affect the controller's ECC functionality.

The above description of "prior art" is only to provide background technology, and does not admit that the above description of "prior art" reveals the subject matter of the present disclosure. It does not constitute prior art of the present disclosure, and any description of the above "prior art" None should form any part of this case.

One aspect of the present disclosure provides a control method for a data storage device, including: storing a first data in a first area of a memory module of the data storage device; and storing a first data in a second area of the memory module. store a second data in, wherein the second data is associated with the first data; read the first data and the second data through the first communication interface; and in response to the read first data and the second data two data to generate a first output signal.

Another aspect of the present disclosure provides a data storage device. The data storage device includes a first area and a second area. The first area is configured to store a first data. The second area is configured to store a second data. The second data is associated with the first data. The first data and/or the second data do not include an error correction code (ECC).

Another aspect of the present disclosure provides a non-transitory computer-readable medium storing a program including instructions that, when executed by a processor, cause a data storage device to: store a first region in a memory. a data; storing a second data in a second area of the memory, wherein the second data is associated with the first data; reading the first data and the second data through a first communication interface; and generating a first output signal in response to the read first data and second data.

The data storage device of the present disclosure includes a memory controller and a memory module. The memory module includes a first area and a second area. The first area and the second area are configured to store a first data and a second data respectively. The first data is associated with the second data to form a data pair. The first data may be normal data, and the second data may be encoded data. The memory controller is configured to read the first data and the second data through a communication interface, and then generate an output signal based on the read first data and second data. Generating the output signal includes performing a logical operation on the first data and the second data. When the output signal has a first value, it indicates that the first data and the second data have no data corruption. When the output signal has a second value, it indicates that one of the first data and the second data has data corruption on its bits. This determination of the value of the output signal can be repeated for other data pairs. The data storage device of the present disclosure can detect whether the data pair is correct without using error correction code (ECC). This is advantageous for memory controllers with passive ECC functionality, that is, enabling the ECC function after receiving data. Such a memory controller can still read the correct data directly from the memory module. The risk of erroneously triggering the memory controller's ECC function with incorrect data can be reduced.

The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be readily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

Specific language will now be used to describe the embodiments, or examples, of the present disclosure illustrated in the drawings. It should be understood that there is no intention to limit the scope of the present disclosure. Any changes or modifications to the described embodiments, and any further applications of the principles described herein, are deemed to be commonly made by one of ordinary skill in the art to which this disclosure relates. Reference numbers may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment apply to another embodiment, even if they share the same reference number.

It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers or sections, these elements, elements, regions, layers or sections are not limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the inventive concept.

The terminology used herein is for describing particular embodiments only and is not intended to limit the concepts of the invention. As used herein, the singular forms "a", "an" and "the" also include the plural forms unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and "includes", when used in this specification, indicate the presence of stated features, integers, steps, operations, elements or components, but do not exclude the presence or addition of one or more other Characteristic, integer, step, operation, element, component, or group thereof.

FIG. 1 is a block diagram illustrating a data storage device 100 and a host device 50 according to some embodiments of the present disclosure. The data storage device 100 may include a portable or non-portable data storage device, such as a memory card complying with the SD/MMC, CF, MS or XD standards, a non-volatile (NV) memory device, a flash memory device, Flash memory device or solid state drive (SSD). The host device 50 may include a multifunctional mobile phone, a tablet computer, a wearable device, and a personal computer such as a desktop computer or a notebook computer. The data storage device 100 may communicate with the host device 50 through wiring, a system bus, or wirelessly. Data may be transferred between data storage device 100 and host device 50 .

As shown in FIG. 1 , the data storage device 100 may include a memory module 1 and a memory controller 2 . The memory controller 2 can communicate with the memory module 1 through wiring, system bus or wireless means. Memory controller 2 may be configured to access memory module 1 . Memory module 1 can be configured to store data. Memory controller 2 may include an NV memory controller, a flash memory controller, or the like. The memory module 1 may include an NV memory module, a flash memory module, or similar modules. In some embodiments, the memory controller 2 of the data storage device 100 may include the functionality of a host device, so the data storage device 100 may not be connected to the host device.

In some embodiments, the memory controller 2 can write system operation information into the memory module 1, such as redundant array of independent disk (RAID) information, error correction code (error correction code) , ECC) parity, mapping table, control flag, etc. System operation information can be added at any step in writing data, such as a data randomization process (Process) or similar process.

As shown in FIG. 1 , the memory controller 2 may include a communication interface 21 , a microprocessor 22 (or processor), a memory 23 and a communication interface 24 , wherein these components may be coupled to each other through a bus.

The host device 50 can indirectly access the memory module 1 in the data storage device 100 by sending a plurality of host device commands and corresponding logical addresses to the memory controller 2 . The memory controller 2 can receive a plurality of host device commands and logical addresses through the communication interface 21 . The memory controller 2 can translate a plurality of host device commands into memory operation commands, and then control the memory module 1 to read and write memory units or pages with specific physical addresses in the memory module 1 /program or erase. Physical addresses can correspond to logical addresses.

Communication interface 21 may receive or send one or more host device commands. The communication interface 21 can receive or send data, where the data can include one or a plurality of logical addresses, or data pages. The communication interface 24 may receive or send one or more memory operation commands. The communication interface 24 can receive or send data, where the data can include one or more physical addresses, or data pages. The communication interface 21 may be a bus protocol for communication from the host device 50 , for example, an integrated circuit therein, to the microprocessor 22 , or the memory 23 of the memory controller 2 . The communication interface 24 may be a bus protocol used for communication from the memory controller 2 to the memory module 1 . The communication interface 21 or the communication interface 24 may comply with a specific communication specification (for example, Serial Advanced Technology Attachment (SATA) specification, Universal Serial Bus (USB) specification, Peripheral Component Interconnect Express (PCIE) specification) or comply with non-volatile memory VMware (NVMe) and can perform communication according to its specific communication specifications. The communication interface 21 may be an NVMe interface. Communication interface 24 may be a flash memory interface.

The microprocessor 22 of the memory controller 2 may have a functional block configured to perform logical operations OP1 based on data read from the memory module 1 . The logical operation OP1 includes at least one of AND, NAND, OR, NOR, NOT, XOR, and XNOR.

Memory 23 may be configured to store information, such as data paging, or host device commands from host device 50 . Memory 23 may be implemented using random access memory (RAM). Memory 23 may be configured to store programs 23P executable by microprocessor 22.

The microprocessor 22 may be configured to execute the program 23P stored in the memory 23 to cause the data storage device 100 to perform a plurality of operations, such as reading, writing, or erasing. Program 23P may be stored in a non-transitory computer-readable medium of memory 23 .

The memory module 1 may include a buffer memory 3 and a storage block group 4 including storage blocks 41, 42, 43, 44, wherein these components may be coupled to each other through a bus. In some embodiments, storage block group 4 may include more storage blocks. The buffer memory 3 can communicate with the memory controller 2, for example, the communication interface 24. Buffer memory 3 may be configured to store one or more memory operation commands from memory controller 2 . Buffer memory 3 may be configured to store data including physical addresses from memory controller 2 . Buffer memory 3 can be configured to store data pages. The storage block group 4 may include, but is not limited to, a plurality of flash memory chips or components. Storage blocks 41, 42, 43, 44 may include SLC, MLC, TLC, or QLC.

There are various fabrication technologies for memory module 1; for example, two-dimensional/planar NAND flash memory technology, in which the memory cells are arranged in a single layer, and three-dimensional NAND flash memory technology, in which the memory cells are arranged in a single layer. Multiple layers and stacked vertically. According to some embodiments, the memory module 1 may be implemented as a planar NAND flash memory architecture with a single layer of memory cells. According to some embodiments, the memory module 1 may be implemented as a three-dimensional NAND flash memory architecture in which memory cells are vertically stacked in multiple layers.

Still referring to FIG. 1 , host device 50 may include communication interface 51 . The communication interface 51 can transmit one or more host device commands. The communication interface 51 can receive or transmit data, where the data can include one or more logical addresses, or data pages. The communication interface 51 may comply with a specific communication specification (e.g., Serial Advanced Technology Attachment (SATA) specification, Universal Serial Bus (USB) specification, Peripheral Component Interconnect Express (PCIE) specification) or non-volatile memory storage device ( NVMe) and can perform communication according to its specific communication specifications. The communication interface 51 may be an NVMe interface.

In some embodiments, host device 50 may include host memory 52 , which may be part of the internal storage of host device 50 .

FIG. 2 is a block diagram illustrating the memory module 1 of the data storage device 100 according to some embodiments of the present disclosure. Each of blocks 41, 42, 43 and 44 includes a plurality of pages. As shown in Figure 2, block 41 includes pages 410, 411, ..., 431. The number of pages can be 32. In some embodiments, the number of pages may vary, such as 64 or more. Each page 410, 411, ..., 431 can be configured to store data. The data stored in the pages 410, 411, ..., 431 can be read through the communication interface 24 in response to address signals, data signals or command signals from the memory controller 2. The data stored in the pages 410, 411, ..., 431 can be stored in the buffer memory 3.

FIG. 3 is a block diagram illustrating the paging 410 of the block 41 of the memory module 1 according to some embodiments of the present disclosure. As shown in FIG. 3 , the paging 410 may include a first area 410A and a second area 410B. In other words, the first area 410A and the second area 410B are on the same page (eg, page 410) of the memory module 1. The first area 410A may be configured to store the first data D11. The second area 410B may be configured to store the second data D12. The second data D12 can be associated with the first data D11 to form a data pair. The first data D11 and/or the second data D12 may not include ECC. In some embodiments, the first data D11 is encoded into the second data D12. In this case, the first data D11 can be regarded as normal data, and the second data D12 can be regarded as encoded data. In some embodiments, the second data D12 and the first data D11 are complementary to each other. In some embodiments, the first data D11 and the second data D12 are the same.

FIG. 4 is a block diagram illustrating a plurality of pages 410 and 411 of the memory module 1 of the data storage device 100 according to some embodiments of the present disclosure. For a detailed description of paging 410, reference may be made to the embodiment shown in FIG. 3 . As shown in FIG. 4 , the paging 411 may include a third area 411A and a fourth area 411B. In other words, the third area 411A and the fourth area 411B are on the same page of the memory module 1 (for example, page 411). The third area 411A may be configured to store the third data D11'. The fourth area 411B may be configured to store fourth data D12'. The fourth data D12' may be associated with the third data D11' to form a data pair. The third data D11' and/or the fourth data D12' may not include ECC. In some embodiments, the third data D11' is encoded as fourth data D12'. In this case, the third data D11' can be regarded as normal data, and the fourth data D12' can be regarded as encoded data. In some embodiments, the fourth data D12' and the third data D11' are complementary to each other. In some embodiments, the third data D11' and the fourth data D12' are the same.

The first data D11 and the third data D11' may correspond to the same original data. The third data D11' may correspond to the first data D11. If data corruption occurs during the writing operation of the first data D11 and/or the third data D11', the first data D11 and the third data D11' may be different. If no data corruption occurs, the first data D11 and the third data D11' are the same. The second data D12 and the fourth data D12' may correspond to the same original data. If data corruption occurs during the writing operation of the second data D12 and the fourth data D12', the second data D12 and the fourth data D12' may be different. If no data corruption occurs, the second data D12 and the fourth data D12' are the same.

Additionally, there may be more pages in storage block 41, including two areas configured to store two interrelated data.

FIG. 5 is a schematic diagram illustrating a writing sequence in a data storage device (eg, data storage device 100 ) and a host device (eg, host device 50 ) according to some embodiments of the present disclosure. As discussed in the following paragraphs/sections, the operations disclosed in the embodiment of FIG. 3 can be controlled by the microprocessor 22 executing the program 23P stored in the memory 23 .

As shown in FIG. 5 , the host device 50 may transmit data or host device commands to the data storage device 100 ( S10 ). The communication interface 21 of the data storage device 100 may be configured to receive data or host device commands from the host device 50 (S10). Communication interface 21 may be configured to receive raw data D0 from host device 50 . The original data D0 may include a data page. In another embodiment, the original data D0 may include a plurality of data pages. The communication interface 21 may be configured to transmit the raw data D0 to the microprocessor 22 (S11). Microprocessor 22 may be configured to receive raw data DO (S11). After being received by the microprocessor 22 of the memory controller 2, the original data D0 may be programmed into the first data D11 to comply with the specific communication specification used in the communication interface 24. In some embodiments, the original data D0 and the first data D11 are the same. In some embodiments, the microprocessor 22 of the memory controller 2 may be configured to encode the original data D0 into the second data D12. The second data D12 may be complementary to the original data D0. In some embodiments, the memory controller may disable the ECC function, such that the first data and/or the second data may not include ECC. The microprocessor 22 of the memory controller 2 may be configured to transmit the first data D11 and the second data D12 to the communication interface 24 (S12). The communication interface 24 may be configured to transmit the first data D11 and the second data D12 together with the address signal and the write command to the memory module 1, for example, the buffer memory 3 (S13). The buffer memory 3 may be configured to buffer the first data D11 and the second data D12. The buffer memory 3 may be configured to transmit the first data D11 to the first area 410A of the page 410 in the block 41, as shown in FIGS. 3 and 4, in response to the address signal and the write command (S14) . Similarly, the buffer memory 3 may be configured to transmit the second data D12 to the second area 410B of the page 410 in the block 41 in response to the address signal and the write command (S14).

In addition, the microprocessor 22 may be configured to copy the first data D11 and the second data D12 into the third data D11' and the fourth data D12' respectively. The microprocessor 22 may be configured to transmit the third data D11' and the fourth data D12' together with the address signal and the write command to the communication interface 24 (S12), which in turn transmits these data together with the address signal and the write command. The command is sent to memory module 1 (S13). The buffer memory 3 may be configured to transmit the third data D11' in the block 41 to the third area 411A of the page 411, as shown in FIGS. 3 and 4, in response to the address signal and the write command (S14) . Similarly, the buffer memory 3 may be configured to transmit the second data D12 to the fourth area of the page 411B in the block 41 in response to the address signal and the write command (S14). In some embodiments, the microprocessor 22 of the memory controller 2 may be configured to repeatedly transmit raw data and encoded data with updated specific communication specifications to different parts of the same storage block (eg, storage block 41 ). Paging (for example, the first data D11 and the second data D12 in the page 410, the third data D11' and the fourth data D12' in the page 411).

The writing sequence shown in Figure 5 can be repeated until all original data D0 is written. Therefore, the operation shown in Figure 5 may require multiple pages to store the original data D0. Therefore, the data storage device can store the original data D0 in a space that is twice as large as the conventional technology.

In another embodiment, the first data D11, the second data D12, the third data D11' and/or the fourth data D12' can be obtained by electronic equipment, such as a programmer, a device programmer, a chip programmer. Or program the NAND programmer into memory module 1.

FIG. 6 is a schematic diagram illustrating a reading sequence in a data storage device (eg, data storage device 100 ) and a host device (eg, host device 50 ) according to some embodiments of the present disclosure. As discussed in the following paragraphs/sections, the operations disclosed in the embodiment of FIG. 3 can be controlled by the microprocessor 22 executing the program 23P stored in the memory 23 .

As shown in FIG. 6 , the host device 50 may be configured to transmit a host device command to the communication interface 21 of the data storage device 100 ( S20 ). The host device command may cause the data storage device 100 to provide storage data associated with the original data D0. Communication interface 21 may be configured to transmit host device commands to microprocessor 22 (S21). The microprocessor 22 may be configured to process host device commands and further generate address signals and read commands for reading data stored in the memory module 1 associated with the original data D0. In some embodiments, the first data D11 and the second data D12 stored in the page 410 in the block 41 of the memory module 1 are associated with the original data D0. Microprocessor 22 may be configured to transmit the address signal and read command to communication interface 24 (S22). The communication interface 24 may be configured to transmit the address signal and the read command to the memory module 1, such as the buffer memory 3 (S23).

The buffer memory 3 may be configured to read the first data D11 from the first area 410A of the page 410 and read the second data D12 from the second area 410B of the page 410 (S24). The buffer memory 3 may be configured to buffer the first data D11 and the second data D12. The buffer memory 3 may be configured to transmit the first data D11 and the second data D12 to the communication interface 24 (S25). The communication interface 24 may be configured to transmit the first data D11 and the second data D12 to the microprocessor 22 (S26). In other words, the memory controller 2 can be configured to read the first data D11 and the second data D12 through the communication interface 24 in response to the address signal and the read command. The memory controller 2 may be configured to generate the first output signal OUT1 in response to the first data D11 and the second data D12. The first output signal OUT1 may be stored in the memory 23 . The microprocessor 22 of the memory controller 2 may have a functional block to generate the first output signal OUT1. The functional blocks of the microprocessor 22 may be configured to perform logical operations OP1 based on data pairs (eg, first data D11 and second data D12). The logical operation OP1 includes at least one of AND, NAND, OR, NOR, NOT, XOR, and XNOR.

In some embodiments, the first data D11 may be complementary to the second data D12. For example, when the first data D11 is 55 in hexadecimal, the second data D12 is AA in hexadecimal. In another example, when the first data D11 is 88 in hexadecimal, the second data D12 is 77 in hexadecimal. However, in another example, when the first data D11 is binary 01010101, the second data D12 is binary 10101010. The microprocessor 22 of the memory controller 2 may be configured to perform the XOR operation OP1 on the first data D11 and the second data D12. The microprocessor 22 of the memory controller 2 may be configured to generate a first output signal OUT1 having a first value VA1, such as hexadecimal FF, when the first data D11 and the second data D12 are complementary to each other. The first value VA1 represents the bits in the page 410 storing the first data D11 and the second data D12. As shown in FIG. 3, there is no data corruption (that is, there are no erroneous bits). Therefore, the memory controller 2 may be configured to transmit the first data D11 to the communication interface 21 (S27). The communication interface 21 may be configured to transmit the first data D11 to the host device 50 (S28). In other words, when the first output signal OUT1 has the first value VA1 , the memory controller 2 is configured to transmit the first data D11 to the host device 50 through the communication interface 21 . In some embodiments, the first data D11 and/or the second data D12 may have incorrect bits or data corruption. Therefore, the microprocessor 22 of the memory controller 2 may be configured to generate the first output signal OUT1 having a second value VA2 that is different from the first value VA1.

When the first output signal OUT1 has the second value VA2, the memory controller 2 may also be configured to transmit the address signal and the read command to the communication interface 24 (S22'). The communication interface 24 may be configured to transmit the address signal and the read command to the memory module 1 (S23'). The buffer may be configured to read the third data D11' and the fourth data D12' in response to the address signal and the read command (S24'). The buffer memory 3 may be configured to buffer the third data D11' and the fourth data D12'. The buffer memory 3 may be configured to transmit the third data D11' and the fourth data D12' to the communication interface 24 (S25'). The communication interface 24 may be configured to transmit the third data D11' and the fourth data D12' to the microprocessor 22 (S26'). In other words, the memory controller 2 may be configured to read the third data D11 ′ and the fourth data D12 ′ through the communication interface 24 in response to the address signal and the read command from the memory controller 2 . The memory controller 2 may be configured to generate the second output signal OUT2 in response to the third data D11' and the fourth data D12'. The second output signal OUT2 may be stored in the memory 23 of the memory controller 2 .

In some embodiments, the third data D11' may be complementary to the fourth data D12'. The microprocessor 22 of the memory controller 2 may be configured to perform an XOR operation on the third data D11' and the fourth data D12'. The microprocessor 22 of the memory controller 2 may be configured to generate the second output signal OUT2 having the third value VA3 when the third data D11' and the fourth data D12' are complementary to each other. The third value VA3 represents the bits in the page 411 storing the third data D11' and the fourth data D12'. As shown in FIG. 3, there is no data corruption (for example, no erroneous bits). Therefore, the memory controller 2 may be configured to transmit the third data D11' to the communication interface 21 (S27'). The communication interface 21 may be configured to transmit the third data D11' to the host device 50 (S28'). In other words, when the second output signal OUT2 has the third value VA3, the memory controller 2 may be configured to transmit the third data D11' to the host device 50 through the communication interface 21. In some embodiments, the third data D11' and/or the fourth data D12' may have incorrect bits or data corruption. Therefore, the microprocessor 22 of the memory controller 2 may be configured to generate the second output signal OUT2 having a fourth value VA4 that is different from the third value VA3.

When the second output signal OUT2 has the fourth value VA4, the memory controller 2 may also be configured to read the memory stored in the memory through the communication interface 24 in response to the address signal and/or the command signal from the memory controller 2. Other data (or other pairs of data) in other areas of phantom set 1. Other data can be associated with the original data D0. Other data may be the first data D11 and the second data D12 corresponding to each other. In other words, the other data and one of the first data D11 may correspond to the same original data. Memory controller 2 may also be configured to generate other output signals based on the other data. The memory controller 2 may be configured to determine whether the stored other data has data corruption based on other output signals. Memory controller 2 may be configured to transmit one of the other data to host device 50 through communication interface 24 when it is determined that the other data is not data corrupt. In some embodiments, memory controller 2 may be configured to read more other data stored in communication interface 24 until memory controller 2 reads the correct data.

In some comparative embodiments, the memory controller may have a passive ECC function, which means that the memory controller enables the ECC function after reading data stored in the memory module. The data read first must eliminate any incorrect bits or data corruption. Otherwise, the memory controller's ECC function may not be enabled or may work incorrectly. Therefore, the reliability requirements for the memory unit storing the so-called first-read data are very strict. Such memory cells must be free of defects, which is almost impossible to guarantee in manufacturing. In the present disclosure, the memory controller 2 can store the data pairs (eg, the first data D11 and the second data D12) associated with the original data D0 in different areas of the same page. In response to a command from the host device to read data associated/corresponding to the original data D0 stored in the memory module 2, the memory controller 2 may be configured to read at least one data pair. Memory controller 2 may be configured to determine whether the bits storing the data pair are free of data corruption. Based on this determination, memory controller 2 may be configured to transfer the normal data of the data pair to the host device (eg, host device 50) or read other data pairs associated/corresponding to the original data D0. This determination can be repeated until a data pair with no data corruption is found. Therefore, the data storage device 100 can still directly read correct data without the ECC function. The risk of erroneously triggering the ECC function of the memory controller 2 with incorrect data can be reduced.

In some embodiments, the microprocessor 22 of the memory controller 2 may be configured to perform an ADD operation when the first data D11 and the second data D12 are determined to be the same and no data corruption occurs. Depending on the type of the data pair (eg, the first data D11 and the second data D12), the microprocessor 22 of the memory controller 2 may be configured to perform a logical operation to determine whether the data pair has data corruption.

FIG. 7 is a block diagram illustrating pages 410 of the memory module 1 of the data storage device 100 according to some embodiments of the present disclosure. As shown in FIG. 7 , paging 410 includes a first plurality of sub-regions 4101, 4103, ..., 410N. Paging 410 includes a second plurality of sub-regions 4102, 4104, ..., 410M. The first plurality of sub-regions 4101, 4103, ..., 410N and the second plurality of sub-regions 4102, 4104, ..., 410M are interleaved with each other.

The first plurality of sub-regions 4101, 4103, ..., 410N may include a first plurality of data D21, D22, ..., D2N (eg, normal data). The second plurality of sub-regions 4102, 4104, ..., 410M may include a second plurality of data D31, D32, ..., D3N (eg, encoded data). Each of the first plurality of data D21, D22, ..., D2N may be associated with a corresponding one of the second plurality of data D31, D32, ..., D3N. For example, data D21 may be associated with data D31. Data D31 and data D21 are complementary to each other. The data storage device 100 can read correct data from the data pair of normal data D21, D22, ..., D2N and encoded data D31, D32, ..., D3N through the operations shown in FIG. 5 and FIG. 6 .

FIG. 8 is a block diagram illustrating pages 410 and 411 of the memory module 1 of the data storage device 100 according to some embodiments of the present disclosure. For a detailed description of paging 410, reference may be made to the embodiment shown in FIG. 7 . As shown in FIG. 7 , paging 411 includes third plural sub-regions 4111, 4113, ..., 411N. Paging 411 includes fourth plurality of sub-areas 4112, 4114, ..., 411M. The third plurality of sub-regions 4111, 4113, ..., 411N and the fourth plurality of sub-regions 4112, 4114, ..., 411M are interleaved with each other.

The third plurality of sub-regions 4111, 4113, ..., 411N may include a third plurality of data D21', D22', ..., D2N' (eg, normal data). The fourth plurality of sub-regions 4112, 4114, ..., 411M may include a fourth plurality of data D31', D32', ..., D3N' (eg, encoded data). Each of the third set of data D21', D22', ..., D2N' can be associated with a corresponding one of the fourth set of data D31', D32', ..., D3N'. For example, data D21' may be associated with data D31'. Data D31' and data D21' are complementary to each other. The data storage device 100 can obtain the normal data D21, D22, ..., D2N, the encoded data D31, D32, ..., D3N and the normal data D21', D22', . The data pairs of .., D2N' and encoded data D31', D32', ..., D3N' read the correct data.

In addition, there may be more pages in the storage block 41, including two plurality of sub-areas configured to store two plurality of interrelated data.

FIG. 9 is a block diagram illustrating a plurality of pages 410 and 411 of the memory module 1 of the data storage device 100 according to some embodiments of the present disclosure. As shown in Figure 9, page 410 may be configured to store data D41, and page 411 may be configured to store data D42. The address ADD1 of the page 410 (eg, the first area) is different from the address ADD2 of the page 411 (eg, the second area). Data D41 and data D42 can be associated with original D0. Data D41 can be associated with data D42. Data D41 may be encoded as data D42. Data D42 can complement data D41. As shown in FIG. 5 and FIG. 6 , the data storage device 100 can read correct data from the data pair of normal data D41 and encoded data D42.

FIG. 10 is a block diagram illustrating a plurality of pages 410 , 411 , 412 and 414 of the memory module 1 of the data storage device 100 according to some embodiments of the present disclosure. For a detailed description of paging 410 and 411, reference may be made to the embodiment shown in FIG. 9 .

As shown in Figure 10, page 412 can be configured to store data D41', and page 413 can be configured to store data D42'. The address ADD3 of the page 412 (eg, the third area) is different from the address ADD4 of the page 413 (eg, the fourth area). Data D41' and data D42' can be associated with original D0. Data D41' can be associated with data D42'. Data D41' may be encoded as data D42'. Data D42' can be complementary to data D41'. The data storage device 100 can read correct data from the data pair of normal data D41 and encoded data D42 and the data pair of normal data D41' and encoded data D42' through the operations shown in FIGS. 5 and 6 .

FIG. 11 is a flowchart illustrating a control method 200 of a data storage device (eg, data storage device 100 ) according to some embodiments of the present disclosure.

The control method 200 starts from operation S201 and includes storing a first data in a first area of a memory module of a data storage device.

The control method 200 continues with operation S203, including storing a second data in a second area of the memory module. The second data is associated with the first data.

The control method 200 continues to perform operation S205, including reading the first data and the second data through a first communication interface.

The control method 200 continues to perform operation S207, including generating a first output signal in response to the read first data and second data.

The control method 200 continues to perform operation S209, including transmitting the first data through a second communication interface when the first output signal has a first value.

The control method 200 is only an example, and is not intended to limit the content of the present disclosure beyond the scope explicitly mentioned in the patent application. Additional operations may be provided before, during, or after each operation of control method 200, and some of the operations described may be replaced, eliminated, or moved for other embodiments of the method. In some embodiments, control method 200 may include further operations not depicted in FIG. 11 . In some embodiments, control method 200 may include one or more operations described in FIG. 11 .

FIG. 12 is a flowchart illustrating a control method 210 of a data storage device (eg, data storage device 100 ) according to some embodiments of the present disclosure. The control method 210 of FIG. 12 is similar to the control method 200 of FIG. 11 , and the differences therebetween will be described below.

The control method 210 further includes operation S209. Operation S209 includes transmitting the first data through a second communication interface when the first output signal has a first value.

The control method 210 is only an example, and is not intended to limit the content of the present disclosure beyond the scope explicitly mentioned in the patent application. Additional operations may be provided before, during, or after each operation of control method 210, and some of the operations described may be replaced, eliminated, or moved for other embodiments of the method. In some embodiments, control method 210 may include further operations not depicted in FIG. 12 . In some embodiments, control method 210 may include one or more of the operations described in FIG. 12 .

FIG. 13 is a flowchart illustrating a control method 220 of a data storage device (eg, data storage device 100 ) according to some embodiments of the present disclosure. The control method 220 of FIG. 13 is similar to the control method 200 of FIG. 11 , and the differences therebetween will be described below.

The control method 220 further includes operation S204A. The operation includes storing a third data in a third area of the memory module, wherein the third data corresponds to the first data.

The control method 220 continues to perform operation S204B, including storing a fourth data in a fourth area of the memory module. The fourth data is associated with the third data.

The control method 220 further includes operation S210. Operation S210 includes reading the third data and the fourth data through the first communication interface when the first output signal has a second value.

The control method 220 continues to perform operation S211, including generating a second output signal in response to the read third data and fourth data.

The control method 220 continues to perform operation S213, including transmitting the third data through the second communication interface when the second output signal has a third value.

The control method 220 is merely an example, and is not intended to limit the disclosure beyond what is expressly mentioned in the patent application. Additional operations may be provided before, during, or after each operation of control method 220, and some of the operations described may be replaced, eliminated, or moved for other embodiments of the method. In some embodiments, control method 220 may include further operations not depicted in FIG. 13 . In some embodiments, control method 220 may include one or more operations described in FIG. 13 .

FIG. 14 is a flowchart illustrating a control method 230 of a data storage device (eg, data storage device 100 ) according to some embodiments of the present disclosure. The control method 230 of FIG. 14 is similar to the control method 220 of FIG. 13 , and the differences therebetween will be described below.

Instead of operation S213, the control method 230 proceeds to operation S214. When the second output signal has a fourth value, other data stored in other areas is read through the first communication interface. The other data corresponds to the first data and the second data.

The control method 230 is only an example, and is not intended to limit the content of the present disclosure beyond the scope explicitly mentioned in the patent application. Additional operations may be provided before, during, or after each operation of control method 230, and some of the operations described may be replaced, eliminated, or moved for additional embodiments of the method. In some embodiments, control method 230 may include further operations not depicted in FIG. 14 . In some embodiments, control method 230 may include one or more operations described in FIG. 14 .

One aspect of the present disclosure provides a control method for a data storage device, including: storing a first data in a first area of a memory module of the data storage device; and storing a first data in a second area of the memory module. store a second data in, wherein the second data is associated with the first data; read the first data and the second data through the first communication interface; and in response to the read first data and the second data two data to generate a first output signal.

Another aspect of the present disclosure provides a data storage device. The data storage device includes a first area and a second area. The first area is configured to store a first data. The second area is configured to store a second data. The second data is associated with the first data. The first data and/or the second data do not include an error correction code (ECC).

Another aspect of the present disclosure provides a non-transitory computer-readable medium storing a program including instructions that, when executed by a processor, cause a data storage device to: store a first region in a memory. a data; storing a second data in a second area of the memory, wherein the second data is associated with the first data; reading the first data and the second data through a first communication interface; and generating a first output signal in response to the read first data and second data.

The data storage device of the present disclosure includes a memory controller and a memory module. The memory module includes a first area and a second area. The first area and the second area are configured to store a first data and a second data respectively. The first data is associated with the second data to form a data pair. The first data may be normal data, and the second data may be encoded data. The memory controller is configured to read the first data and the second data through a communication interface, and then generate an output signal based on the read first data and second data. Generating the output signal includes performing a logical operation on the first data and the second data. When the output signal has a first value, it indicates that the first data and the second data have no data corruption. When the output signal has a second value, it indicates that one of the first data and the second data has data corruption on its bits. This determination of the value of the output signal can be repeated for other data pairs. The data storage device of the present disclosure can detect whether the data pair is correct without using error correction code (ECC). This is advantageous for memory controllers with passive ECC functionality, that is, enabling the ECC function after receiving data. Such a memory controller can still read the correct data directly from the memory module. The risk of erroneously triggering the memory controller's ECC function with incorrect data can be reduced.

Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the claimed claims. For example, many of the processes described above may be implemented in different ways and may be substituted for many of the processes described above with other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. Those skilled in the art will understand from the disclosure of this disclosure that existing or future developed processes, machines, manufacturing, etc. can be used in accordance with the disclosure to have the same function or achieve substantially the same results as the corresponding embodiments described herein. A material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patentable scope of this application.

1: Memory module 2:Memory controller 3: Buffer memory 4:Storage block group 21: Communication interface 22:Microprocessor 23:Memory 23P:Program 24: Communication interface 41:Storage block 42:Storage block 43:Storage block 44:Storage block 50: Host device 51: Communication interface 52: Host memory 100:Data storage device 200:Control method 210:Control method 220:Control method 230:Control method 410, 411, ..., 431: paging 4101, 4103, ..., 410N: first plural sub-region 4102, 4104, ..., 410N: second complex sub-region 4111, 4113, ..., 410N: The third complex sub-region 4112, 4114, ..., 411M: The fourth complex sub-region 410A:First area 410B:Second area 411A:The third area 411B:The fourth area ADD1: address ADD2:address ADD3:address ADD4: address D0: original data D11: first information D11':Third data D12: Second information D12':Fourth information D21, D22, ..., D2N: the first plural data D31, D32, ..., D3N: second plural data D21', D22', ..., D2N': the third plurality of data D31', D32', ..., D3N': the fourth plural data D41: Information D41':Information D42: Information D42':data OP1: Logical operation OUT1: first output signal OUT2: The second output signal S10: Sequence S11: Sequence S12: Sequence S13: Sequence S14: Sequence S20: Sequence S21: Sequence S22: Sequence S22': sequence S23: Sequence S23':Sequence S24: Sequence S24': sequence S25: Sequence S25': sequence S26: Sequence S26': sequence S27: Sequence S27':Sequence S28: Sequence S28':Sequence S201: Operation S203: Operation S204A: Operation S204B: Operation S205: Operation S207: Operation S209: Operation S210: Operation S211: Operation S213: Operation S214: Operation VA1: first value VA2: second value VA3: third value VA4: fourth value

The disclosure content of this application can be more fully understood by referring to the embodiments and the patent scope combined with the drawings. The same element symbols in the drawings refer to the same elements. FIG. 1 is a block diagram illustrating a data storage device and a host device according to some embodiments of the present disclosure. FIG. 2 is a block diagram illustrating a memory module of a data storage device according to some embodiments of the present disclosure. FIG. 3 is a block diagram illustrating paging of a memory module of a data storage device according to some embodiments of the present disclosure. FIG. 4 is a block diagram illustrating multiple pages of a memory module of a data storage device according to some embodiments of the present disclosure. FIG. 5 is a schematic diagram illustrating the writing sequence in the data storage device and the host device according to some embodiments of the present disclosure. FIG. 6 is a schematic diagram illustrating the reading sequence in the data storage device and the host device according to some embodiments of the present disclosure. FIG. 7 is a block diagram illustrating paging of a memory module of a data storage device according to some embodiments of the present disclosure. FIG. 8 is a block diagram illustrating multiple pages of a memory module of a data storage device according to some embodiments of the present disclosure. FIG. 9 is a block diagram illustrating multiple pages of a memory module of a data storage device according to some embodiments of the present disclosure. FIG. 10 is a block diagram illustrating multiple pages of a memory module of a data storage device according to some embodiments of the present disclosure. FIG. 11 is a flow chart illustrating a control method of a data storage device according to some embodiments of the present disclosure. FIG. 12 is a flow chart illustrating a control method of a data storage device according to some embodiments of the present disclosure. FIG. 13 is a flow chart illustrating a control method of a data storage device according to some embodiments of the present disclosure. FIG. 14 is a flow chart illustrating a control method of a data storage device according to some embodiments of the present disclosure.

1: Memory module 2:Memory controller 3: Buffer memory 4:Storage block group 21: Communication interface 22:Microprocessor 23:Memory 23P:Program 24: Communication interface 41:Storage block 42:Storage block 43:Storage block 44:Storage block 50: Host device 51: Communication interface 52: Host memory 100:Data storage device OP1: Logical operation

Claims (19)

A control method for a data storage device, including: storing a first data in a first area of a memory module of the data storage device; and storing a second data in a second area of the memory module. ; wherein the second data is associated with the first data, and the first data and/or the second data do not include an error correction code (ECC, error correction code); the first data is read through a first communication interface a data and the second data; and in response to the read first data and the second data, a first output signal is generated; wherein when the first output signal has a first value, a second communication is performed The interface transmits the first data. The control method as claimed in claim 1, wherein the first area and the second area are located on the same page of the memory module. The control method according to claim 2, wherein the first area includes a first plurality of sub-areas, and the second area includes a second plurality of sub-areas. The control method as described in claim 3, wherein the first plurality of sub-regions and the second plurality of sub-regions are arranged in a staggered manner. The control method as claimed in claim 1, wherein the first area is in a first part of the memory module On a page, the second area is on a second page of the memory module. The control method as claimed in claim 5, wherein the first page and the second page are adjacent to each other. The control method as claimed in claim 1, wherein the address of the first area is different from the address of the second area. The control method as claimed in claim 1, wherein the second data is the same as the first data. The control method of claim 1, wherein storing the second data in the second area of the memory module includes encoding the first data as the second data. The control method as claimed in claim 9, wherein the second data and the first data are complementary. The control method of claim 1, wherein generating the first output signal includes performing a logical operation based on the first data and the second data. The control method as claimed in claim 11, wherein the logical operation includes at least one of AND, NAND, OR, NOR, NOT, NOT, XOR and XNOR. The control method as described in claim 1, wherein the first data and/or the second data are not controlled by a An ECC function of the memory controller is handled. The control method as claimed in claim 1 further includes: storing a third data in a third area of the memory module, wherein the third data corresponds to the first data; and in the memory module A fourth data is stored in a fourth area of the group, where the fourth data is associated with the third data. The control method of claim 14 further includes: when the first output signal has a second value, reading the third data and the fourth data through the first communication interface. The control method as claimed in claim 15, wherein the first value and the second value are different. The control method as described in claim 15 further includes: generating a second output signal in response to the read third data and fourth data. The control method as claimed in claim 17, further comprising: when the second output signal has a third value, transmitting the third data through the second communication interface; and when the second output signal has a fourth value , reading other data stored in other areas through the first communication interface, where the other data corresponds to the first data and the second data. The control method as described in claim 14, wherein in the fourth area of the memory module Storing the fourth data includes encoding the third data as the fourth data, and the fourth data and the third data are complementary.