TWI825516B - Manufacturing method of semiconductor device - Google Patents

Abstract

A manufacturing method of a semiconductor device includes forming a first photoresist layer over a dielectric structure, and the dielectric structure has an opening. A first portion of the first photoresist layer is removed and a portion of the first photoresist layer remains in the opening. A second photoresist layer is formed over the dielectric structure and the first photoresist layer in the opening. A first trench is formed in the second photoresist layer to expose the first photoresist layer and the portion of the dielectric structure. The portion of the dielectric structure and a second portion of the first photoresist layer are etched by the second photoresist layer to form a second trench. The first photoresist layer is removed, and a conductive structure is formed in the second trench and the opening.

Description

Method of manufacturing semiconductor device

Some embodiments of the present disclosure relate to methods of fabricating semiconductor devices, particularly methods of forming conductive line trenches.

As the integration density in semiconductor devices increases, the integrated circuits in each semiconductor device become more and more complex. Therefore, a good interconnection structure that connects different components in a semiconductor device can improve the performance of the semiconductor device. A dual damascene process may be used to form the interconnect structure. Common dual damascene processes include trench first process and via first process. The difference between the two is that the trench first process forms trenches first and then forms via openings in the trenches. The via-first process forms the via opening first, and then forms a wider and shallower trench in the via opening. Although the technology of the dual damascene process has gradually matured, there are still some difficulties that need to be solved.

According to some embodiments of the present disclosure, a method of manufacturing a semiconductor device includes forming a first photoresist layer on a dielectric structure having an opening in the dielectric structure. The first portion of the first photoresist layer is removed, leaving the first photoresist layer in the opening. A second photoresist layer is formed over the dielectric structure and the first photoresist layer in the opening. A first trench is formed in the second photoresist layer to expose the first photoresist layer and a portion of the dielectric structure. A second trench is formed by etching a portion of the dielectric structure and a second portion of the first photoresist layer through the second photoresist layer. Remove the first photoresist layer. and forming a conductive structure in the second trench and the opening.

According to some embodiments of the present disclosure, the first photoresist layer is a negative photoresist layer.

According to some embodiments of the present disclosure, the second photoresist layer is a negative photoresist layer.

According to some embodiments of the present disclosure, the width of the trench is wider than the width of the mouth.

According to some embodiments of the present disclosure, the dielectric structure includes a first dielectric layer and a second dielectric layer, the second dielectric layer is on the first dielectric layer, and the second trench is formed in the second dielectric layer. middle.

According to some embodiments of the present disclosure, removing the first portion of the first photoresist layer includes exposing a portion of the first photoresist layer directly above the opening, and the first portion of the first photoresist layer is not exposed. The first photoresist layer is developed to remove the unexposed first portion of the first photoresist layer.

According to some embodiments of the present disclosure, the method further includes using a solvent to remove the exposed portion of the first photoresist layer after removing the first portion of the first photoresist layer.

According to some embodiments of the present disclosure, the dielectric structure and the first photoresist layer are etched at substantially the same rate when etching the portion of the dielectric structure and the second portion of the first photoresist layer.

According to some embodiments of the present disclosure, the method further includes removing the second photoresist layer after forming the second trench.

According to some embodiments of the present disclosure, the method further includes etching a bottom portion of the through dielectric structure after removing the first photoresist layer.

Some embodiments of the present disclosure may improve processes for manufacturing conductive wires. Specifically, when etching conductive line trenches, using negative photoresist as a hole-filling material for the trenches can reduce the formation of defects, such as fence defects. Therefore, after the photoresist is subsequently removed and the trenches are filled with conductive structures, the performance of the resulting semiconductor device is improved.

A plurality of implementation manners of the present disclosure will be disclosed below with drawings. For clarity of explanation, many practical details will be explained together in the following description. However, it should be understood that these practical details should not be used to limit the disclosure. That is to say, in some implementations of the present disclosure, these practical details are not necessary. In addition, for the sake of simplifying the drawings, some commonly used structures and components will be illustrated in a simple schematic manner in the drawings.

Some embodiments of the present disclosure use negative photoresist as a hole-filling material for trenches to reduce the formation of defects, such as fence defects. Therefore, after the photoresist is subsequently removed and the trenches are filled with conductive structures, the performance of the resulting semiconductor device is improved.

1 to 9 illustrate cross-sectional views of intermediate stages of a process of manufacturing the semiconductor device 100 in some embodiments of the present disclosure. Specifically, the processes of FIGS. 1 to 9 may be used to form interconnect structures in the semiconductor device 100 . Referring to FIG. 1 , a dielectric structure 110 having an opening 111 is formed on the conductive structure 102 . In some implementations, the conductive structures 102 may be metal lines in an interconnect structure, electronic components in a wafer (eg, transistors, diodes, etc.). The dielectric structure 110 has a stop layer 112, a first dielectric layer 114 and a second dielectric layer 116 stacked from bottom to top. In other words, the first dielectric layer 114 is located on the stop layer 112 and the second dielectric layer 116 is located on the first dielectric layer 114 . Stop layer 112, first dielectric layer 114 and second dielectric layer 116 may be made of any suitable dielectric material. In some embodiments, first dielectric layer 114 is made from a carbon oxide (such as SiCOH), while second dielectric layer 116 is made from an oxide (such as formed from a tetraethoxysilane (TEOS) precursor). oxide), and the stop layer 112 is made of a material with etching selectivity to the first dielectric layer 114, such as nitride (SiN), carbide (SiC) or the like. Specifically, the dielectric structure 110 having the opening 111 may be formed using the following method. First, a photoresist layer is formed on the dielectric structure 110, and then the photoresist layer is exposed and developed to form a patterned photoresist layer. Finally, the patterned photoresist layer is used to etch the first dielectric layer 114 and the second dielectric layer 116. Thus, the dielectric structure 110 with the opening 111 is obtained. In some embodiments, the stop layer 112 serves as a stop layer for etching the first dielectric layer 114 and the second dielectric layer 116 to form the opening 111 , so the opening 111 does not penetrate the stop layer 112 . Stop layer 112 may in turn protect underlying conductive structure 102 from damage during formation of opening 111 . In subsequent processes, the opening 111 will be filled with conductive material to form a through-hole member.

Referring to FIG. 2 , a first photoresist layer 120 is formed on the dielectric structure 110 . The first photoresist layer 120 may be formed using any suitable method, such as spin coating. During the formation of the first photoresist layer 120 , the first photoresist layer 120 fills the opening 111 , as shown in FIG. 2 . In some embodiments, the first photoresist layer 120 may not fill the opening 111 . For example, the first photoresist layer 120 may only partially fill the opening 111 . In some embodiments, the first photoresist layer 120 is a negative photoresist. Negative photoresist can be converted into insoluble substances after being exposed to light. Therefore, after the development process, the exposed soluble substances will remain, while the unexposed parts will dissolve and be removed. In some embodiments, the material of the first photoresist layer 120 is a material suitable for a negative development process, such as an epoxy resin-based material.

Referring to FIG. 3 , a portion of the first photoresist layer 120 is removed, leaving the first photoresist layer 120 in the opening 111 . In some embodiments in which the first photoresist layer 120 is a negative photoresist, the portion of the first photoresist layer 120 directly above the opening 111 in the dielectric structure 110 can be exposed first, so that the exposed portion of the first photoresist layer 120 is not soluble in developer. Next, the first photoresist layer 120 is developed to remove the unexposed portion of the first photoresist layer 120 directly above the second dielectric layer 116 of the dielectric structure 110 , that is, the portion of the first photoresist layer 120 that is not in the opening 111 is removed. Photoresist layer 120. After development, a first photoresist layer 120 protruding from the top surface of the dielectric structure 110 is formed in the opening 111 .

Referring to FIG. 4 , a portion of the first photoresist layer 120 higher than the top surface of the dielectric structure 110 is removed, so that the remaining first photoresist layer 120 is only located in the opening 111 . In some embodiments, the height of the remaining first photoresist layer 120 is slightly lower than the depth of the opening 111 of the dielectric structure 110 . Any method, such as using a solvent, may be used to partially remove the first photoresist layer 120 . In some embodiments, the solvent used to partially remove the first photoresist layer 120 may be an organic solvent, such as propylene glycol methyl ether acetate (PGMEA), propylene glycol methyl ether (PGME), the like, or a combination thereof. In order to correspond to the process described later (eg, FIG. 7 ), the portion of the first photoresist layer 120 removed in FIGS. 3 and 4 can be regarded as the first portion of the first photoresist layer 120 being removed.

Referring to FIG. 5 , a second photoresist layer 130 is formed on the dielectric structure 110 and the first photoresist layer 120 in the opening 111 . The second photoresist layer 130 may be formed using any suitable method, such as spin coating. In some embodiments, the second photoresist layer 130 is a negative photoresist. In some embodiments, the material of the second photoresist layer 130 is a material suitable for a negative development process, such as an epoxy resin-based material.

Referring to FIG. 6 , a portion of the second photoresist layer 130 is removed, and a first trench 132 is formed in the second photoresist layer 130 to expose the first photoresist layer 120 and a portion of the dielectric structure 110 . The width of the first trench 132 in the second photoresist layer 130 is wider than the width of the opening 111 in the dielectric structure 110 . Therefore, the first trench 132 is completely exposed to the first photoresist layer 120 in the opening 111 and is partially exposed to a portion of the dielectric structure 110 . In some embodiments where the second photoresist layer 130 is a negative photoresist, the portion of the second photoresist layer 130 directly above the dielectric structure 110 can be exposed first, that is, the portion of the second photoresist layer 130 that is not in the opening 111 can be exposed. The portion above the first photoresist layer 120 makes the exposed portion of the second photoresist layer 130 insoluble in the developer. Next, the second photoresist layer 130 is developed to remove the unexposed portion of the second photoresist layer 130 on the first photoresist layer 120 in the opening 111 to form the first trench 132 .

Referring to FIG. 7 , a portion of the dielectric structure 110 and the second portion of the first photoresist layer 120 are etched through the patterned second photoresist layer 130 to form a second trench 134 . The dielectric structure 110 and the first photoresist layer 120 may be partially removed through any suitable process. In some embodiments, anisotropic etching, such as dry etching, may be used to partially remove the dielectric structure 110 and the first photoresist layer 120 . The depth of the second trench 134 can be determined according to different situations. In some embodiments, the second trench 134 is formed in the second dielectric layer 116 so that the process in FIG. 7 does not remove the first dielectric layer 114 . Alternatively, the first dielectric layer 114 can be used as an etching stop layer for anisotropic etching, so that the etching of the second trench 134 stops when it reaches the first dielectric layer 114 . The first photoresist layer 120 and the dielectric structure 110 (eg, the second dielectric layer 116 ) have substantially the same resistance to the etching process in FIG. 7 . Therefore, when etching the dielectric structure 110 and the first photoresist layer 120 , etching the dielectric structure 110 and the first photoresist layer 120 at substantially the same rate. Thereby, the bottom surface of the etched second trench 134 is substantially flat, so there is no upward protrusion formed near the junction of the second dielectric layer 116 and the first photoresist layer 120 on the bottom surface of the second trench 134 Fence type defects. When the second trench 134 is filled with conductive structures in subsequent processes, the second trench 134 with a flat bottom can be used to form conductive lines. In some embodiments, the upper surface of the etched first photoresist layer 120 may be concave.

Referring to Figure 8, the remaining first photoresist layer 120 is removed. In some embodiments, the second photoresist layer 130 and the first photoresist layer 120 are removed in the same process. In other embodiments, the second photoresist layer 130 may be removed first and then the first photoresist layer 120 . The first photoresist layer 120 and the second photoresist layer 130 can be removed using any suitable method. In some embodiments, a photoresist ashing process may be used to remove the first photoresist layer 120 and the second photoresist layer 130 . Next, the stop layer 112 under the opening 111 in the dielectric structure 110 is etched through, so that the opening 111 is exposed to the conductive structure 102 under the stop layer 112 .

Referring to FIG. 9 , a conductive structure 140 is formed in the second trench 134 and the opening 111 . Specifically, the conductive structure 140 may include a through-hole member 142 formed in the opening 111 and a conductive line 144 formed in the second trench 134 . The via 142 and the conductive lines 144 may be made of different conductive materials. For example, a first conductive material (such as tungsten) can be filled in the opening 111 to form the through-hole member 142, and then a second conductive material (such as copper) can be filled in the second trench 134 and chemical mechanical polishing (Chemical Mechanical Polishing) can be performed. polishing) to form conductive lines 144. The through-hole component 142 and the conductive wire 144 can also be made of the same conductive material. For example, the through-hole component 142 and the conductive wire 144 are both made of metal (such as copper). Vias 142 may be used to vertically connect conductive lines 144 or conductive structures 102 in different layers. Because the second trench 134 from which the conductive lines 144 are formed has a substantially flat bottom, the resulting conductive lines 144 do not have voids formed when the material is deposited due to defects extending from the trench bottom. In this way, the problem of resistance increase caused by the gaps in the conductive lines can be improved, and the yield of the semiconductor device can be further improved. In some embodiments, before forming the conductive structure 140, a barrier layer may be formed on the sidewalls of the opening 111 and the second trench 134 to prevent the material of the conductive structure 140, such as metal, from diffusing into the dielectric structure. 110, causing the performance of the semiconductor device to be reduced.

After the formation of the semiconductor device 100 is completed, the dielectric structure 110 and the conductive structure 140 can be regarded as a layer of interconnection structures in the semiconductor device 100 . Then, another layer of interconnection structures can be continuously formed on the semiconductor device 100 in the manner of FIGS. 1 to 9 of the present disclosure, and the conductive structures 140 between different layers are connected to each other. In some embodiments, the number of layers of the interconnect structure may range from 1 to 15 layers. In addition, solder balls may also be formed on the conductive structure 140 of the uppermost interconnect structure so that the semiconductor device 100 can be connected to other application devices, such as a circuit board or the like. It should be noted that the elements in each interconnect structure may not be identical. For example, the dielectric structure of the interconnect structure may only include the second dielectric layer 116 but not the first dielectric layer 114, or vice versa.

Embodiments of the present disclosure use a photoresist layer as a hole-filling material to fill openings used to form through-hole members. The etching selectivity of the photoresist layer and the dielectric structure is substantially the same, so that when the trench for forming the conductive line is etched, the bottom of the trench is substantially flat and does not have upwardly protruding fence-type defects. When the filling material is in the trench, a conductive line with fewer gaps can be formed to further improve the resistance of the conductive line and improve the yield of the semiconductor device.

Although the disclosure has been disclosed in the above embodiments, it is not intended to limit the disclosure. Anyone skilled in the art can make various changes and modifications without departing from the spirit and scope of the disclosure. Therefore, the protection of the disclosure The scope shall be determined by the appended patent application scope.

100:Semiconductor device 102:Conductive structure 110:Dielectric structure 111:Open your mouth 112: Stop layer 114: First dielectric layer 116: Second dielectric layer 120: First photoresist layer 130: Second photoresist layer 132:First trench 134:Second trench 140:Conductive structure 142:Through hole parts 144: Conductive thread

1-9 illustrate cross-sectional views of intermediate stages of a process of manufacturing a semiconductor device in some embodiments of the present disclosure.

Domestic storage information (please note in order of storage institution, date and number) without Overseas storage information (please note in order of storage country, institution, date, and number) without

100:Semiconductor device

102:Conductive structure

110:Dielectric structure

112: Stop layer

114: First dielectric layer

116: Second dielectric layer

140:Conductive structure

142:Through hole parts

144: Conductive thread

Claims (10)

A method of manufacturing a semiconductor device, comprising: Forming a first photoresist layer on a dielectric structure, wherein the dielectric structure has an opening; removing a first portion of the first photoresist layer and leaving the first photoresist layer in the opening; forming a second photoresist layer on the dielectric structure and the first photoresist layer in the opening; forming a first trench in the second photoresist layer to expose the first photoresist layer and a portion of the dielectric structure; and Etching the portion of the dielectric structure and a second portion of the first photoresist layer through the second photoresist layer to form a second trench; removing the first photoresist layer; and A conductive structure is formed in the second trench and the opening. The method of claim 1, wherein the first photoresist layer is a negative photoresist layer. The method of claim 1, wherein the second photoresist layer is a negative photoresist layer. The method of claim 1, wherein a width of the trench is wider than a width of the opening. The method of claim 1, wherein the dielectric structure includes a first dielectric layer and a second dielectric layer, the second dielectric layer is on the first dielectric layer, and the second trench formed in the second dielectric layer. The method of claim 1, wherein removing the first portion of the first photoresist layer includes: exposing the portion of the first photoresist layer directly above the opening, and the first portion of the first photoresist layer is not exposed; and The first photoresist layer is developed to remove the unexposed first portion of the first photoresist layer. The method of claim 6, further comprising using a solvent to remove the exposed portion of the first photoresist layer after removing the first portion of the first photoresist layer. The method of claim 1, wherein when etching the portion of the dielectric structure and the second portion of the first photoresist layer, the dielectric structure and the first photoresist layer are etched at substantially the same rate. The method of claim 1 further includes removing the second photoresist layer after forming the trench. The method of claim 1, further comprising etching through a bottom of the dielectric structure after removing the first photoresist layer.

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