TWI822504B - Printed circuit board - Google Patents
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- TWI822504B TWI822504B TW111146649A TW111146649A TWI822504B TW I822504 B TWI822504 B TW I822504B TW 111146649 A TW111146649 A TW 111146649A TW 111146649 A TW111146649 A TW 111146649A TW I822504 B TWI822504 B TW I822504B
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- 230000005540 biological transmission Effects 0.000 claims abstract description 81
- 238000005476 soldering Methods 0.000 claims description 69
- 239000004020 conductor Substances 0.000 claims description 15
- 238000004806 packaging method and process Methods 0.000 claims description 8
- 230000002776 aggregation Effects 0.000 claims 4
- 238000004220 aggregation Methods 0.000 claims 4
- 238000010586 diagram Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000037361 pathway Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 230000001934 delay Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
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Abstract
Description
本發明有關於一種印刷電路板，尤指一種可從兩種不同的封裝晶片擇一焊接其上的印刷電路板。The present invention relates to a printed circuit board, in particular to a printed circuit board on which one of two different package chips can be selectively soldered.
一般而言，業者配合特定晶片元件之腳位定義為印刷電路板之覆晶區域進行的布線設計，使得晶片元件能夠被焊接至印刷電路板之預設位置，從而提供特定之功能。Generally speaking, the industry conducts wiring design in accordance with the pin positions of specific chip components, which are defined as the flip-chip area of the printed circuit board, so that the chip components can be soldered to preset positions on the printed circuit board to provide specific functions.
然而，為了避免缺料發生而導致延宕出貨，一般來說，業者會為了二種以上其工作相同卻腳位定義不同之晶片元件進行備料。However, in order to avoid delays in shipments due to material shortages, manufacturers generally prepare materials for two or more types of chip components that work the same but have different pin definitions.
故，必須因應不同晶片元件而設計二種以上的印刷電路板，才能實現兩種晶片功能，如此，不僅耗費人力物力成本提升，且讓採購物料有所侷限，不能同時採購兩種不同規格之晶片功能。Therefore, more than two types of printed circuit boards must be designed according to different chip components to realize the functions of two chips. This not only increases the cost of manpower and material resources, but also limits the procurement of materials, and cannot purchase two different specifications of chips at the same time. Function.
由此可見，上述技術顯然仍存在不便與缺陷，而有待加以進一步改良。因此，如何能有效地解決上述不便與缺陷，實屬當前重要研發課題之一，亦成爲當前相關領域亟需改進的目標。It can be seen that the above-mentioned technology obviously still has inconveniences and defects, and needs to be further improved. Therefore, how to effectively solve the above inconveniences and defects is indeed one of the current important research and development topics, and it has also become an urgent need for improvement in related fields.
本發明之一目的在於提供一種印刷電路板，用以解決以上先前技術所提到的困難。One object of the present invention is to provide a printed circuit board to solve the above difficulties mentioned in the prior art.
本發明之一實施例提供一種印刷電路板。印刷電路板包含一層疊結構、一傳輸線路圖案及一晶片配置區。傳輸線路圖案分布於層疊結構的外表面。晶片配置區位於層疊結構的外表面。晶片配置區包含一第一環狀區及一第二環狀區。第一環狀區圍繞出一矩形區，內含一第一焊墊聚集圖案。第二環狀區圍繞第一環狀區及矩形區，且受到傳輸線路圖案所圍繞。第二環狀區內含一第二焊墊聚集圖案。第二焊墊聚集圖案電連接第一焊墊聚集圖案與傳輸線路圖案。故，當一封裝晶片只覆蓋第一環狀區與矩形區時，封裝晶片焊接至第一焊墊聚集圖案上，且透過第一焊墊聚集圖案及第二焊墊聚集圖案電連接傳輸線路圖案；當封裝晶片覆蓋第二環狀區、第一環狀區與矩形區時，封裝晶片焊接至第二焊墊聚集圖案上，且透過第二焊墊聚集圖案電連接傳輸線路圖案。An embodiment of the present invention provides a printed circuit board. The printed circuit board includes a stacked structure, a transmission line pattern and a chip configuration area. Transmission line patterns are distributed on the outer surface of the laminated structure. The chip configuration area is located on the outer surface of the stacked structure. The chip configuration area includes a first annular area and a second annular area. The first annular area surrounds a rectangular area containing a first bonding pad gathering pattern. The second annular area surrounds the first annular area and the rectangular area, and is surrounded by the transmission line pattern. The second annular area contains a second bonding pad gathering pattern. The second bonding pad gathering pattern is electrically connected to the first bonding pad gathering pattern and the transmission line pattern. Therefore, when a package chip only covers the first annular area and the rectangular area, the package chip is soldered to the first pad gathering pattern, and is electrically connected to the transmission line pattern through the first pad gathering pattern and the second pad gathering pattern. ; When the packaging chip covers the second annular area, the first annular area and the rectangular area, the packaging chip is welded to the second bonding pad gathering pattern, and is electrically connected to the transmission line pattern through the second bonding pad gathering pattern.
依據本發明一或複數個實施例，在上述之印刷電路板中，第一焊墊聚集圖案包含二第一橫向柱狀區及二第一縱向柱狀區。這些第一橫向柱狀區沿一第一軸向延伸，且彼此平行排列。此些第一縱向柱狀區沿一正交第一軸向之第二軸向延伸，且彼此平行排列。這些第一縱向柱狀區與這些第一橫向柱狀區共同圍繞矩形區。各個第一橫向柱狀區包含多個第一直焊墊。這些第一直焊墊依據1*M的陣列方式排列。各個第一縱向柱狀區包含多個第一橫焊墊，這些第一橫焊墊依據M*1的陣列方式排列，其中M為正整數。According to one or more embodiments of the present invention, in the above-mentioned printed circuit board, the first pad collection pattern includes two first lateral columnar areas and two first longitudinal columnar areas. These first transverse columnar regions extend along a first axis and are arranged parallel to each other. The first longitudinal columnar areas extend along a second axis orthogonal to the first axis and are arranged parallel to each other. These first longitudinal columnar areas and these first transverse columnar areas together surround the rectangular area. Each first lateral columnar region includes a plurality of first direct bonding pads. These first direct bonding pads are arranged in a 1*M array. Each first longitudinal columnar area includes a plurality of first horizontal bonding pads, and these first horizontal bonding pads are arranged in an M*1 array, where M is a positive integer.
依據本發明一或複數個實施例，在上述之印刷電路板中，第二焊墊聚集圖案包含二第二橫向柱狀區及二第二縱向柱狀區。這些第二橫向柱狀區沿第一軸向延伸，且彼此平行排列，各個第一橫向柱狀區位於其中一第二橫向柱狀區與矩形區之間，且與此第二橫向柱狀區保持間隙。此些第二縱向柱狀區沿第二軸向延伸，且彼此平行排列。各個第一縱向柱狀區位於其中一第二縱向柱狀區與矩形區之間，與第二縱向柱狀區保持間隙。這些第二縱向柱狀區與這些第二橫向柱狀區共同圍繞第一環狀區與矩形區。各個第二橫向柱狀區包含多個第二直焊墊，這些第二直焊墊依據1*N的陣列方式排列，各個第二縱向柱狀區包含多個第二橫焊墊，這些第二橫焊墊依據N*1的陣列方式排列，其中N為正整數。According to one or more embodiments of the present invention, in the above-mentioned printed circuit board, the second bonding pad gathering pattern includes two second lateral columnar areas and two second longitudinal columnar areas. These second transverse columnar regions extend along the first axis and are arranged parallel to each other. Each first transverse columnar region is located between one of the second transverse columnar regions and the rectangular region, and with the second transverse columnar region. Keep gaps. These second longitudinal columnar regions extend along the second axial direction and are arranged parallel to each other. Each first longitudinal columnar region is located between one of the second longitudinal columnar regions and the rectangular region, maintaining a gap with the second longitudinal columnar region. These second longitudinal columnar areas and these second transverse columnar areas together surround the first annular area and the rectangular area. Each second lateral columnar area includes a plurality of second straight soldering pads, and these second straight soldering pads are arranged in a 1*N array. Each second longitudinal columnar area includes a plurality of second horizontal soldering pads. These second straight soldering pads are arranged in a 1*N array. The horizontal pads are arranged in an N*1 array, where N is a positive integer.
依據本發明一或複數個實施例，在上述之印刷電路板中，各個第一直焊墊之長軸方向與各個第一橫焊墊之長軸方向彼此正交，且平行各個第二直焊墊之長軸方向。各個第二直焊墊之長軸方向與各個第二橫焊墊之長軸方向彼此正交。According to one or more embodiments of the present invention, in the above-mentioned printed circuit board, the long axis direction of each first direct soldering pad and the long axis direction of each first horizontal soldering pad are orthogonal to each other and parallel to each second direct soldering pad. The direction of the long axis of the pad. The long axis direction of each second straight bonding pad and the long axis direction of each second horizontal bonding pad are orthogonal to each other.
依據本發明一或複數個實施例，在上述之印刷電路板中，這些第一直焊墊及這些第一橫焊墊之總數量等於這些第二直焊墊及這些第二橫焊墊之總數量。According to one or more embodiments of the present invention, in the above-mentioned printed circuit board, the total number of the first straight soldering pads and the first horizontal soldering pads is equal to the total number of the second straight soldering pads and the second horizontal soldering pads. quantity.
依據本發明一或複數個實施例，在上述之印刷電路板中，這些第一直焊墊之一部分一一對應這些第二直焊墊之一部分，這些第一橫焊墊之一部分分別一一對應這些第二橫焊墊之一部分。According to one or more embodiments of the present invention, in the above-mentioned printed circuit board, a part of the first straight soldering pads corresponds to a part of the second straight soldering pads, and a part of the first horizontal soldering pads corresponds to a one-to-one correspondence. part of these second lateral solder pads.
依據本發明一或複數個實施例，在上述之印刷電路板中，各個第一直焊墊之長度大於其中一第二直焊墊的長度，且此第一直焊墊之寬度小於第二直焊墊之寬度。各個第一橫焊墊之長度大於其中一第二橫焊墊的長度，且此第一橫焊墊之寬度小於第二橫焊墊之寬度。According to one or more embodiments of the present invention, in the above-mentioned printed circuit board, the length of each first straight soldering pad is greater than the length of one of the second straight soldering pads, and the width of the first straight soldering pad is smaller than the second straight soldering pad. The width of the soldering pad. The length of each first horizontal bonding pad is greater than the length of one of the second horizontal bonding pads, and the width of the first horizontal bonding pad is smaller than the width of the second horizontal bonding pad.
依據本發明一或複數個實施例，在上述之印刷電路板中，這些第一直焊墊之一部份分別透過位於層疊結構的外表面上之印刷線路直接連接這些第二直焊墊之一部份，這些第一橫焊墊之一部份分別透過位於層疊結構的外表面上之另一印刷線路直接連接這些第二橫焊墊之一部份。According to one or more embodiments of the present invention, in the above-mentioned printed circuit board, a part of the first direct soldering pads is directly connected to one of the second direct soldering pads through a printed circuit located on the outer surface of the laminated structure. In part, a part of the first horizontal bonding pads is directly connected to a part of the second horizontal bonding pads through another printed circuit located on the outer surface of the laminated structure.
依據本發明一或複數個實施例，在上述之印刷電路板中，這些第一直焊墊之一部份分別透過一位於層疊結構內之立體途徑連接傳輸線路圖案與這些第二直焊墊之一部份。這些第一橫焊墊之一部份分別透過另一位於層疊結構內之立體途徑連接傳輸線路圖案與這些第二橫焊墊之一部份。According to one or more embodiments of the present invention, in the above-mentioned printed circuit board, part of the first direct soldering pads are respectively connected to the transmission line pattern and the second direct soldering pads through a three-dimensional path located in the stacked structure. a part. A part of the first horizontal bonding pads is connected to a transmission line pattern and a part of the second horizontal bonding pads through another three-dimensional path located in the stacked structure.
依據本發明一或複數個實施例，在上述之印刷電路板中，其中一立體途徑包含至少一第一導孔、至少一第二導孔及至少一層內導線。第一導孔位處矩形區內，且電連接第一焊墊聚集圖案。第二導孔位處晶片配置區之外，且電連接傳輸線路圖案及第二焊墊聚集圖案。層內導線位於該層疊結構內部，且電連接第一導孔與第二導孔。封裝晶片透過第一焊墊聚集圖案、第一導孔、層內導線及第二導孔電連接第二焊墊聚集圖案及傳輸線路圖案。According to one or more embodiments of the present invention, in the above-mentioned printed circuit board, one of the three-dimensional paths includes at least one first via hole, at least one second via hole and at least one layer of inner conductors. The first via hole is located in the rectangular area and is electrically connected to the first pad assembly pattern. The second via hole is located outside the chip configuration area and is electrically connected to the transmission line pattern and the second pad assembly pattern. The intra-layer conductor is located inside the stacked structure and electrically connects the first conductive hole and the second conductive hole. The package chip is electrically connected to the second bonding pad gathering pattern and the transmission line pattern through the first bonding pad gathering pattern, the first via hole, the intra-layer conductor and the second via hole.
依據本發明一或複數個實施例，在上述之印刷電路板中，第一焊墊聚集圖案包含至少一第一訊號用焊墊。第二焊墊聚集圖案包含至少一第二訊號用焊墊。第二訊號用焊墊透過一位於層疊結構的外表面上之印刷線路連接第一訊號用焊墊。According to one or more embodiments of the present invention, in the above-mentioned printed circuit board, the first pad collection pattern includes at least one first signal pad. The second bonding pad gathering pattern includes at least one second signal bonding pad. The second signal pad is connected to the first signal pad through a printed circuit located on the outer surface of the laminated structure.
依據本發明一或複數個實施例，在上述之印刷電路板中，第一焊墊聚集圖案更包含至少一第一電源用焊墊，第一電源用焊墊透過位於層疊結構內部的立體途徑連接傳輸線路圖案。第二焊墊聚集圖案更包含至少一第二電源用焊墊，第二電源用焊墊透過位於層疊結構內部的另一立體途徑連接傳輸線路圖案。According to one or more embodiments of the present invention, in the above-mentioned printed circuit board, the first pad assembly pattern further includes at least one first power pad, and the first power pad is connected through a three-dimensional path located inside the stacked structure. Transmission line pattern. The second bonding pad gathering pattern further includes at least one second power supply bonding pad, and the second power supply bonding pad is connected to the transmission line pattern through another three-dimensional path located inside the stacked structure.
依據本發明一或複數個實施例，在上述之印刷電路板中，晶片配置區包含一第一跨接電阻與一第二跨接電阻，第一跨接電阻電連接第一訊號用焊墊與傳輸線路圖案。第二跨接電阻電連接第二訊號用焊墊與傳輸線路圖案，當封裝晶片焊接至第一焊墊聚集圖案時，第一跨接電阻使第一訊號用焊墊導通傳輸線路圖案。當封裝晶片焊接至第二焊墊聚集圖案時，第二跨接電阻使第二訊號用焊墊導通傳輸線路圖案。According to one or more embodiments of the present invention, in the above-mentioned printed circuit board, the chip configuration area includes a first jumper resistor and a second jumper resistor, and the first jumper resistor is electrically connected to the first signal pad and Transmission line pattern. The second jumper resistor is electrically connected to the second signal pad and the transmission line pattern. When the package chip is soldered to the first bonding pad assembly pattern, the first jumper resistor causes the first signal pad to conduct to the transmission line pattern. When the package chip is soldered to the second pad assembly pattern, the second jumper resistor enables the second signal pad to conduct the transmission line pattern.
如此，透過以上架構，本揭露能夠滿足在同一個電路板能應用於多種封裝模式之積體電路，亦即能夠使用(採購)兩種不同封裝的晶片。此外，本案還可以進行模組化核心電路，將同一區塊的積體線路能夠複製到另一個電路板設計之應用，能夠達成兩種不同封裝晶片的功能，如此一來能將此技術套用在任何電路板設計。In this way, through the above structure, the present disclosure can satisfy the requirement that the same circuit board can be applied to integrated circuits of multiple packaging modes, that is, two different packaged chips can be used (purchased). In addition, this case can also modularize the core circuit, and the integrated circuits of the same block can be copied to another circuit board design application, which can achieve the functions of two different packaging chips. In this way, this technology can be applied to Any circuit board design.
以上所述僅係用以闡述本發明所欲解決的問題、解決問題的技術手段、及其產生的功效等等，本發明之具體細節將在下文的實施方式及相關圖式中詳細介紹。The above is only used to describe the problems to be solved by the present invention, the technical means to solve the problems, the effects thereof, etc. The specific details of the present invention will be introduced in detail in the following embodiments and related drawings.
以下將以圖式揭露本發明之複數個實施例，為明確說明起見，許多實務上的細節將在以下敘述中一併說明。然而，應瞭解到，這些實務上的細節不應用以限制本發明。也就是說，在本發明各實施例中，這些實務上的細節是非必要的。此外，為簡化圖式起見，習知慣用的眾結構與元件在圖式中將以簡單示意的方式繪示之。The following will disclose multiple embodiments of the present invention in the drawings. For the sake of clarity, many practical details will be explained in the following description. However, it will be understood that these practical details should not limit the invention. That is to say, in various embodiments of the present invention, these practical details are not necessary. In addition, for the sake of simplifying the drawings, commonly used structures and components are shown in a simple schematic manner in the drawings.
第1圖為本發明一實施例之印刷電路板10的上視圖。第2圖為第1圖之區域P的放大圖。第3圖為第2圖之印刷電路板10的局部剖視圖。如第1圖至第3圖所示，在本實施例中，一種印刷電路板10包含一層疊結構100、一傳輸線路圖案200及一晶片配置區300。傳輸線路圖案200與晶片配置區300位於層疊結構100的外表面120(即絕緣表面)，且傳輸線路圖案200包圍晶片配置區300。更具體地，層疊結構100包含多個板體110。這些板體110沿一縱向V彼此層疊。任一板體110的配置表面為絕緣材質，傳輸線路圖案200與晶片配置區300皆位於這些板體110之最外側者表面(即絕緣表面)，且沿一橫向H延伸。Figure 1 is a top view of a printed circuit board 10 according to an embodiment of the present invention. Figure 2 is an enlarged view of area P in Figure 1. Figure 3 is a partial cross-sectional view of the printed circuit board 10 of Figure 2 . As shown in FIGS. 1 to 3 , in this embodiment, a printed circuit board 10 includes a stacked structure 100 , a transmission line pattern 200 and a chip configuration area 300 . The transmission line pattern 200 and the chip configuration area 300 are located on the outer surface 120 (ie, the insulating surface) of the stacked structure 100, and the transmission line pattern 200 surrounds the chip configuration area 300. More specifically, the laminated structure 100 includes a plurality of plates 110 . These plates 110 are stacked on each other along a longitudinal direction V. The configuration surface of any board 110 is made of insulating material. The transmission line pattern 200 and the chip configuration area 300 are located on the outermost surface (ie, the insulating surface) of these boards 110 and extend along a horizontal direction H.
晶片配置區300包含一第一環狀區320及一第二環狀區330。第一環狀區320呈方環狀或呈回字形，且第一環狀區320圍繞(甚至完全圍繞)出一矩形區310。第二環狀區330呈方環狀或呈回字形，且第二環狀區330圍繞(甚至完全圍繞)第一環狀區320及矩形區310，且受到傳輸線路圖案200所圍繞(甚至完全圍繞)。傳輸線路圖案200連接至晶片配置區300之第二焊墊聚集圖案500。須了解到，傳輸線路圖案200泛指層疊結構100上除了晶片配置區300以外的傳輸線路之總稱，其能夠傳遞訊號進出晶片配置區300上之封裝晶片。The chip placement area 300 includes a first annular area 320 and a second annular area 330 . The first annular area 320 is in a square annular shape or a zigzag shape, and the first annular area 320 surrounds (or even completely surrounds) a rectangular area 310 . The second annular area 330 is square annular or zigzag-shaped, and the second annular area 330 surrounds (even completely surrounds) the first annular area 320 and the rectangular area 310 , and is surrounded (even completely) by the transmission line pattern 200 around). The transmission line pattern 200 is connected to the second pad gathering pattern 500 of the chip placement area 300 . It should be understood that the transmission line pattern 200 generally refers to the general name of the transmission lines on the stacked structure 100 except the chip configuration area 300, which can transmit signals in and out of the package chips on the chip configuration area 300.
第一環狀區320之範圍內配置有一第一焊墊聚集圖案400，且第一焊墊聚集圖案400只位於第一環狀區320內，且圍繞(甚至完全圍繞)矩形區310。第二環狀區330之範圍內配置有一第二焊墊聚集圖案500，且第二焊墊聚集圖案500只位於第二環狀區330內，圍繞(甚至完全圍繞)第一焊墊聚集圖案400，且與第一焊墊聚集圖案400之間保持分離。第一焊墊聚集圖案400位於第二焊墊聚集圖案500與矩形區310之間，且電連接第二焊墊聚集圖案500。第二焊墊聚集圖案500位於第一焊墊聚集圖案400與傳輸線路圖案200之間，且電連接第一焊墊聚集圖案400與傳輸線路圖案200。A first pad gathering pattern 400 is disposed within the first annular area 320 , and the first pad gathering pattern 400 is only located within the first annular area 320 and surrounds (even completely surrounds) the rectangular area 310 . A second pad gathering pattern 500 is disposed within the second annular area 330 , and the second pad gathering pattern 500 is only located within the second annular area 330 , surrounding (or even completely surrounding) the first pad gathering pattern 400 , and remain separated from the first bonding pad gathering pattern 400 . The first pad gathering pattern 400 is located between the second pad gathering pattern 500 and the rectangular area 310 and is electrically connected to the second pad gathering pattern 500 . The second pad gathering pattern 500 is located between the first pad gathering pattern 400 and the transmission line pattern 200, and is electrically connected to the first pad gathering pattern 400 and the transmission line pattern 200.
故，當操作人員選擇以一第一封裝晶片覆蓋至第一環狀區320與矩形區310，且讓第一封裝晶片之腳位分別焊接至第一焊墊聚集圖案400時，第一封裝晶片之腳位能夠透過第一焊墊聚集圖案400、第二焊墊聚集圖案500電連接傳輸線路圖案200，使得第一封裝晶片能夠透過傳輸線路圖案200與印刷電路板10外之電子元件交換訊號。Therefore, when the operator chooses to cover the first annular area 320 and the rectangular area 310 with a first package chip, and allows the pins of the first package chip to be soldered to the first pad gathering pattern 400 respectively, the first package chip The pins can be electrically connected to the transmission line pattern 200 through the first pad assembly pattern 400 and the second pad assembly pattern 500, so that the first package chip can exchange signals with electronic components outside the printed circuit board 10 through the transmission line pattern 200.
反之，當操作人員改以一大於第一封裝晶片之第二封裝晶片覆蓋第二環狀區330、第一環狀區320與矩形區310，且讓第二封裝晶片之腳位分別焊接至第二焊墊聚集圖案500時，第二封裝晶片之腳位能夠透過第二焊墊聚集圖案500電連接傳輸線路圖案200，使得第二封裝晶片能夠透過傳輸線路圖案200與印刷電路板10外之電子元件交換訊號。On the contrary, when the operator uses a second package chip that is larger than the first package chip to cover the second annular area 330, the first annular area 320 and the rectangular area 310, and the pins of the second package chip are soldered to the first package chip respectively. When the two pad assembly patterns 500 are formed, the pins of the second package chip can be electrically connected to the transmission line pattern 200 through the second pad assembly pattern 500, so that the second package chip can communicate with electronics outside the printed circuit board 10 through the transmission line pattern 200. Component exchange signals.
須了解到，由於第一封裝晶片呈矩形(如正方形)，第一封裝晶片之面積大致等於第一環狀區320與矩形區310之總面積，故，第一封裝晶片之面積僅能夠覆蓋第一環狀區320與矩形區310，無法覆蓋至第二環狀區330之區域。同理，由於第二封裝晶片呈矩形(如正方形)，第二封裝晶片之面積大致等於第一環狀區320、第二環狀區330與矩形區310之總面積，故，第二封裝晶片之面積能夠覆蓋第一環狀區320、第二環狀區330與矩形區310。It should be understood that since the first package chip is rectangular (such as a square), the area of the first package chip is approximately equal to the total area of the first annular area 320 and the rectangular area 310. Therefore, the area of the first package chip can only cover the first annular area 320 and the rectangular area 310. An annular area 320 and a rectangular area 310 cannot cover the area of the second annular area 330. Similarly, since the second package chip is rectangular (such as square), the area of the second package chip is approximately equal to the total area of the first annular area 320, the second annular area 330 and the rectangular area 310. Therefore, the second package chip The area can cover the first annular area 320, the second annular area 330 and the rectangular area 310.
在本實施例中，更具體地，第一焊墊聚集圖案400包含二第一橫向柱狀區410及二第一縱向柱狀區420。這些第一橫向柱狀區410沿一第一軸向D1延伸，且彼此平行排列。此些第一縱向柱狀區420沿一正交第一軸向D1之第二軸向D2延伸，且彼此平行排列。這些第一縱向柱狀區420與這些第一橫向柱狀區410共同圍繞出上述之矩形區310。In this embodiment, more specifically, the first bonding pad gathering pattern 400 includes two first lateral columnar regions 410 and two first longitudinal columnar regions 420 . These first transverse columnar regions 410 extend along a first axis D1 and are arranged parallel to each other. The first longitudinal columnar areas 420 extend along a second axis D2 that is orthogonal to the first axis D1 and are arranged parallel to each other. The first longitudinal columnar areas 420 and the first transverse columnar areas 410 together surround the above-mentioned rectangular area 310.
各個第一橫向柱狀區410包含多個第一直焊墊411。這些第一直焊墊411依據1*M的陣列方式排列(M為正整數)，換句話說，這些第一直焊墊411沿著第一軸向D1且依據一個接著一個之排列方式等距地依序排列。各個第一縱向柱狀區420包含多個第一橫焊墊421，這些第一橫焊墊421依據M*1的陣列方式排列(M為正整數)，換句話說，這些第一橫焊墊421 沿著第二軸向D2且依據一個接著一個之排列方式等距地依序排列。每個第一直焊墊411之長軸方向與每個第一橫焊墊421之長軸方向彼此正交，且平行每個第二直焊墊511之長軸方向。此些第一橫向柱狀區410之第一直焊墊411之數量彼此相同，且此些第一縱向柱狀區420之第一橫焊墊421之數量彼此相同。Each first lateral columnar region 410 includes a plurality of first direct bonding pads 411 . These first direct bonding pads 411 are arranged in an array of 1*M (M is a positive integer). In other words, these first direct bonding pads 411 are equidistant along the first axis D1 and arranged one after another. Places are arranged in order. Each first longitudinal columnar area 420 includes a plurality of first horizontal bonding pads 421. These first horizontal bonding pads 421 are arranged in an M*1 array (M is a positive integer). In other words, these first horizontal bonding pads 421 are arranged in sequence equidistantly along the second axis D2 and arranged one after another. The long axis direction of each first straight bonding pad 411 and the long axis direction of each first horizontal bonding pad 421 are orthogonal to each other and parallel to the long axis direction of each second straight bonding pad 511 . The number of the first direct bonding pads 411 of the first transverse columnar regions 410 is the same as each other, and the number of the first horizontal bonding pads 421 of the first longitudinal columnar regions 420 is the same as each other.
第二焊墊聚集圖案500包含二第二橫向柱狀區510及二第二縱向柱狀區520。這些第二橫向柱狀區510沿第一軸向D1延伸，且彼此平行排列，各個第一橫向柱狀區410位於相鄰的第二橫向柱狀區510與矩形區310之間，且與此第二橫向柱狀區510保持間隙。此些第二縱向柱狀區520沿第二軸向D2延伸，且彼此平行排列。各個第一縱向柱狀區420位於相鄰的第二縱向柱狀區520與矩形區310之間，與第二縱向柱狀區520保持間隙。這些第二縱向柱狀區520與這些第二橫向柱狀區510共同圍繞出上述第一環狀區320與矩形區310。各個第二橫向柱狀區510包含多個第二直焊墊511，這些第二直焊墊511依據1*N的陣列方式(N為正整數)排列，換句話說，這些第二直焊墊511沿著第一軸向D1且依據一個接著一個之排列方式等距地依序排列。各個第二縱向柱狀區520包含多個第二橫焊墊521，這些第二橫焊墊521依據N*1的陣列方式(N為正整數)排列，換句話說，這些第二橫焊墊521沿著第二軸向D2依據一個接著一個之排列方式等距地依序排列。每個第二橫焊墊521之長軸方向與每個第二直焊墊511之長軸方向彼此正交，且平行每個第一橫焊墊421之長軸方向。此些第二橫向柱狀區510之第二直焊墊511之數量彼此相同，且此些第二縱向柱狀區520之第二橫焊墊521之數量彼此相同。故，這些第一直焊墊411及這些第一橫焊墊421之總數量等於這些第二直焊墊511及這些第二橫焊墊521之總數量。The second bonding pad gathering pattern 500 includes two second lateral columnar regions 510 and two second longitudinal columnar regions 520 . These second transverse columnar regions 510 extend along the first axial direction D1 and are arranged parallel to each other. Each first transverse columnar region 410 is located between the adjacent second transverse columnar region 510 and the rectangular region 310, and with this The second lateral columnar region 510 maintains the gap. These second longitudinal columnar regions 520 extend along the second axis D2 and are arranged parallel to each other. Each first longitudinal columnar region 420 is located between the adjacent second longitudinal columnar region 520 and the rectangular region 310 , maintaining a gap with the second longitudinal columnar region 520 . The second longitudinal columnar regions 520 and the second transverse columnar regions 510 together surround the first annular region 320 and the rectangular region 310 . Each second lateral columnar area 510 includes a plurality of second straight bonding pads 511, which are arranged in a 1*N array (N is a positive integer). In other words, these second straight bonding pads 511 are arranged in a 1*N array (N is a positive integer). 511 are arranged in sequence equidistantly along the first axis D1 and arranged one after another. Each second longitudinal columnar area 520 includes a plurality of second horizontal bonding pads 521. These second horizontal bonding pads 521 are arranged in an N*1 array (N is a positive integer). In other words, these second horizontal bonding pads 521 are arranged equidistantly in sequence along the second axis D2 in a one-to-one arrangement. The long axis direction of each second horizontal bonding pad 521 and the long axis direction of each second straight bonding pad 511 are orthogonal to each other and parallel to the long axis direction of each first horizontal bonding pad 421 . The number of the second straight bonding pads 511 of the second transverse columnar regions 510 is the same as each other, and the number of the second horizontal bonding pads 521 of the second longitudinal columnar regions 520 is the same as each other. Therefore, the total number of the first straight bonding pads 411 and the first horizontal bonding pads 421 is equal to the total number of the second straight bonding pads 511 and the second horizontal bonding pads 521 .
每個第一橫向柱狀區410之其中數個第一直焊墊411分別一一對應相鄰之第二橫向柱狀區510之其中數個第二直焊墊511，意即，上述數個第一直焊墊411是以一對一的方式分別對應上述數個第二直焊墊511。更進一步地，所述數個第一直焊墊411分別透過位於層疊結構100的外表面120上之第一印刷線路610直接連接所述數個第二直焊墊511；及/或者，所述數個第一直焊墊411分別透過一位於層疊結構100內之第一立體途徑700連接傳輸線路圖案200與所述數個第二直焊墊511。The plurality of first direct soldering pads 411 in each first lateral columnar region 410 respectively correspond to the plurality of second direct soldering pads 511 in the adjacent second lateral columnar region 510. That is to say, the above-mentioned several The first direct bonding pads 411 respectively correspond to the above-mentioned plurality of second direct bonding pads 511 in a one-to-one manner. Furthermore, the first direct soldering pads 411 are directly connected to the second direct soldering pads 511 through the first printed circuits 610 located on the outer surface 120 of the laminated structure 100; and/or, the The plurality of first direct bonding pads 411 are respectively connected to the transmission line pattern 200 and the plurality of second direct bonding pads 511 through a first three-dimensional path 700 located in the stacked structure 100 .
舉例來說，第一立體途徑700包含多個第一導孔710、多個第二導孔720及一或多個第一層內導線730。這些第一導孔710位處於矩形區310內，且各別電連接第一焊墊聚集圖案400之其中一第一直焊墊411。這些第二導孔720位處晶片配置區300之外，且分別電連接傳輸線路圖案200及第二焊墊聚集圖案500。每個第一層內導線730位於層疊結構100之內部(如板體110之間的配置表面上)且電連接第一導孔710與第二導孔720。如此，當第一封裝晶片被選擇安裝至第一環狀區320時，第一封裝晶片之眾腳位分別透過第一焊墊聚集圖案400、這些第一導孔710、第一層內導線730及第二導孔720電連接第二焊墊聚集圖案500及傳輸線路圖案200。For example, the first three-dimensional via 700 includes a plurality of first vias 710 , a plurality of second vias 720 and one or more first-layer inner conductors 730 . These first via holes 710 are located in the rectangular area 310 and are each electrically connected to one of the first direct bonding pads 411 of the first bonding pad assembly pattern 400 . These second via holes 720 are located outside the chip placement area 300 and are electrically connected to the transmission line pattern 200 and the second bonding pad gathering pattern 500 respectively. Each first-layer inner conductor 730 is located inside the stacked structure 100 (such as on the arrangement surface between the boards 110 ) and electrically connects the first conductive hole 710 and the second conductive hole 720 . In this way, when the first package chip is selectively mounted to the first annular area 320, the pins of the first package chip pass through the first pad assembly pattern 400, the first via holes 710, and the first layer inner conductors 730 respectively. And the second via hole 720 is electrically connected to the second pad assembly pattern 500 and the transmission line pattern 200 .
在一實施例中，第一印刷線路610之寬度遠小於第一直焊墊411及第二直焊墊511各自的寬度。第一立體途徑700之範圍跨越傳輸線路圖案200及晶片配置區300。In one embodiment, the width of the first printed circuit 610 is much smaller than the respective widths of the first direct bonding pad 411 and the second direct bonding pad 511 . The scope of the first three-dimensional path 700 spans the transmission line pattern 200 and the chip configuration area 300 .
每個第一縱向柱狀區420之其中數個第一橫焊墊421分別一一對應相鄰之第二縱向柱狀區520之其中數個第二橫焊墊521，意即，上述數個第一橫焊墊421是以一對一的方式分別對應上述數個第二橫焊墊521。更進一步地，所述數個第一橫焊墊421分別透過位於層疊結構100的外表面120上之第二印刷線路620直接連接所述數個第二橫焊墊521；及/或者，所述數個第一橫焊墊421分別透過一位於層疊結構100內之第二立體途徑800連接傳輸線路圖案200與所述數個第二橫焊墊521。The plurality of first horizontal bonding pads 421 in each first longitudinal columnar region 420 respectively correspond to the plurality of second horizontal bonding pads 521 in the adjacent second longitudinal columnar region 520. That is to say, the above-mentioned several The first horizontal bonding pads 421 respectively correspond to the above-mentioned plurality of second horizontal bonding pads 521 in a one-to-one manner. Furthermore, the plurality of first horizontal bonding pads 421 are directly connected to the plurality of second horizontal bonding pads 521 through the second printed circuits 620 located on the outer surface 120 of the laminated structure 100; and/or, the The plurality of first horizontal bonding pads 421 are respectively connected to the transmission line pattern 200 and the plurality of second horizontal bonding pads 521 through a second three-dimensional path 800 located in the stacked structure 100 .
舉例來說，第二立體途徑800包含多個第三導孔810、多個第四導孔820及一或多個第二層內導線830。這些第三導孔810位處矩形區310內，且各別電連接第一焊墊聚集圖案400。這些第四導孔820位處晶片配置區300之外，且分別電連接傳輸線路圖案200及第二焊墊聚集圖案500。每個第二層內導線830位於層疊結構100之內部(如板體110之間的配置表面上)，且電連接第三導孔810與第四導孔820。如此，當第二封裝晶片被選擇安裝至第二環狀區330時，第二封裝晶片之眾腳位分別透過第一焊墊聚集圖案400、第三導孔810、第二層內導線830及第四導孔820電連接傳輸線路圖案200。For example, the second three-dimensional via 800 includes a plurality of third vias 810 , a plurality of fourth vias 820 and one or more second-layer inner conductors 830 . These third via holes 810 are located in the rectangular area 310 and are electrically connected to the first pad gathering pattern 400 respectively. These fourth via holes 820 are located outside the chip configuration area 300 and are electrically connected to the transmission line pattern 200 and the second bonding pad gathering pattern 500 respectively. Each second-layer inner conductor 830 is located inside the stacked structure 100 (such as on the arrangement surface between the boards 110 ), and is electrically connected to the third conductive hole 810 and the fourth conductive hole 820 . In this way, when the second package chip is selectively mounted to the second annular area 330, the pins of the second package chip pass through the first pad assembly pattern 400, the third via hole 810, the second layer inner conductor 830 and The fourth via hole 820 is electrically connected to the transmission line pattern 200 .
在一實施例中，第二印刷線路620之寬度遠小於第一橫焊墊421及第二橫焊墊521各自的寬度。第二立體途徑800之範圍跨越傳輸線路圖案200及晶片配置區300。In one embodiment, the width of the second printed circuit 620 is much smaller than the respective widths of the first lateral bonding pad 421 and the second lateral bonding pad 521 . The range of the second three-dimensional path 800 spans the transmission line pattern 200 and the chip configuration area 300 .
更具體地，其中一例子中，各個第一直焊墊411之長度L1大於其中一第二直焊墊511的長度L2，且各個第一直焊墊411之寬度W1小於第二直焊墊511之寬度W2。各個第一橫焊墊421之長度L3大於其中一第二橫焊墊521的長度L4，且各個第一橫焊墊421之寬度W3小於第二橫焊墊521之寬度W4。More specifically, in one example, the length L1 of each first straight bonding pad 411 is greater than the length L2 of one of the second straight bonding pads 511 , and the width W1 of each first straight bonding pad 411 is smaller than the second straight bonding pad 511 The width is W2. The length L3 of each first horizontal bonding pad 421 is greater than the length L4 of one of the second horizontal bonding pads 521 , and the width W3 of each first horizontal bonding pad 421 is smaller than the width W4 of the second horizontal bonding pad 521 .
第4A圖為第2圖之傳輸線路圖案200搭配第一電源用焊墊440、第二電源用焊墊540之關係示意圖。如第2圖與第4A圖所示，第一焊墊聚集圖案400包含至少一第一訊號用焊墊430及至少一第一電源用焊墊440。舉例來說，其中一第一橫向柱狀區410之所有第一直焊墊411中包含數個第一訊號用焊墊430及第一電源用焊墊440。第二焊墊聚集圖案500包含至少一第二訊號用焊墊530及至少一第二電源用焊墊540。舉例來說，其中一第二橫向柱狀區510之所有第二直焊墊511中包含數個第二訊號用焊墊530及第二電源用焊墊540。依據矩形區310之中心往其邊緣之方向，其中一第二訊號用焊墊530透過所述第一印刷線路610連接第一訊號用焊墊430。依據矩形區310之中心往其邊緣之方向，第一電源用焊墊440透過位於層疊結構100內部的立體途徑間接連接傳輸線路圖案200，而第二電源用焊墊540透過位於層疊結構100的外表面120的印刷線路或內部的立體途徑直接或間接連接傳輸線路圖案200。Figure 4A is a schematic diagram of the relationship between the transmission line pattern 200 of Figure 2 and the first power supply pad 440 and the second power supply pad 540. As shown in FIGS. 2 and 4A , the first pad gathering pattern 400 includes at least one first signal pad 430 and at least one first power pad 440 . For example, all the first direct bonding pads 411 in one of the first lateral columnar regions 410 include several first signal bonding pads 430 and first power supply bonding pads 440 . The second pad gathering pattern 500 includes at least one second signal pad 530 and at least one second power pad 540 . For example, all the second straight bonding pads 511 in one of the second lateral columnar regions 510 include several second signal bonding pads 530 and second power supply bonding pads 540 . According to the direction from the center of the rectangular area 310 to its edge, a second signal pad 530 is connected to the first signal pad 430 through the first printed circuit 610 . According to the direction from the center of the rectangular area 310 to its edge, the first power supply pad 440 is indirectly connected to the transmission line pattern 200 through a three-dimensional path located inside the laminated structure 100 , and the second power supply pad 540 is located outside the laminated structure 100 . The printed circuits on the surface 120 or the internal three-dimensional pathways are directly or indirectly connected to the transmission circuit pattern 200 .
第4B圖為第2圖之印刷電路板10搭配訊號用焊墊、第一跨接電阻450與第二跨接電阻460之關係示意圖。如第2圖與第4B圖所示，晶片配置區300包含第一跨接電阻450與第二跨接電阻460，第一跨接電阻450電連接第一訊號用焊墊430與傳輸線路圖案200。第二跨接電阻460電連接第二訊號用焊墊530與傳輸線路圖案200。如此，當封裝晶片焊接至第一焊墊聚集圖案400時，藉由第一跨接電阻450之串接作用，第一跨接電阻450能夠使第一訊號用焊墊430導通傳輸線路圖案200。當另個封裝晶片焊接至第二焊墊聚集圖案500時，藉由第二跨接電阻460之串接作用，第二跨接電阻460能夠使第二訊號用焊墊530導通傳輸線路圖案200。Figure 4B is a schematic diagram of the relationship between the printed circuit board 10 of Figure 2 and the signal pads, the first jumper resistor 450 and the second jumper resistor 460. As shown in Figures 2 and 4B, the chip configuration area 300 includes a first jumper resistor 450 and a second jumper resistor 460. The first jumper resistor 450 is electrically connected to the first signal pad 430 and the transmission line pattern 200. . The second jumper resistor 460 is electrically connected to the second signal pad 530 and the transmission line pattern 200 . In this way, when the package chip is soldered to the first bonding pad gathering pattern 400, through the series connection of the first bonding resistor 450, the first bonding pad 430 for signals can be connected to the transmission line pattern 200 by the first bonding resistor 450. When another package chip is soldered to the second pad gathering pattern 500, through the series connection of the second jumper resistor 460, the second jumper resistor 460 can enable the second signal pad 530 to conduct the transmission line pattern 200.
如此，透過以上架構，本揭露能夠滿足在同一個電路板能應用於多種封裝模式之積體電路，亦即能夠使用(採購)兩種不同封裝的晶片。此外，本案還可以進行模組化核心電路，將同一區塊的積體線路能夠複製到另一個電路板設計之應用，能夠達成兩種不同封裝晶片的功能，如此一來能將此技術套用在任何電路板設計。In this way, through the above structure, the present disclosure can satisfy the requirement that the same circuit board can be applied to integrated circuits of multiple packaging modes, that is, two different packaged chips can be used (purchased). In addition, this case can also modularize the core circuit, and the integrated circuits of the same block can be copied to another circuit board design application, which can achieve the functions of two different packaging chips. In this way, this technology can be applied to Any circuit board design.
最後，上述所揭露之各實施例中，並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，皆可被保護於本發明中。因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Finally, the above disclosed embodiments are not intended to limit the present invention. Anyone skilled in the art can make various modifications and modifications without departing from the spirit and scope of the present invention, and all of them are protected by the present invention. Inventing. Therefore, the protection scope of the present invention shall be determined by the appended patent application scope.
10:印刷電路板10:Printed circuit board
100:層疊結構100:Laminated structure
110:板體110:Plate body
120:外表面120:Outer surface
200:傳輸線路圖案200:Transmission line pattern
300:晶片配置區300: Chip configuration area
310:矩形區310: Rectangular area
320:第一環狀區320: First ring area
330:第二環狀區330:Second ring area
400:第一焊墊聚集圖案400: First pad gathering pattern
410:第一橫向柱狀區410: First transverse columnar area
411:第一直焊墊411: The first direct soldering pad
420:第一縱向柱狀區420: First longitudinal columnar area
421:第一橫焊墊421: First horizontal pad
430:第一訊號用焊墊430: Soldering pad for first signal
440:第一電源用焊墊440: Soldering pad for first power supply
450:第一跨接電阻450: First jumper resistor
460:第二跨接電阻460: Second jumper resistor
500:第二焊墊聚集圖案500: Second pad gathering pattern
510:第二橫向柱狀區510: Second horizontal columnar area
511:第二直焊墊511: Second straight soldering pad
520:第二縱向柱狀區520: Second longitudinal columnar area
521:第二橫焊墊521: Second horizontal pad
530:第二訊號用焊墊530: Solder pad for second signal
540:第二電源用焊墊540: Soldering pad for second power supply
610:第一印刷線路610: First Printing Line
620:第二印刷線路620: Second printing line
700:第一立體途徑700:First three-dimensional pathway
710:第一導孔710: First guide hole
720:第二導孔720: Second guide hole
730:第一層內導線730: First layer inner conductor
800:第二立體途徑800: Second three-dimensional pathway
810:第三導孔810:Third guide hole
820:第四導孔820:Fourth guide hole
830:第二層內導線830: Second layer inner conductor
D1:第一軸向D1: first axis
D2:第二軸向D2: Second axis
H:橫向H:Horizontal
L1、L2、L3、L4:長度L1, L2, L3, L4: length
P:區域P:Area
W1、W2、W3、W4:寬度W1, W2, W3, W4: Width
V:縱向V: Vertical
為讓本發明之上述和其他目的、特徵、優點與實施例能更明顯易懂，所附圖式之說明如下： 第1圖為本發明一實施例之印刷電路板的上視圖。 第2圖為第1圖之區域P的放大圖。 第3圖為第2圖之印刷電路板的局部剖視圖。 第4A圖為第2圖之傳輸線路圖案搭配第一電源用焊墊、第二電源用焊墊之關係示意圖。 第4B圖為第2圖之印刷電路板搭配訊號用焊墊、第一跨接電阻與第二跨接電阻之關係示意圖。 In order to make the above and other objects, features, advantages and embodiments of the present invention more apparent and understandable, the accompanying drawings are described as follows: Figure 1 is a top view of a printed circuit board according to an embodiment of the present invention. Figure 2 is an enlarged view of area P in Figure 1. Figure 3 is a partial cross-sectional view of the printed circuit board of Figure 2 . Figure 4A is a schematic diagram of the relationship between the transmission line pattern in Figure 2 and the first power supply pads and the second power supply pads. Figure 4B is a schematic diagram of the relationship between the printed circuit board in Figure 2 and the signal pads, the first jumper resistor and the second jumper resistor.
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無 Domestic storage information (please note in order of storage institution, date and number) without Overseas storage information (please note in order of storage country, institution, date, and number) without
10:印刷電路板 10:Printed circuit board
100:層疊結構 100:Laminated structure
120:外表面 120:Outer surface
200:傳輸線路圖案 200:Transmission line pattern
300:晶片配置區 300: Chip configuration area
310:矩形區 310: Rectangular area
320:第一環狀區 320: First ring area
330:第二環狀區 330:Second ring area
400:第一焊墊聚集圖案 400: First pad gathering pattern
500:第二焊墊聚集圖案 500: Second pad gathering pattern
D1:第一軸向 D1: first axis
D2:第二軸向 D2: Second axis
P:區域 P:Area
Claims (20)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW111146649A TWI822504B (en) | 2022-12-05 | 2022-12-05 | Printed circuit board |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW111146649A TWI822504B (en) | 2022-12-05 | 2022-12-05 | Printed circuit board |
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| Publication Number | Publication Date |
|---|---|
| TWI822504B true TWI822504B (en) | 2023-11-11 |
Family
ID=89722660
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| Application Number | Title | Priority Date | Filing Date |
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| TW111146649A TWI822504B (en) | 2022-12-05 | 2022-12-05 | Printed circuit board |
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| Country | Link |
|---|---|
| TW (1) | TWI822504B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0503201A2 (en) * | 1990-12-20 | 1992-09-16 | Kabushiki Kaisha Toshiba | Semiconductor device having an interconnecting circuit board and method for manufacturing same |
| US20050161796A1 (en) * | 1996-11-20 | 2005-07-28 | Wark James M. | Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice |
| TW200810079A (en) * | 2006-04-17 | 2008-02-16 | Elpida Memory Inc | Stacked semiconductor device and fabrication method for same |
| TW200814258A (en) * | 2006-09-08 | 2008-03-16 | Taiwan Solutions Systems Corp | Chip package structure |
| TW200845334A (en) * | 2007-05-15 | 2008-11-16 | Chipmos Technology Inc | Chip stacked package structure and applications thereof |
-
2022
- 2022-12-05 TW TW111146649A patent/TWI822504B/en active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0503201A2 (en) * | 1990-12-20 | 1992-09-16 | Kabushiki Kaisha Toshiba | Semiconductor device having an interconnecting circuit board and method for manufacturing same |
| US20050161796A1 (en) * | 1996-11-20 | 2005-07-28 | Wark James M. | Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice |
| TW200810079A (en) * | 2006-04-17 | 2008-02-16 | Elpida Memory Inc | Stacked semiconductor device and fabrication method for same |
| TW200814258A (en) * | 2006-09-08 | 2008-03-16 | Taiwan Solutions Systems Corp | Chip package structure |
| TW200845334A (en) * | 2007-05-15 | 2008-11-16 | Chipmos Technology Inc | Chip stacked package structure and applications thereof |
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