TWI817484B - Timing control circuit and timing control method thereof - Google Patents

Abstract

A timing control circuit includes a receiving circuit and a line memory coupled to the receiving circuit. The line memory is configured for outputting a first data signal during a first frame, and outputting a second data signal during a second frame. An end time point of the first frame period coincides with the start time point of the second frame period. One of the first data signal and the second data signal is corresponding to a long H mode; the other of the first data signal and the second data signal is corresponding to a long V mode.

Description

Timing control circuit and timing control method

The present invention refers to a timing control circuit and a timing control method thereof, in particular to a timing control circuit and a timing control method that can improve display quality and reliability.

In the touch and display driver integrated circuit (TDDI), display operations and touch operations are performed in a time-sharing manner to avoid noise interference that affects the touch sensor or produces erroneous display results. . In order to improve display quality and reliability, there is still room for improvement in the operation of touch and display driver integrated circuits.

Therefore, the present invention mainly provides a timing control circuit and a timing control method thereof to improve display quality and reliability.

The invention discloses a timing control circuit, including a receiving circuit; and a line memory coupled to the receiving circuit, wherein the line memory is used to output a first data signal during a first frame; and a second frame A second data signal is output during the period, wherein the end time point of the first frame period coincides with the starting time point of the second frame period, wherein one of the first data signal and the second data signal corresponds to a Long horizontal scan pause mode, the first data signal and the second data signal The other one corresponds to a long vertical scan pause mode.

The present invention also discloses a timing control method, including outputting a first data signal during a first frame period; and outputting a second data signal during a second frame period, wherein the end time point of the first frame period is the same as the end time point of the first frame period. The starting time point of the second frame period coincides, wherein one of the first data signal and the second data signal corresponds to a long horizontal scan pause mode, and the other of the first data signal and the second data signal Corresponds to a long vertical scan pause mode.

10:Touch display device

100:Video packet streaming

110: Drive circuit

111: Timing control circuit

111a: receiving circuit

111b: line memory

111c: Timing generation circuit

111d: Oscillation circuit

112: Source driver

113:Gate driver

114:Touch circuit

120:Touch display panel

122:Touch electrode

122S, 122S1a~122S10b, 122S1c, 122S2c: touch signal

BLLP: low power blank period

DL2~DL4: Delay

F1~F4,F12~F14,F22,F23: frames

FP1~FP3,FP12,FP13: frame period

FP2DP, FP2DPr: During display operation

FP2TP: During touch operation

FP3DP1~FP3DP10, FP2DP1~FP2DPn: Display operation sub-period

FP3TP1~FP3TP10: Touch operation sub-period

HBP: horizontal trailing edge

HFP: horizontal frontier

HS: Horizontal synchronization starts

Hsync1: external horizontal synchronization signal

Hsync2: internal horizontal synchronization signal

LPM: low power

RGB: horizontal sync pulse line period

tL1~tL3,tL2’,tL3’,tL12~tL14: horizontal period

tVBP2, tVBP3, tVBP2’, tVBP3’, tVBP13’: vertical trailing edge time

tVFP2,tVFP3,tVFP2’,tVFP3’,tVFP12’: vertical leading edge time

VS: Vertical synchronization ends

Vsync1: external vertical synchronization signal

Figure 1 is a schematic diagram of a touch display device according to an embodiment of the present invention.

Figure 2 is a timing diagram of an embodiment of the present invention.

Figures 3 and 4 are respectively enlarged partial views of Figure 2.

Figures 5 to 7 are respectively timing diagrams of embodiments of the present invention.

Figure 1 is a schematic diagram of a touch display device 10 according to an embodiment of the present invention. The touch display device 10 includes a driving circuit 110 and a touch display panel 120 . The driver circuit 110 can receive a video packet stream 100 from a front-end circuit (not shown) (such as a processor, etc.) through a transmission interface. Different frames of the video packet stream 100 may correspond to horizontal periods of different lengths (also known as 1H or line time), and the driver circuit 110 can switch between long horizontal scan pause mode (long H mode) and long vertical scan pause mode (long V mode) to ensure display quality.

In detail, the driving circuit 110 may include a timing control circuit 111, a source driver 112, Gate driver 113 and touch circuit 114. The timing control circuit 111 can receive the video packet stream 100 . The timing control circuit 111 can provide a vertical start signal or a gate frequency signal to the gate driver 113 according to the video packet stream 100, so that the gate driver 113 can drive at least one gate line (not shown) of the touch display panel 120. . The timing control circuit 111 can provide a vertical synchronization signal, a horizontal start signal or a data signal to the source driver 112 according to the video packet stream 100, so that the source driver 112 can drive at least one data line (not shown) of the touch display panel 120. ). The timing control circuit 111 can control the touch circuit 114 so that the touch circuit 114 can provide a touch signal to drive at least one touch electrode 122 of the touch display panel 120 .

The timing control circuit 111 may include a receiving circuit 111a, a line memory 111b, a timing generating circuit 111c, and an oscillation circuit 111d. Please refer to Figures 1 to 4 together. Figure 2 is a timing diagram of an embodiment of the present invention. Figures 3 and 4 are respectively enlarged partial diagrams of Figure 2.

The receiving circuit 111a can be used to receive the video packet stream 100. In one embodiment, the receiving circuit 111a can decode the video packet stream 100 to generate the external vertical synchronization signal Vsync1, the external horizontal synchronization signal Hsync1 or the original data signal as shown in FIG. 2 . The external vertical synchronization signal Vsync1 is used to indicate the start or end of a frame. As shown in FIG. 2 , the external horizontal synchronization signal Hsync1 may have multiple pulses (or lines) in one frame (for example, one of the frames F1 to F4). The period of one pulse is one horizontal period (for example, horizontal periods tL1, tL2, tL3). The horizontal period (eg, horizontal period tL2) of each pulse of a frame (eg, frame F2) is the same, but the horizontal periods (eg, horizontal period tL2, tL3) of different frames (eg, frames F2, F3) may be different.

The oscillator circuit 111d can be used to provide an internal frequency signal to the timing generation circuit 111c or the touch circuit 114.

The timing generation circuit 111c can be used to receive the external horizontal synchronization signal Hsync1 from the receiving circuit 111a, and convert the external horizontal synchronization signal Hsync1 into the internal horizontal synchronization signal Hsync2 according to the internal frequency signal from the oscillator circuit 111d. In addition, the timing generation circuit 111c can be used to detect the time length of the horizontal period of the external horizontal synchronization signal Hsync1 (for example, the horizontal period tL1~tL3) to determine whether to switch to the long horizontal scan pause mode or the long vertical scan pause mode.

In one embodiment, the line memory 111b can be used to receive the external vertical synchronization signal Vsync1, the external horizontal synchronization signal Hsync1 or the original data signal from the receiving circuit 111a, and can convert the pixel data (such as the original data signal) according to the external horizontal synchronization signal Hsync1. Write line memory 111b. The line memory 111b can be used to receive the internal horizontal synchronization signal Hsync2 from the timing generation circuit 111c, and can provide pixel data (such as the first data signal output by FP2 during the frame period or the second data signal output by FP3 during the frame period) according to the internal horizontal synchronization signal Hsync2. data signal) to the source driver 112. The first data signal and the second data signal may correspond to different scan pause modes. For example, the first data signal may correspond to a long vertical scan pause mode, and the second data signal may correspond to a long horizontal scan pause mode.

In short, the timing generation circuit 111c can be used to determine whether the time length of the external horizontal synchronization signal Hsync1 in the horizontal periods of two consecutive frames (for example, the horizontal periods tL1 to tL3) is the same. Based on the time length difference between the horizontal periods tL2 and tL3, the first data signal and the second data signal respectively correspond to different ones of the long horizontal scan pause mode and the long vertical scan pause mode. Based on the fact that there is no time length difference between the horizontal periods tL1 and tL2, the data signal output during the frame period FP1 and the second data signal output during the frame period FP2 correspond to the same one of the long horizontal scan pause mode and the long vertical scan pause mode.

For example, the receiving circuit 111a may receive the first external signal of the video packet stream 100 in frame F2, and extract the external horizontal synchronization signal Hsync1 from the first external signal in the horizontal period tL2 of frame F2 and The original data signal of frame F2 is written into the line memory 111b according to the external horizontal synchronization signal Hsync1. Accordingly, the line memory 111b can provide the first data signal to the source driver 112 in the frame period FP2 according to the internal horizontal synchronization signal Hsync2. The frame period FP2 corresponds to the frame F2 and has the same time length as the frame F2. Furthermore, based on the short horizontal period tL2, the first data signal may correspond to the long vertical scan pause mode. Based on the fact that the horizontal period tL1 is equal to the horizontal period tL2 , the data signal and the first data signal output by FP1 during the frame period can both correspond to the long vertical scan pause mode.

As shown in Figure 2, in the long vertical scan pause mode, the frame period FP2 is divided into a display operation period FP2DP and a touch operation period FP2TP. During a display operation, FP2DP is used to output pixel data to the touch display panel 120, and during a continuous display operation, FP2DP is used for all display operations of a frame. During the touch operation period FP2TP is used to transmit the touch signal 122S, and the scanning of the touch electrode 122 is continuously performed. The touch signal 122S shown in FIG. 3 is transmitted during the continuous touch operation period FP2TP. The long vertical scan pause mode can perform a touch operation after the pixel data corresponding to all gate lines is output, that is, the touch operation will not be performed until the display operation of a complete frame is completed. Since the display operation is performed continuously, display stripes in the long horizontal scan pause mode can be avoided and reliability can be improved.

Similarly, the receiving circuit 111a can receive the second external signal of the video packet stream 100 in frame F3, extract the external horizontal synchronization signal Hsync1 in the horizontal period tL3 of frame F3 and the original data signal of frame F3 from the second external signal, and The original data signal is written into the line memory 111b according to the external horizontal synchronization signal Hsync1. Accordingly, the line memory 111b can provide the second data signal to the source driver 112 in the frame period FP3 according to the internal horizontal synchronization signal Hsync2. The frame period FP3 corresponds to the frame F3 and has the same time length as the frame F3. Furthermore, since the horizontal period tL3 is longer (compared to the horizontal period tL2 ), the second data signal may correspond to the long horizontal scan pause mode.

In the long horizontal scan pause mode, the frame period FP3 is divided into multiple time units (for example, 10 time units). Each time unit has a display operation sub-period and a touch operation sub-period. The display operation sub-periods FP3DP1 to FP3DP10 are used to output pixel data to the touch display panel 120 . The touch operation sub-period FP3TP1~FP3TP10 is used to transmit touch signals. For example, the touch signals 122S1a ~ 122S10b shown in Figure 4 can be transmitted during the intermittent touch operation sub-periods FP3TP1 ~ FP3TP10 respectively. Since the time length of a touch operation sub-period cannot be too long, so in a touch operation sub-period Only part of the touch electrodes 122 (for example, one row/column or several rows/columns of the touch electrodes 122) is driven during the control operation sub-period. A touch operation sub-period can be inserted between two adjacent display operation sub-periods. That is, in the long horizontal scan pause mode, the display operation sub-periods FP3DP1~FP3DP10 and the touch operation sub-periods FP3TP1~FP3TP10 are interleaved with each other. That is to say, in the long horizontal scan pause mode, a long horizontal scan pause period (i.e., a touch operation sub-period) can be performed after driving a fixed number of gate lines (or outputting pixel data corresponding to these gate lines). ) pauses display operations to allow for touch operations.

During the touch operation sub-period (for example, the touch operation sub-period FP3TP1), the pixel data written into the line memory 111b will be read from the line memory 111b corresponding to the internal horizontal synchronization signal Hsync2 in the next display operation sub-period (for example, the display operation sub-period FP3DP2). read out. In one embodiment, the data lines FP3TP1 to FP3TP10 are not necessarily equal to 0 volts during the touch operation sub-period. The data lines may have a waveform with the same voltage difference/phase as the touch signal to reduce the load of the touch signal ( Loading) (i.e. load free drive (LFD)).

In the long horizontal scan pause mode, the long horizontal scan pause period usually occurs on the same gate line, making the driving time of this gate line much longer than the driving time of other gate lines. Therefore, the gate line located on this gate line Circuit components (such as thin film transistors) decay faster than other gates The circuit components on the line decay faster, resulting in poorer display performance of this gate line. For example, turning on the thin film transistors on certain gate lines for a long time causes these gate lines to age more seriously, which may result in irrecoverable display stripes (also known as horizontal lines, longH stripes or horizontal stripes) on the touch display panel 120. horizontal gate line stripes). By switching between the long horizontal scan pause mode and the long vertical scan pause mode, irrecoverable display horizontal lines on the touch display panel 120 can be avoided.

High frame rate and low frame rate

In one embodiment, a long vertical scan pause mode may be used at high frame rate (HFR), and a long horizontal scan pause mode may be used at low frame rate (LFR). For example, the frame period FP2 may be 8.33 milliseconds (ms), and the frame rate (refresh rate or frame rate or display frame rate) is the reciprocal of the frame period. Therefore, the frame rate corresponding to the frame period FP2 may be, for example, 120 Hz. (Hertz, Hz). The frame period FP3 may be, for example, 16.67 milliseconds, and the frame rate may be, for example, 60 Hz. Based on the fact that the frame period FP2 of the first data signal is smaller than the frame period FP3 of the second data signal (that is, the frame periods FP2 and FP3 correspond to the high frame rate and the low frame rate respectively), the first data signal corresponds to the long vertical scan pause mode, The second data signal corresponds to the long horizontal scan pause mode. Using a long vertical scan pause mode at a high frame rate can avoid irrecoverable display horizontal stripes on the touch display panel 120 when the horizontal period tL2 is short.

In one embodiment, based on the frame period FP2 of the first data signal being smaller than the frame period FP3 of the second data signal, the first data signal corresponds to the long vertical scan pause mode, and the second data signal corresponds to the long horizontal scan pause mode and the extended horizontal scan. Pause mode (extend H mode). The number of pulses (i.e., line count) corresponding to the frame period FP3 of the extended horizontal scan pause mode does not change (for example, equal to the number of pulses of the frame period FP2). On the other hand, the number of pulses corresponding to the extended horizontal scan pause mode tL3 is longer (for example, greater than the horizontal period tL2), and the frame period FP3 corresponding to the extended horizontal scan pause mode is longer (for example, greater than the frame period FP2), so that the frame period FP3 corresponds to a low frame rate (for example, lower than the frame period FP2). Rate). In the extended horizontal scan pause mode, the vertical blank period not used for display operation is less than one-half of the frame period FP3, where the vertical blank period of a frame may include vertical front time (Vertical Front Porch, VFP), vertical trailing edge (Vertical Back Porch, VBP) time or the vertical synchronization time corresponding to the external vertical synchronization signal Vsync1. Since the vertical leading edge time tVFP3’ of FP3 during the frame period is not too long in the extended horizontal scan pause mode, flickering screen problems can be avoided. In addition, the horizontal period tL3 corresponding to the extended horizontal scan pause mode is longer, so the voltage is relatively easy to reach a predetermined level.

In another embodiment, the second data signal may also correspond to an extended vertical edge mode (extend Vproch mode). In the extended vertical edge mode, due to the long vertical blank period of a frame, the non-driving time of each gate line is long, and the circuit components (such as thin film transistors) located on the gate lines are not conductive for a long time, causing the liquid crystal capacitor to The potential decrease affects the expected gray scale value. In the next frame, the circuit elements located on the gate lines are turned on again and the liquid crystal capacitor is charged and adjusted to the expected gray scale value, so that the touch display panel 120 may have a flickering problem.

Touch report rate

In one embodiment, frame period FP2 and frame period FP3 are not equal, but the touch report rate corresponding to frame period FP2 may be equal to the touch report rate (touch report rate or touch frame rate) corresponding to frame period FP3. For example, the frame period FP2 and the frame period FP3 can be 8.33 milliseconds and 16.67 milliseconds respectively, so that the frame rates are 120Hz and 60Hz respectively, but the touch reporting rates can both be 120Hz, for example.

Specifically, in long vertical scan pause mode, the touch reporting rate can be equal to the frame rate. Therefore, all display operations of one frame are performed during one frame period (for example, frame period FP2), and the touch operation can scan the touch display panel 120 once. For example, FP2TP uses the touch signal 122S to drive the touch electrode 122 only during the touch operation.

In the long horizontal scan pause mode, the touch reporting rate may not be equal to the frame rate, and the touch reporting rate may be equal to an integer multiple (integer multiple) or a fractional multiple (fractional multiple) of the frame rate. Therefore, all display operations of one frame are performed during one frame period (for example, frame period FP3), and the touch operation can scan the entire touch display panel 120 an integer number of times or a non-integer number of times. For example, the touch display panel 120 may include 10 rows (or 10 columns) of touch electrodes 122 . The touch operation sub-periods FP3TP1~FP3TP5 can be used to perform the first scan of the touch electrodes 122 in the 1st row (column) to the 10th row (column), and the touch operation sub-periods FP3TP6~FP3TP10 can be used to perform the first scan of the 1st row (column). ) to the second scan of the 10th row (column) touch electrode 122 . For example, during the touch operation sub-period FP3TP1 uses the touch signal 122S1a to drive the touch electrodes 122 in the first row (column), and during the touch operation sub-period FP3TP6 uses the touch signal 122S1b to drive the first row (column). of touch electrodes 122 . In other words, the touch operation can scan the entire touch display panel 120 twice. Accordingly, the long horizontal scan pause mode can achieve a touch reporting rate that is different from the frame rate.

In short, by switching between the long horizontal scan pause mode and the long vertical scan pause mode, even if the frame period FP2 and the frame period FP3 are not equal, the frame rate corresponding to the frame period FP2 is not equal to the frame rate corresponding to the frame period FP3, However, the touch reporting rate corresponding to frame period FP2 may be equal to the touch reporting rate corresponding to frame period FP3.

In one embodiment, when switching from a high frame rate (eg, 120 Hz) to a low frame rate (eg, 40 Hz), the touch reporting rate can be maintained at 120 Hz, but the invention is not limited thereto. In another embodiment, when switching from a high frame rate (for example, 120Hz) to a low frame rate (for example, 40Hz), the touch reporting rate can be changed according to different design considerations (for example, switching from 120Hz to 60Hz).

delay

In one embodiment, in the long vertical scan pause mode, pixel data may not be written to the line memory 111b. In another embodiment, the line memory 111b may be used to switch between the long horizontal scan pause mode and the long vertical scan pause mode. That is, in the long horizontal scan pause mode, pixel data can be written into the line memory 111b to squeeze out the period for touch operations. Correspondingly, in the long vertical scan pause mode, pixel data is also written into the line memory 111b.

Specifically, please refer to Figure 1 and Figure 4. In the long horizontal scan pause mode, the frequency of the internal horizontal synchronization signal Hsync2 may be higher than the frequency of the external horizontal synchronization signal Hsync1. The receiving circuit 111a can write pixel data (eg, original data signal) into the line memory 111b according to the external horizontal synchronization signal Hsync1. Furthermore, the pixel data can be read out from the line memory 111b at a faster data rate according to the internal horizontal synchronization signal Hsync2 during the frame period FP3. In this way, the time for display operations can be compressed and the time period used for touch operations can be squeezed out.

As shown in Figure 4, the horizontal period tL3' corresponding to the display operation sub-period FP3DP1 is smaller than the horizontal period tL3 of the external horizontal synchronization signal Hsync1, so the touch operation sub-period FP3TP1 for touch operations can be squeezed out. The horizontal period tL3 of the external horizontal synchronization signal Hsync1 may correspond to the time for writing pixel data corresponding to one gate line to the line memory 111b. The horizontal period tL3' may be a period time of applying voltage to a row of pixels of the touch display panel 120 (that is, between the starting time point of applying voltage to one row of pixels to the starting time point of applying voltage to another row of pixels). The length of time between), that is, the cycle time of driving one gate line (that is, the length of time between the starting time point of driving one gate line and the starting time point of driving another gate line). The horizontal period tL3' may correspond to the time for reading pixel data corresponding to one gate line from the line memory 111b.

For example, in the long horizontal scan pause mode, the receiving circuit 111a may The flat synchronization signal Hsync1 writes the received pixel data corresponding to the 20 gate lines into the line memory 111b in the time length of one time unit. The internal horizontal synchronization signal Hsync2 can be used to control the pixel data corresponding to the 20 gate lines to be read out from the line memory 111b at a faster data rate and transferred to the touch display panel 120, so that during a display operation sub-period (such as In the display operation sub-period FP3DP1), the display operation of pixel data corresponding to 20 gate lines is performed. That is, the amount of pixel data received in a time unit is equal to the amount of pixel data output in a display operation sub-period of a time unit.

For example, in the long horizontal scan pause mode, a specific amount of pixel data (for example, the gates of columns 1 to 20) can be output corresponding to the internal horizontal synchronization signal Hsync2 during a display operation sub-period (such as the display operation sub-period FP3DP1). pixel data corresponding to the gate lines) to the touch display panel 120, and then enters the touch operation sub-period (such as the touch operation sub-period FP3TP1), and other pixel data (such as pixels corresponding to the gate lines in the 21st to 27th columns) Data) during the touch operation sub-period FP3TP1 still continues to be written (temporarily stored) in the line memory 111b corresponding to the external horizontal synchronization signal Hsync1. Moreover, the pixel data newly written into the line memory 111b (pixel data corresponding to the gate lines of the 21st to 27th columns) will correspond to the internal horizontal synchronization signal Hsync2 from the line in the next display operation sub-period (for example, the display operation sub-period FP3DP2). The memory 111b is read out, and other pixel data (such as pixel data corresponding to the gate lines of the 28th to 40th columns) is written into the line memory 111b corresponding to the external horizontal synchronization signal Hsync1 and corresponding to the internal horizontal synchronization during the display operation sub-period FP3DP2 The signal Hsync2 is output to the touch display panel 120 .

In the long horizontal scan pause mode, because part of the pixel data (such as the pixel data corresponding to the gate lines of the 1st to 7th columns) must be written (temporarily) before the display operation sub-period (such as the display operation sub-period FP3DP1), There is) line memory 111b. Therefore, as shown in FIG. 2, there may be a delay DL3 between (frame F3 of the external horizontal synchronization signal Hsync1) and (frame period FP3 of the internal horizontal synchronization signal Hsync2). The delay DL3 may be greater than or equal to the writing time of the pixel data that needs to be written into the line memory 111b first, This is to avoid the need to read pixel data that has not been written to the line memory 111b during the display operation sub-period (eg, the display operation sub-period FP3DP1). For example, during the touch operation sub-period (such as the touch operation sub-period FP3TP1), the number of lines corresponds to 50 (meaning that pixel data corresponding to 50 gate lines is written to the line memory 111b), the line memory 111b can To store pixel data corresponding to 100 columns of gate lines, the number of lines corresponding to delay DL3 can be greater than or equal to 50 and less than 100.

In one embodiment, in the long vertical scan pause mode, as shown in FIG. 2, there may be a delay DL2 between the external horizontal synchronization signal Hsync1 (frame F2) and the internal horizontal synchronization signal Hsync2 (frame period FP2). In one embodiment, in order to dynamically switch between the long horizontal scan pause mode and the long vertical scan pause mode, in the long vertical scan pause mode, as shown in Figure 2, the external horizontal synchronization signal Hsync1 (frame F4) There may be a delay DL4 with the internal horizontal synchronization signal Hsync2 (frame period FP4).

In one embodiment, the delays DL2, DL3, and DL4 between the external horizontal synchronization signal Hsync1 and the internal horizontal synchronization signal Hsync2 may correspond to the same number of lines (or the number of pulses). For example, delays DL2, DL3, and DL4 can correspond to 50 lines respectively. In one embodiment, the delay DL2 is proportional to the horizontal period tL2, the delay DL3 is proportional to the horizontal period tL3, and the ratio between the delay DL2 and the delay DL3 is equal to the ratio between the horizontal period tL2 and the horizontal period tL3. In one embodiment, since the horizontal period tL2 is smaller than the horizontal period tL3, the time length of the delay DL3 may be greater than the time length of the delay DL2. In another embodiment, the number of lines corresponding to delays DL2 and DL4 may be greater than the number of lines corresponding to delay DL3.

Detect touch events or touch locations

In the long vertical scan pause mode, as shown in Figure 3, at the vertical leading edge time tVFP2' corresponding to the touch operation period FP2TP, the timing generation circuit 111c can control the touch circuit 114 to (minutes (time) to drive (all) the touch electrodes 122 of the touch display panel 120 in order to sense/detect touch events and/or touch positions that occur on the touch display panel 120 .

In another embodiment, in the long vertical scan pause mode, in order to further squeeze out the time period for the touch operation, the time of the display operation can be compressed. Please refer to Figure 5, which is a timing diagram of an embodiment of the present invention. As shown in Figure 5, touch operations can be performed during the touch operation sub-periods FP2TP1 and FP2TP2, where the touch operation sub-period FP2TP2 corresponds to the vertical leading edge time tVFP2', which is equivalent to the touch operation period shown in Figure 3 FP2TP.

Specifically, in the long vertical scan pause mode, the frequency of the internal horizontal synchronization signal Hsync2 may be higher than the frequency of the external horizontal synchronization signal Hsync1. The receiving circuit 111a can write pixel data (eg, original data signal) into the line memory 111b according to the external horizontal synchronization signal Hsync1. Moreover, the pixel data can be read out from the line memory 111b at a faster data rate according to the internal horizontal synchronization signal Hsync2 during the frame period FP2.

For example, in the long vertical scan pause mode, the time length of a display operation sub-period (such as the display operation sub-period FP2DP1) is equivalent to 32 horizontal periods tL2 of the internal synchronization signal Hsync2 (corresponding to 32 pulses/line number) 'or 31 horizontal periods tL2 of the external horizontal synchronization signal Hsync1 (corresponding to 31 pulses/line number). During a display operation sub-period (for example, the display operation sub-period FP2DP1), the receiving circuit 111a can write the received pixel data corresponding to the 31 gate lines into the line memory 111b according to the external horizontal synchronization signal Hsync1. Moreover, the pixel data corresponding to the 32 gate lines can be read out from the line memory 111b at a faster data rate according to the internal horizontal synchronization signal Hsync2 during the frame period FP2.

In the long vertical scan pause mode, if the 32 horizontal periods tL2' of the internal synchronization signal Hsync2 (corresponding to one display operation sub-period) are equivalent to the 31 horizontal periods tL2 of the external horizontal synchronization signal Hsync1, and FP2DPr can be drawn during the display operation Divided into n (for example, 45) display operation sub-periods FP2DP1~FP2DPn, compared with the display operation period FP2DP shown in Figure 3, the display operation period FP2DPr lacks n (for example, 45) external horizontal synchronization signals Hsync1 ) horizontal period tL2, which can be used as the touch operation sub-period FP2TP1.

In other words, in the long vertical scan pause mode, as shown in FIG. 5 , the touch operation can be performed during the touch operation sub-period FP2TP1 and the touch operation sub-period FP2TP2 corresponding to the vertical leading edge time tVFP2′. During the touch operation sub-periods FP2TP1 and FP2TP2, the timing generation circuit 111c can control the touch circuit 114 to (time-division) drive (all) the touch electrodes 122 of the touch display panel 120 so that sensing/detection occurs in the touch display. Touch event and/or touch location of panel 120 . For example, the touch signal 122S1c in Figure 5 can be used to drive the touch electrodes 122 in the first row (column), and the touch signal 122S2c in Figure 5 can be used to drive the touch electrodes 122 in the second row (column). . When the touch operation sub-period FP2TP1 is used for touch operations, the vertical frontier time tVFP2' (or the number of vertical frontier lines can be reduced) can be shortened, the bit rate can be reduced, and the required bandwidth can be reduced, thereby saving money. power consumption.

In the long vertical scan pause mode, if 32 horizontal periods tL2' of the internal synchronization signal Hsync2 (corresponding to one display operation sub-period) are equivalent to 31 horizontal periods tL2 of the external horizontal synchronization signal Hsync1, then the line memory 111b corresponds to a display The operation sub-period (for example, the display operation sub-period FP2DP1) may need to temporarily store pixel data corresponding to one gate line (or pixel data corresponding to one line). If the display operation period FP2DPr can be divided into 45 display operation sub-periods FP2DP1~FP2DPn, the line memory 111b may need to temporarily store pixel data corresponding to 45 gate lines. If the line memory 111b can store pixel data corresponding to 100 columns of gate lines, the number of lines corresponding to the delay DL2 can be greater than or equal to 45 items are less than 100 items.

In another embodiment, in the long vertical scan pause mode, the touch operation can be performed only during the touch operation sub-period FP2TP1 shown in FIG. 5, but not during the touch operation sub-period corresponding to the vertical leading edge time tVFP2'. FP2TP2 performs touch operation. During the touch operation sub-period FP2TP1, the timing generation circuit 111c can control the touch circuit 114 to (simultaneously) drive (partially or mutually short-circuit connected) touch electrodes 122 in order to sense/detect the touch event.

In one embodiment, the touch operation period FP2TP in Figure 3 corresponds to the vertical leading edge time tVFP2' and the touch operation sub-period FP2TP2 in Figure 5 corresponds to the vertical leading edge time tVFP2', but the invention is not limited thereto. The operation period or touch operation sub-period can also correspond to the vertical trailing edge time.

Synchronize

In one embodiment, in order to synchronize the timing of the internal horizontal synchronization signal Hsync2 with the timing of the external horizontal synchronization signal Hsync1 and the timing of the external vertical synchronization signal Vsync1, the timing generation circuit 111c can perform synchronization operations regularly.

For example, as shown in Figure 4, in the long horizontal scan pause mode, the external horizontal synchronization signal Hsync1 and the internal horizontal synchronization signal Hsync2 can be synchronized at the starting time point (marked by the white arrow) of each time unit , for example, synchronization can be performed once every 20 horizontal periods tL3 of the external horizontal synchronization signal Hsync1.

For example, as shown in Figure 5, in the long vertical scan pause mode, the external horizontal synchronization signal Hsync1 and the internal horizontal synchronization signal Hsync2 can be used during each display operation sub-period (such as display Synchronization is performed at the starting time point (marked by the white arrow) of the operation sub-period FP2DP1). For example, synchronization can be performed every 31 horizontal periods tL2 of the external horizontal synchronization signal Hsync1.

In one embodiment, the vertical leading times tVFP2, tVFP3 or the vertical trailing edges tVFP2, tVBP3 of the frames F2 and F3 of the external horizontal synchronization signal Hsync1 may be respectively equal to the vertical leading times tVFP2', tVFP3' or the vertical trailing edges of the frame period FP2. Time tVBP2', tVBP3'.

In an embodiment, the delay DL2, vertical leading edge time tVFP2 or vertical trailing edge time tVBP2 corresponding to frame F2 may not be equal to or equal to the delay DL3, vertical leading edge time tVFP3 or vertical trailing edge time tVBP3 corresponding to frame F3. Since the touch operation can be performed at the vertical front edge time tVFP2, increasing the vertical front edge time tVFP2 can increase the time length for the touch operation. In an embodiment, the vertical leading edge time tVFP2 of frame F2 may be greater than the vertical leading edge time tVFP3 of frame F3.

In one embodiment, one display operation sub-period (such as the display operation sub-periods FP3DP1~FP3DP10 shown in Figure 4 or the display operation sub-periods FP2DP1~FP2DPn shown in Figure 5) can be used to output the same number of gate lines. corresponding pixel data, so the time length of each display operation sub-period can be equal. Similarly, the touch operation sub-periods (such as the touch operation sub-periods FP3TP1 to FP3TP10 shown in FIG. 4 ) can be used to drive the same number of touch electrodes 122 , so the time length of each touch operation sub-period can be equal. The number (eg, 10) of the touch operation sub-periods (eg, the touch operation sub-periods FP3TP1 to FP3TP10 shown in FIG. 4 ) may be related to the number of rows (or columns) of the touch electrodes 122 .

Same frame rate

In one embodiment, different ones of the long horizontal scan pause mode and the long vertical scan pause mode may be used at the same frame rate. Please refer to Figures 1 and 6. Figure 6 shows an embodiment of the present invention. Sequence diagram.

In one embodiment, the timing generation circuit 111c can be used to determine the horizontal period (such as the horizontal period shown in FIG. 6) of the external horizontal synchronization signal Hsync1 in two consecutive frames (such as the frames F12~F14 shown in FIG. 6). Whether the time lengths of tL12~tL14) are the same. Since the horizontal period tL13 (compared to the horizontal period tL12 ) is longer, the data signal output by FP12 during the frame period can correspond to the long vertical scan pause mode, and the data signal output by FP13 during the frame period can correspond to the long horizontal scan pause mode.

In one embodiment, the frame period FP12 is equal to the frame period FP13, but the touch reporting rate corresponding to the frame period FP2 may not be equal to the touch reporting rate corresponding to the frame period FP3. For example, the frame period FP12 and the frame period FP13 can both be 11.11 milliseconds, so that the frame rates are both 90Hz, but the touch reporting rates can be, for example, 90Hz and 180Hz respectively.

In another embodiment, the microcontroller unit (MCU) (not shown) of the driving circuit 110 can use an algorithm to interpolate the points, so that the touch reporting rate in the long vertical scan pause mode can be different from the frame rate. For example, the frame period FP12 may be 11.11 milliseconds, making the frame rate 90 Hz, but the touch reporting rate may be 180 Hz, for example. In this way, when switching from the long vertical scan pause mode to the long horizontal scan pause mode, the frame rate can be maintained at 90Hz, and the touch reporting rate can be maintained at 180Hz.

Dynamic switching between long vertical scan pause mode and long horizontal scan pause mode

As shown in Figure 2 or Figure 6, it is possible to dynamically switch between the long vertical scan pause mode and the long horizontal scan pause mode. That is to say, in the process of switching from the long vertical scan pause mode to the long horizontal scan pause mode, there is no need to first enter the sleep mode (or the integrated circuit (IC) pause or shut down) from the long vertical scan pause mode, and then End sleep mode (or the integrated circuit resumes or turns on machine) to switch to long horizontal scan pause mode. Therefore, during the process of switching from the long vertical scan pause mode to the long horizontal scan pause mode, the touch display panel 120 will not dim and can continue to display images. That is to say, the frame using the long vertical scan pause mode (for example, frame period FP12) and the frame using the long horizontal scan pause mode (for example, frame period FP13) are two consecutive frames, and the frame using the long vertical scan pause mode (for example, frame period FP13) (The end time point of the frame period FP12) is connected to (the start time point) of the frame using the long horizontal scan pause mode (for example, the frame period FP13). For example, the vertical leading edge time tVFP12' of a frame using a long vertical scan pause mode (e.g., frame period FP12) is connected to the vertical trailing edge time tVBP13' of a frame using a long horizontal scan pause mode (e.g., frame period FP13). ).

In short, in one embodiment, the timing generation circuit 111c can be used to determine whether the time length of the external horizontal synchronization signal Hsync1 in the horizontal periods of two consecutive frames (for example, horizontal periods tL12, tL13) is the same, to determine whether to switch to Long vertical scan pause mode or long horizontal scan pause mode.

In another embodiment, the timing generation circuit 111c can determine whether to switch to the long vertical scan pause mode or the long horizontal scan pause mode by detecting the length of the horizontal period (such as the horizontal period tL12) according to the received external horizontal synchronization signal Hsync1. Scan pause mode. For example, based on the time length of the horizontal period tL12, the data signal output by FP12 during the frame period may correspond to the long vertical scan pause mode. Based on the time length of the horizontal period tL13, the data signal output by FP13 during the frame period may correspond to the long horizontal scan pause mode.

In another embodiment, the timing generation circuit 111c can determine whether to switch to the long vertical scan pause mode or the long horizontal scan pause mode according to the received command. For example, based on the command received by the timing generation circuit 111c, the data signal output by FP12 during the frame period may correspond to the long vertical scan pause mode, and the data signal output by FP13 during the frame period may correspond to the long horizontal scan pause mode.

Figure 7 is a timing diagram of an embodiment of the present invention. In another embodiment, the timing generation circuit 111c can detect the low-power blanking period of the horizontal period (such as the horizontal period tL22, tL23) according to the received external synchronization signal Hsync1 (which can be used to introduce a low-power state). or Low Power interval) BLLP, horizontal sync pulse line period (Horizontal active line, HACT) RGB, horizontal back edge (Horizontal back porch) HBP or horizontal front porch (Horizontal front porch) HFP time length tBLLP, tHACT, tHBP, tHFP, To determine whether to switch to long vertical scan pause mode or long horizontal scan pause mode. Among them, frames F22 and F23 may respectively include vertical synchronization end packet (Vertical Sync End packet) VS, horizontal synchronization start packet (Horizontal Sync Start packet) HS, low power (Low Power Mode) LPM, low power blank period BLLP, and horizontal synchronization pulse line. Periodic RGB, horizontal trailing edge HBP or horizontal leading edge HFP.

In one embodiment, the time length of horizontal periods tL22, tL23, low power blank period BLLP, horizontal synchronization pulse line period RGB, horizontal trailing edge HBP or horizontal leading edge HFP is actually determined by the front-end circuit (not shown in the first (Figure), these time lengths can be known from the video packet stream 100 transmitted by the front-end circuit. In other words, the front-end circuit determines whether the frame rate changes. The timing generation circuit 111c passively performs internal switching (timing switching corresponding to the long vertical scan pause mode or the long horizontal scan pause mode) based on the video packet stream 100 from the front-end circuit.

In one embodiment, the touch display panel 120 may include a display panel for display operations and a touch panel for touch operations. The touch panel can be embedded inside the display panel.

In one embodiment, the driving circuit 110 may include a touch and display driver integrated circuit and/or other driving circuits. The transmission interface may include a mobile industry processor interface (MobileIndustry Processor Interface (MIPI) and/or other transmission interfaces.

For convenience of explanation, each drawing of the present invention is only schematic to make it easier to understand the present invention, and its detailed proportions can be adjusted according to design requirements. "Including" mentioned in the present invention is an open-ended term, so it should be interpreted as "including but not limited to". The "first", "second" and other descriptions mentioned in the present invention are only used to distinguish different components and do not limit their production order or coexistence. The "when" mentioned in the present invention can mean "if", "under the condition of", "immediately when... occurs", "immediately after..." or "after..." ...and after a (tolerable/ignorable) length of time”. Embodiments of the invention may be combined in various ways without conflict.

To sum up, the driving circuit of the present invention can automatically switch between the long horizontal scan pause mode and the long horizontal scan pause mode according to the period corresponding to the received video packet stream, for example, according to whether the time length of the horizontal period of two consecutive frames is the same. Long vertical scan pauses between modes, thus ensuring display quality. The present invention can adopt a long vertical scan pause mode at a high frame rate and a long horizontal scan pause mode at a low frame rate for power saving. Using a long vertical scan pause mode at high frame rates can avoid irrecoverable display stripes on the touch display panel when the horizontal period is short. Using long horizontal scan pause mode and extended horizontal scan pause mode at low frame rates, the vertical blank period will not be too long, thus avoiding flickering and other display abnormality problems. At low frame rates, the long horizontal scan pause mode and the extended horizontal scan pause mode are used. Since the horizontal period is longer, it is easier for the voltage to reach a predetermined level. Moreover, in the present invention, the touch reporting rate corresponding to the high frame rate may be equal to the touch reporting rate corresponding to the low frame rate. The above are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the patentable scope of the present invention shall fall within the scope of the present invention.

122S, 122S1a~122S10b: touch signal

DL2~DL4: Delay

F1~F4: frame

FP1~FP3: frame period

FP2DP: During display operation

FP2TP: During touch operation

FP3DP1~FP3DP10: Display operation sub-period

FP3TP1~FP3TP10: Touch operation sub-period

Hsync1: external horizontal synchronization signal

Hsync2: internal horizontal synchronization signal

tL1~tL3: horizontal period

tVBP2, tVBP3, tVBP2’, tVBP3’: vertical trailing edge time

tVFP2,tVFP3,tVFP2’,tVFP3’: vertical leading edge time

Vsync1: external vertical synchronization signal

Claims (20)

A timing control circuit includes: a receiving circuit; and a line memory coupled to the receiving circuit, wherein the line memory is used to: output a first data signal during a first frame period; and during a second frame period Output a second data signal, wherein the end time point of the first frame period coincides with the starting time point of the second frame period, wherein one of the first data signal and the second data signal corresponds to a long Horizontal scan pause mode, the other one of the first data signal and the second data signal corresponds to a long vertical scan pause mode. The timing control circuit of claim 1, wherein the receiving circuit is used to: receive a first external signal, wherein the first external signal corresponds to a first cycle; and receive a second external signal, wherein the The second external signal corresponds to a second period. The first period and the second period are not equal. The first period and the second period are both a horizontal period, a horizontal synchronization pulse line period, a low-power blank period, and a horizontal trailing edge. or horizontal front. The timing control circuit as described in claim 1, wherein the receiving circuit is used to: receive a second external signal, wherein the second external signal corresponds to a second period, wherein based on the second period, the second The data signal corresponds to the long vertical scan pause mode or the long horizontal scan pause mode. The timing control circuit according to claim 1, wherein the first frame period based on the first data signal is greater than the second frame period of the second data signal. period, the first data signal corresponds to the long horizontal scan pause mode, wherein based on the first frame period of the first data signal being smaller than the second frame period of the second data signal, the first data signal corresponds to the long horizontal scan pause mode. Vertical scan pause mode. The timing control circuit as described in claim 1, wherein the first frame period of the first data signal is not equal to the second frame period of the second data signal, and a first touch corresponding to the first frame period The touch reporting rate is equal to a second touch reporting rate corresponding to the second frame period. The timing control circuit of claim 1, wherein one of the first data signal and the second data signal corresponds to the long horizontal scan pause mode and an extended horizontal scan pause mode. The timing control circuit of claim 1, wherein the receiving circuit is used to: receive a first external signal, wherein the first external signal corresponds to a first period, the first data signal and the first external signal There is a first delay, the first delay is proportional to the first period; and receiving a second external signal, wherein the second external signal corresponds to a second period, the first data signal and the second There is a second delay between the external signals, the second delay is proportional to the second period, and the first delay is not equal to the second delay. The timing control circuit of claim 7, wherein the ratio between the first delay and the second delay is equal to the ratio between the first period and the second period. The timing control circuit as described in claim 1, wherein the first data signal of the first data signal A frame period is equal to the second frame period of the second data signal, and a first touch reporting rate corresponding to the first data signal is not equal to a second touch reporting rate corresponding to the second data signal. The timing control circuit of claim 1, wherein a first vertical leading edge time corresponding to the first data signal is not equal to a second vertical leading edge time corresponding to the first data signal. A timing control method includes: outputting a first data signal during a first frame period; and outputting a second data signal during a second frame period, wherein the end time point of the first frame period is the same as the second frame period. The starting time point of the period coincides, wherein one of the first data signal and the second data signal corresponds to a long horizontal scan pause mode, and the other of the first data signal and the second data signal corresponds to a long horizontal scan pause mode. Vertical scan pause mode. The timing control method according to claim 11, further comprising: receiving a first external signal, wherein the first external signal corresponds to a first period; and receiving a second external signal, wherein the second external signal corresponds to a second period, the first period and the second period are not equal, and the first period and the second period are both a horizontal period, a horizontal synchronization pulse line period, a low-power blank period, a horizontal trailing edge or a horizontal leading edge; wherein , based on the time length difference between the first period and the second period, the first data signal and the second data signal respectively correspond to different ones of the long horizontal scan pause mode and the long vertical scan pause mode. The timing control method as described in claim 11, further comprising: receiving a second external signal, wherein the second external signal corresponds to a second period, wherein based on the second period, the second data signal corresponds to the long vertical scan pause mode or the long horizontal scan pause mode. The timing control method as described in claim 11, wherein based on the first frame period of the first data signal being greater than the second frame period of the second data signal, the first data signal corresponds to the long horizontal scan pause mode , wherein based on the first frame period of the first data signal being smaller than the second frame period of the second data signal, the first data signal corresponds to the long vertical scan pause mode. The timing control method according to claim 11, wherein the first frame period of the first data signal is not equal to the second frame period of the second data signal, and the first frame period corresponds to a first touch The touch reporting rate is equal to a second touch reporting rate corresponding to the second frame period. The timing control method of claim 11, wherein one of the first data signal and the second data signal corresponds to the long horizontal scan pause mode and an extended horizontal scan pause mode. The timing control method according to claim 11, further comprising: receiving a first external signal, wherein the first external signal corresponds to a first period, and there is a first data signal between the first data signal and the first external signal. a delay, the first delay being proportional to the first period; and receiving a second external signal, wherein the second external signal corresponds to a second period, the first data There is a second delay between the signal and the second external signal, the second delay is proportional to the second period, and the first delay and the second delay are not equal. The timing control method according to claim 17, wherein the ratio between the first delay and the second delay is equal to the ratio between the first period and the second period. The timing control method according to claim 11, wherein the first frame period of the first data signal is equal to the second frame period of the second data signal, and a first touch corresponding to the first data signal The reporting rate is not equal to a second touch reporting rate corresponding to the second data signal. The timing control method of claim 11, wherein a first vertical leading edge time corresponding to the first data signal is not equal to a second vertical leading edge time corresponding to the first data signal.