TWI813580B - Printed circuit board - Google Patents
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- TWI813580B TWI813580B TW107125939A TW107125939A TWI813580B TW I813580 B TWI813580 B TW I813580B TW 107125939 A TW107125939 A TW 107125939A TW 107125939 A TW107125939 A TW 107125939A TW I813580 B TWI813580 B TW I813580B
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- insulating layer
- metal
- circuit board
- conductive member
- printed circuit
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 335
- 239000002184 metal Substances 0.000 claims abstract description 335
- 238000002844 melting Methods 0.000 claims abstract description 67
- 230000008018 melting Effects 0.000 claims abstract description 67
- 229920000106 Liquid crystal polymer Polymers 0.000 claims description 7
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 claims description 7
- 229920000089 Cyclic olefin copolymer Polymers 0.000 claims description 6
- 229920001955 polyphenylene ether Polymers 0.000 claims description 6
- 229920001343 polytetrafluoroethylene Polymers 0.000 claims description 6
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- 150000002739 metals Chemical class 0.000 claims description 4
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- 230000000149 penetrating effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 175
- 239000011888 foil Substances 0.000 description 25
- 238000000034 method Methods 0.000 description 23
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- 239000003822 epoxy resin Substances 0.000 description 14
- 229920000647 polyepoxide Polymers 0.000 description 14
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- 238000004519 manufacturing process Methods 0.000 description 10
- 239000010949 copper Substances 0.000 description 9
- 238000005530 etching Methods 0.000 description 8
- 239000011810 insulating material Substances 0.000 description 8
- 238000007639 printing Methods 0.000 description 7
- 239000000758 substrate Substances 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 229910000765 intermetallic Inorganic materials 0.000 description 6
- 238000003475 lamination Methods 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 239000011347 resin Substances 0.000 description 5
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- 239000002356 single layer Substances 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
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- 238000009713 electroplating Methods 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- UFWIBTONFRDIAS-UHFFFAOYSA-N Naphthalene Chemical compound C1=CC=CC2=CC=CC=C21 UFWIBTONFRDIAS-UHFFFAOYSA-N 0.000 description 2
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- PXKLMJQFEQBVLD-UHFFFAOYSA-N bisphenol F Chemical compound C1=CC(O)=CC=C1CC1=CC=C(O)C=C1 PXKLMJQFEQBVLD-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
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- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- QTWJRLJHJPIABL-UHFFFAOYSA-N 2-methylphenol;3-methylphenol;4-methylphenol Chemical compound CC1=CC=C(O)C=C1.CC1=CC=CC(O)=C1.CC1=CC=CC=C1O QTWJRLJHJPIABL-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229930003836 cresol Natural products 0.000 description 1
- 239000011353 cycloaliphatic epoxy resin Substances 0.000 description 1
- 229920001971 elastomer Polymers 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- 239000011256 inorganic filler Substances 0.000 description 1
- 229910003475 inorganic filler Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000004843 novolac epoxy resin Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 229920005992 thermoplastic resin Polymers 0.000 description 1
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- 229910052719 titanium Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0137—Materials
- H05K2201/015—Fluoropolymer, e.g. polytetrafluoroethylene [PTFE]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Abstract
Description
以下說明是有關於一種印刷電路板。 The following instructions are for a printed circuit board.
製造印刷電路板的方式有平行構成式層疊(parallel build up lamination)及漸成式層疊(sequential lamination)。平行構成式層疊包括高溫按壓,而漸成式層疊包括低溫按壓。當採用平行構成式層疊方法時,可使用糊膏(paste)作為單元層間連接結構。在此種情形中,內部配線與糊膏之間的黏合及連接性可能劣化。 The methods of manufacturing printed circuit boards include parallel build up lamination and sequential lamination. Parallel build-up lamination involves high-temperature pressing, while incremental build-up involves low-temperature pressing. When a parallel structure stacking method is adopted, paste can be used as the inter-unit layer connection structure. In this case, the adhesion and connectivity between the internal wiring and the paste may deteriorate.
日本公開專利第2003-179356號闡述一種印刷電路板的實例。 Japanese Patent Publication No. 2003-179356 describes an example of a printed circuit board.
本發明的目標是提供一種具有極佳層間黏合的印刷電路板。 The object of the present invention is to provide a printed circuit board with excellent interlayer adhesion.
根據本發明的態樣,提供一種印刷電路板,其包括:絕緣層,絕緣層的下表面中嵌置有金屬接墊;開口部分,穿過絕緣層且形成於金屬接墊的上表面上;金屬凸塊,形成於開口部分中且具有突出於絕緣層的上表面上方的上表面;以及導電構件,形 成於金屬接墊的下表面上,其中導電構件的熔點低於金屬凸塊的熔點,其中金屬接墊的下表面凹陷超過絕緣層的下表面。 According to an aspect of the present invention, a printed circuit board is provided, which includes: an insulating layer with a metal pad embedded in the lower surface of the insulating layer; an opening portion passing through the insulating layer and formed on the upper surface of the metal pad; a metal bump formed in the opening portion and having an upper surface protruding above an upper surface of the insulating layer; and a conductive member shaped formed on the lower surface of the metal pad, wherein the melting point of the conductive component is lower than the melting point of the metal bump, and the lower surface of the metal pad is recessed beyond the lower surface of the insulating layer.
根據本發明的另一態樣,提供一種印刷電路板,其包括:第一絕緣層,其下表面中嵌置有第一金屬接墊;第一開口部分,穿過第一絕緣層且形成於第一金屬接墊的上表面上;第一金屬凸塊,形成於第一開口部分中;第二絕緣層,層疊於第一絕緣層上且形成於第一金屬凸塊上;以及導電構件,形成於第二金屬接墊的下表面上且接觸第一金屬凸塊的側表面。 According to another aspect of the present invention, a printed circuit board is provided, which includes: a first insulating layer with a first metal pad embedded in its lower surface; a first opening portion passing through the first insulating layer and formed in on the upper surface of the first metal pad; a first metal bump formed in the first opening portion; a second insulating layer stacked on the first insulating layer and formed on the first metal bump; and a conductive member, Formed on the lower surface of the second metal pad and contacting the side surface of the first metal bump.
10、20、30:單元基板 10, 20, 30: unit substrate
100、200:絕緣層 100, 200: Insulation layer
110、210:金屬接墊 110, 210: Metal pad
110’、111’:空間 110’, 111’: space
111、211:電路 111, 211: Circuit
120、220:開口部分 120, 220: opening part
130、230:金屬凸塊 130, 230: Metal bumps
131、231:高熔點凸塊 131, 231: High melting point bumps
132、232:低熔點凸塊 132, 232: Low melting point bumps
300:凹陷 300:dent
P1、P2、P3、P4:導電構件 P1, P2, P3, P4: conductive components
C0:絕緣材料 C0: Insulating material
C1:載體金屬箔 C1: Carrier metal foil
C2:晶種金屬箔 C2: Seed metal foil
R:抗蝕劑膜 R: Resist film
M:遮罩 M: mask
圖1示出根據本發明第一實施例的印刷電路板。 Figure 1 shows a printed circuit board according to a first embodiment of the invention.
圖2示出根據本發明第二實施例的印刷電路板。 Figure 2 shows a printed circuit board according to a second embodiment of the invention.
圖3示出根據本發明第三實施例的印刷電路板。 Figure 3 shows a printed circuit board according to a third embodiment of the invention.
圖4示出根據本發明第四實施例的印刷電路板。 Figure 4 shows a printed circuit board according to a fourth embodiment of the invention.
圖5示出根據本發明第五實施例的印刷電路板。 Figure 5 shows a printed circuit board according to a fifth embodiment of the invention.
圖6至圖9是示出製造根據本發明實施例的印刷電路板的方法中所使用的各製程的剖視圖。 6 to 9 are cross-sectional views illustrating various processes used in a method of manufacturing a printed circuit board according to an embodiment of the present invention.
圖10至圖11是示出製造根據本發明另一實施例的印刷電路板的方法中所使用的各製程的剖視圖。 10 to 11 are cross-sectional views illustrating various processes used in a method of manufacturing a printed circuit board according to another embodiment of the present invention.
圖12至圖14是示出製造根據本發明又一實施例的印刷電路板的方法中所使用的各製程的剖視圖。 12 to 14 are cross-sectional views illustrating various processes used in a method of manufacturing a printed circuit board according to yet another embodiment of the present invention.
在所有圖式及詳細說明通篇中,相同的參考編號指代相同的 元件。各圖式可能並非按比例繪製,且為清晰、示出及方便起見,可誇大圖式中的元件的相對大小、比例及繪示。 Throughout the drawings and detailed description, the same reference numbers refer to the same element. The drawings may not be drawn to scale, and the relative sizes, proportions, and illustrations of elements in the drawings may be exaggerated for clarity, illustration, and convenience.
提供以下詳細說明是為了幫助讀者獲得對本文中所述方法、設備及/或系統的全面理解。然而,對於此項技術中具有通常知識者而言,本文中所述方法、設備及/或系統的各種改變、潤飾及等效形式將顯而易見。本文中所述操作順序僅為實例,且並非僅限於本文中所提及的該些操作順序,而是如對於此項技術中具有通常知識者而言將顯而易見,除必定以特定次序出現的操作以外,均可有所改變。此外,為提高清晰性及明確性,可省略對對於此項技術中具有通常知識者而言眾所習知的功能及構造的說明。 The following detailed description is provided to assist the reader in obtaining a comprehensive understanding of the methods, apparatus, and/or systems described herein. However, various modifications, modifications, and equivalents of the methods, apparatus, and/or systems described herein will be apparent to those of ordinary skill in the art. The sequences of operations described herein are examples only, and are not limited to those mentioned herein, but as will be apparent to one of ordinary skill in the art, except for operations that necessarily occur in a specific order. Other than that, it can be changed. In addition, descriptions of functions and constructions that are well known to those of ordinary skill in the art may be omitted to enhance clarity and clarity.
本文中所述特徵可被實施為不同形式,且不應被解釋為僅限於本文中所述實例。確切而言,提供本文中所述實例是為了使此揭露內容將透徹及完整,並將向此項技術中具有通常知識者傳達本發明的全部範圍。 Features described herein may be implemented in different forms and should not be construed as limited to the examples set forth herein. Rather, the examples described herein are provided so that this disclosure will be thorough and complete, and will convey the full scope of the invention to those skilled in the art.
除非另有定義,否則本文中所使用的全部用語(包括技術用語及科學用語)的含義均與其被本發明所屬技術中具有通常知識者所通常理解的含義相同。在常用字典中所定義的任何用語應被解釋為具有與在相關技術的上下文中的含義相同的含義,且除非另有明確定義,否則不應將其解釋為具有理想化或過於正式的含義。 Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Any term defined in a commonly used dictionary shall be construed to have the same meaning as in the context of the relevant technology and shall not be construed to have an idealized or overly formal meaning unless otherwise expressly defined.
無論圖號如何,將對相同的或對應的組件給定相同的參考編號,且將不再對相同的或對應的組件予以贅述。在本發明的說明通篇中,當闡述特定相關傳統技術確定與本發明的觀點無關時,將省略有關詳細說明。在闡述各種組件時可使用例如「第一(first)」及「第二(second)」等用語,但以上組件不應僅限於以上用語。以上用語僅用於區分各個組件。在附圖中,可誇大、省略或簡要示出一些組件,且組件的尺寸未必反映該些組件的實際尺寸。 Regardless of the figure number, the same or corresponding components will be given the same reference numbers and will not be described again. Throughout the description of the present invention, when specific related conventional techniques are described that are determined to be irrelevant to the viewpoint of the present invention, the relevant detailed description will be omitted. Terms such as "first" and "second" may be used when describing various components, but the above components should not be limited to the above terms. The above terms are only used to distinguish between the various components. In the drawings, some components may be exaggerated, omitted, or simplified, and the sizes of components do not necessarily reflect the actual sizes of the components.
在下文中,將參照附圖來詳細闡述本發明的特定實施例。 Hereinafter, specific embodiments of the invention will be explained in detail with reference to the accompanying drawings.
圖1示出根據本發明第一實施例的印刷電路板。 Figure 1 shows a printed circuit board according to a first embodiment of the invention.
參照圖1,根據本發明第一實施例的印刷電路板包括上面形成有金屬接墊110的絕緣層100、形成於絕緣層100中的開口部分120、形成於開口部分120中的金屬凸塊及形成於金屬接墊110的下表面上的導電構件P1。
Referring to FIG. 1 , a printed circuit board according to a first embodiment of the present invention includes an
絕緣層100是由例如樹脂等絕緣材料製成。絕緣層100的樹脂可由例如熱固性樹脂及熱塑性樹脂等各種材料製成。
The
絕緣層100可由具有低介電常數(Dk)及低介電損耗(Df)的材料製成。具體而言,絕緣層100可由液晶聚合物(liquid crystal polymer,LCP)、聚四氟乙烯(polytetrafluoroethylene,PTFE)、聚苯醚(polyphenylene ether,PPE)、環烯烴聚合物(cyclo olefin polymer,COP)及聚氟烷氧基(polyfluoroalkoxy,PFA)中
的至少一者形成。此種材料適合於減少用於傳輸高頻訊號的基板中的訊號損耗。
The
然而,絕緣層100並非僅限於以上材料,且可由環氧樹脂或聚醯亞胺等形成。環氧樹脂的實例包括萘環氧樹脂(naphthalene epoxy resin)、雙酚A型環氧樹脂(bisphenol A type epoxy resin)、雙酚F型環氧樹脂(bisphenol F type epoxy resin)、酚醛清漆環氧樹脂(novolac epoxy resin)、甲酚酚醛清漆環氧樹脂(cresol novolak epoxy resin)、橡膠改質環氧樹脂(rubber modified epoxy resin)、脂環族環氧樹脂(cycloaliphatic epoxy resin)、矽系環氧樹脂(silicon-based epoxy resin)、氮系環氧樹脂(nitrogen-based epoxy resin)、磷系環氧樹脂(phosphorus-based epoxy resin)等。然而,其並非僅限於此。
However, the
絕緣層100可為將例如玻璃布(glass cloth)等纖維加強材料(fiber reinforcement material)包含於樹脂中的預浸體(prepreg,PPG)。絕緣層100可為將例如二氧化矽(silica)等無機填料填充於樹脂中的構成膜。可使用味之素構成膜(ajinomoto build-up film,ABF)等作為此種構成膜。
The
絕緣層100可由例如感光成像介電(photoimageable dielectric,PID)等感光性材料形成。
The
絕緣層100上形成有電路111及金屬接墊110。具體而言,電路111及金屬接墊110可嵌置於絕緣層100的下表面中。電路111是被圖案化以傳輸電性訊號的導體。金屬接墊110是連
接至電路111的端部的導體。電路111及金屬接墊110是由例如銅(Cu)、鈀(Pd)、鋁(Al)、鎳(Ni)、鈦(Ti)、金(Au)、鉑(Pt)或其合金等金屬形成。
金屬接墊110的下表面凹陷超過絕緣層100的下表面。金屬接墊110的下表面相較於絕緣層100的下表面而言進入絕緣層100內部。因此,在金屬接墊110的下表面與絕緣層100的下表面之間形成台階高度(step-height),且金屬接墊110的下表面與絕緣層100提供預定空間(參見圖7中的110’)。
The lower surface of the
電路111的下表面亦可凹陷超過絕緣層100的下表面。亦即,電路111的下表面相較於絕緣層100的下表面而言進入絕緣層100內部。因此,在電路111的下表面與絕緣層100的下表面之間形成台階高度,且電路111的下表面與絕緣層100可提供預定空間(參見圖7中的111’)。
The lower surface of the
開口部分120形成於絕緣層100中。開口部分120被形成為穿過絕緣層100以位於金屬接墊110的上表面上。開口部分120形成於金屬接墊110的上表面上,以使金屬接墊110的上表面的至少一部分經由開口部分120暴露出。開口部分120可形成為圓柱形。
The
金屬凸塊130形成於開口部分120中。金屬凸塊130的上表面可突出於絕緣層100的上表面上方。
Metal bumps 130 are formed in the
金屬凸塊130可形成為兩個層。在此種情形中,金屬凸塊130可包括高熔點凸塊131及低熔點凸塊132。高熔點凸塊131
是由熔點相對高於低熔點凸塊132的金屬製成的凸塊,而低熔點凸塊132是由熔點相對低於高熔點凸塊131的金屬製成的凸塊。例如,分別而言,高熔點凸塊131可由包括銅的金屬製成,而低熔點凸塊132可由包括錫的金屬製成。
Metal bumps 130 may be formed in two layers. In this case, the metal bumps 130 may include high melting point bumps 131 and low melting point bumps 132 . High
低熔點凸塊132可位於高熔點凸塊131上方,且低熔點凸塊132的厚度可小於高熔點凸塊131的厚度。高熔點凸塊131的上表面可位於絕緣層100的上表面之下,且低熔點凸塊132的上表面可位於絕緣層100的上表面上方。亦即,金屬凸塊130的上表面突出於絕緣層100的上表面上方,且高熔點凸塊131與低熔點凸塊132之間的介面可位於絕緣層100的上表面之下。
The low
導電構件P1形成於金屬接墊110的下表面上,金屬接墊110的下表面凹陷超過絕緣層100的下表面。亦即,導電構件P1可形成於由金屬接墊110的下表面與絕緣層100形成的空間110’中。導電構件P1可藉由金屬接墊110的下表面與絕緣層100的下表面之間的台階高度而形成。在此種情形中,導電構件P1的下表面可位於與絕緣層100的下表面相同的平面上。
The conductive member P1 is formed on the lower surface of the
導電構件P1可包含例如銅(Cu)、錫(Sn)及銀(Ag)等金屬。具體而言,導電構件P1可為含有金屬的糊膏。然而,其並非僅限於該些材料。可使用具有導電性的任何材料。形成導電構件P1的金屬可與形成低熔點凸塊132的金屬相同。
The conductive member P1 may include metals such as copper (Cu), tin (Sn), and silver (Ag). Specifically, the conductive member P1 may be a paste containing metal. However, it is not limited to these materials. Any material that is electrically conductive can be used. The metal forming the conductive member P1 may be the same metal as the metal forming the low
導電構件P1的熔點可低於金屬接墊110的熔點,可低於高熔點凸塊131的熔點,且可等於或低於低熔點凸塊132的熔
點。
The melting point of the conductive member P1 may be lower than the melting point of the
導電構件P1可更形成於電路111的下表面上,電路111的下表面凹陷超過絕緣層100的下表面。亦即,導電構件P1可形成於由電路111的下表面與絕緣層100形成的空間111’中。導電構件P1可藉由電路111的下表面與絕緣層100的下表面之間的台階高度而形成。在此種情形中,導電構件P1的下表面可位於與絕緣層100的下表面相同的平面上。
The conductive member P1 may be further formed on a lower surface of the
根據本發明第一實施例的印刷電路板可為多層式印刷電路板。多層式印刷電路板包括多個絕緣層100及200、電路111及211、金屬接墊110及210、開口部分120、220、金屬凸塊130、230、導電構件P1、P2等。將對此予以詳細闡述。
The printed circuit board according to the first embodiment of the present invention may be a multi-layer printed circuit board. The multilayer printed circuit board includes a plurality of insulating
根據本發明第一實施例的印刷電路板可包括上面形成有第一金屬接墊110的第一絕緣層100、上面形成有第二金屬接墊210的第二絕緣層200、形成於絕緣層100中的第一開口部分120、形成於第二絕緣層200中的第二開口部分220、形成於第一開口部分120中的第一金屬凸塊130、形成於第二開口部分220中的第二金屬凸塊230及形成於第二金屬接墊210的下表面上的導電構件P2。
The printed circuit board according to the first embodiment of the present invention may include a first insulating
第一絕緣層100及第二絕緣層200與上述絕緣層相同。第一絕緣層100與第二絕緣層200可由相同的材料形成,且第二絕緣層200可堆疊於第一絕緣層100上。
The
第一電路111及第一金屬接墊110嵌置於第一絕緣層
100的下表面中。另外,第二電路211及第二金屬接墊210嵌置於第二絕緣層200的下表面中。因此,第二電路211的下表面及第二金屬接墊210的下表面位於第一絕緣層100與第二絕緣層200之間的介面處。
The
第二金屬接墊210的下表面凹陷超過第二絕緣層200的下表面。第二金屬接墊210的下表面相較於第二絕緣層200的下表面而言進入第二絕緣層200內部。因此,在第二金屬接墊210的下表面與第二絕緣層200的下表面之間形成台階高度。金屬接墊210的下表面與第二絕緣層200提供預定空間。
The lower surface of the
第二電路211的下表面亦可凹陷超過第二絕緣層200的下表面。亦即,第二電路211的下表面相較於第二絕緣層200的下表面而言進入第二絕緣層200內部。因此,在第二電路211的下表面與第二絕緣層200的下表面之間形成台階高度。第二電路211的下表面與第二絕緣層200提供預定空間。
The lower surface of the
必要時,第一金屬接墊110的下表面可凹陷超過第一絕緣層100的下表面。第一金屬接墊110的下表面相較於第一絕緣層100的下表面而言進入第一絕緣層100內部。因此,在第一金屬接墊110的下表面與第一絕緣層100的下表面之間形成台階高度。第一金屬接墊110的下表面與第一絕緣層100提供預定空間。
If necessary, the lower surface of the
第一電路111的下表面亦可凹陷超過第一絕緣層100的下表面。亦即,第一電路11的下表面相較於第一絕緣層100的下表面而言進入第一絕緣層100內部。在第一電路111的下表面與
第一絕緣層100的下表面之間形成台階高度,且第一電路111的下表面與第一絕緣層100提供預定空間。
The lower surface of the
第一開口部分120穿過第一絕緣層100形成於第一金屬接墊110的上表面上,且第二開口部分220穿過第二絕緣層200形成於第二金屬接墊210的上表面上。第一開口部分120與第二開口部分220被設置成彼此重疊。第一開口部分120與第二開口部分220彼此重疊此一事實意指當在同一平面上進行虛擬投影時第一開口部分120與第二開口部分220彼此重疊。較佳地,第一開口部分120與第二開口部分220可被排列成一行,以使第一開口部分120的中心與第二開口部分220的中心彼此重合。
The
第一金屬凸塊130形成於第一開口部分120中,且第二金屬凸塊230形成於第二開口部分220中。第一金屬凸塊130及第二金屬凸塊230與上述金屬凸塊無異。當第一開口部分120與第二開口部分220被形成為彼此重疊時,第一金屬凸塊130與第二金屬凸塊230亦被形成為彼此重疊。
The
導電構件P2可形成於第二金屬接墊210的下表面上以執行層間結合。此與上述導電構件P1無異。
The conductive member P2 may be formed on the lower surface of the
亦即,導電構件P2的熔點可低於第二金屬接墊210的熔點,低於高熔點凸塊231的熔點,且等於或低於低熔點凸塊232的熔點。
That is, the melting point of the conductive member P2 may be lower than the melting point of the
導電構件P2可包含例如銅(Cu)、錫(Sn)及銀(Ag)等金屬,且具體而言,導電構件P2可為含有金屬的糊膏。然而,
材料並非僅限於該些材料,且可使用具有導電性的任何材料。導電構件P2中所含有的金屬可與低熔點凸塊232中所含有的金屬相同。
The conductive member P2 may include metals such as copper (Cu), tin (Sn), and silver (Ag), and specifically, the conductive member P2 may be a metal-containing paste. However,
The material is not limited to these materials, and any material having conductivity may be used. The metal contained in the conductive member P2 may be the same as the metal contained in the low
導電構件P2可形成於第二金屬接墊210的下表面上,第二金屬接墊210的下表面凹陷超過第二絕緣層200的下表面。第一金屬凸塊130突出超過第一絕緣層100的上表面,且第一金屬凸塊130的突出的上部部分可凹陷至在第二金屬接墊210的下表面上形成的導電構件P2中。導電構件P2可因此接觸第一金屬凸塊130的側表面。導電構件P2與第一金屬凸塊130彼此接觸的區域中形成有金屬間化合物(intermetallic compound,IMC)。
The conductive member P2 may be formed on the lower surface of the
導電構件P2形成於第二金屬接墊210的整個下表面上,以使導電構件P2可設置於第一金屬凸塊130的上表面與第二金屬接墊210的下表面之間以及第一金屬凸塊130的側表面上。
The conductive member P2 is formed on the entire lower surface of the
由金屬凸塊與導電構件構成的結合結構可重覆地形成於多個絕緣層中。換言之,儘管以上說明中闡述了第一絕緣層100及第二絕緣層200,然而印刷電路板可包括三個或更多個絕緣層。此亦適用於彼此相鄰的至少兩個絕緣層。
The bonding structure composed of metal bumps and conductive members can be repeatedly formed in multiple insulating layers. In other words, although the first insulating
導電構件P1可形成於第一金屬接墊110的下表面上,第一金屬接墊110的下表面凹陷超過第一絕緣層100的下表面。此種導電構件P1可設置於堆疊於第一絕緣層100下方的另一絕緣層的金屬凸塊上。
The conductive member P1 may be formed on the lower surface of the
視需要,導電構件P3及P4亦可形成於第一電路111的
下表面上及第二電路211的下表面上。導電構件P3及P4可形成於電路111及211的下表面的整個部分或一部分上。
If necessary, the conductive members P3 and P4 may also be formed on the
圖2示出根據本發明第二實施例的印刷電路板。 Figure 2 shows a printed circuit board according to a second embodiment of the invention.
參照圖2,根據本發明第二實施例的印刷電路板包括上面形成有第一金屬接墊110的第一絕緣層100、上面形成有第二金屬接墊210的第二絕緣層200、形成於第一絕緣層100中的第一開口部分120、形成於第二絕緣層200中的第二開口部分220、形成於第一開口部分120中的第一金屬凸塊130、形成於第二開口部分220中的第二金屬凸塊230及形成於第二金屬接墊210的下表面上的導電構件P2。
2 , a printed circuit board according to a second embodiment of the present invention includes a first insulating
在根據本發明第二實施例的印刷電路板中,導電構件P2接觸第一金屬凸塊130的側表面的預定區域或更多區域。此處,導電構件P2環繞第一金屬凸塊130的側表面的一部分或整個部分。「預定區域」可為第一金屬凸塊130位於由第二金屬接墊210的下表面與第二絕緣層200的下表面界定的空間中的區域。亦即,導電構件P2可接觸第一金屬凸塊130超過第一絕緣層100與第二絕緣層200之間的邊界的側表面。具體而言,當第一絕緣層100與第一金屬凸塊130的側表面之間存在間隙且第一絕緣層100及第二絕緣層200被按壓及層疊時,導電構件P2可流動至間隙中且因此,導電構件P2可覆蓋第一金屬凸塊130的側表面的整體的預定區域或更多區域。較佳地,導電構件P2可覆蓋第一金屬凸塊130的整體。導電構件P2與第一金屬凸塊130彼此接觸的區域中形成
有金屬間化合物(IMC)。導電構件P2與第一金屬凸塊130之間的接觸區域越大,則黏合越強。
In the printed circuit board according to the second embodiment of the present invention, the conductive member P2 contacts a predetermined area or more areas of the side surface of the
另外,可存在第二金屬接墊210中不形成導電構件P2的區。導電構件P2可不形成於除其中第一金屬凸塊130接觸第二金屬接墊210的下表面的中心區以外的區中。然而,在第二實施例中,不排除如圖4中所示導電構件P2形成於第二金屬接墊210的整個下表面上的情形。
In addition, there may be a region in the
必要時,導電構件P2可藉由改變第一絕緣層100及第二絕緣層200的層疊條件而不位於第一金屬凸塊130的上表面與第二金屬接墊210的下表面之間。亦即,第一金屬凸塊130的上表面可接觸第二金屬接墊210的下表面。
If necessary, the conductive member P2 can be prevented from being located between the upper surface of the
舉例而言,若間隙的體積大或者第一金屬凸塊130朝向第二金屬接墊210一側的壓力相對高,則導電構件P2中的所有者流動至間隙中,導電構件P2可不位於第一金屬凸塊130的上表面與第二金屬接墊210的下表面之間。此處,導電構件P2與第二金屬接墊210的下表面之間的接觸區域可等於導電構件P2的厚度。
For example, if the volume of the gap is large or the pressure of the side of the
第一金屬凸塊130的上表面接觸第二金屬接墊210的下表面,且導電構件P2可形成於第二金屬接墊210的下表面中除與第一金屬凸塊130接觸的區以外的部位。亦即,導電構件P2可形成於第二金屬接墊210的不接觸第一金屬凸塊130的下表面上。
The upper surface of the
圖3示出根據本發明第三實施例的印刷電路板。 Figure 3 shows a printed circuit board according to a third embodiment of the invention.
參照圖3,根據本發明第三實施例的印刷電路板包括上
面形成有第一金屬接墊110的第一絕緣層100、上面形成有第二金屬接墊210的第二絕緣層200、形成於第一絕緣層100中的第一開口部分120、形成於第二絕緣層200中的第二開口部分220、形成於第一開口部分120中的第一金屬凸塊130、形成於第二開口部分220中的第二金屬凸塊230及形成於第二金屬接墊210的下表面上的導電構件P2。
Referring to Figure 3, a printed circuit board according to a third embodiment of the present invention includes an upper
The first insulating
在根據本發明第三實施例的印刷電路板中,導電構件P2可延伸至第二金屬接墊210的側表面以覆蓋第二金屬接墊210的側表面。當第二金屬接墊210與第二絕緣層200之間存在間隙時,此可為導電構件P2流動至所述間隙中的結果。
In the printed circuit board according to the third embodiment of the present invention, the conductive member P2 may extend to the side surface of the
導電構件P2可覆蓋第一金屬凸塊130的側表面的預定區域或更多區域,且亦覆蓋第二金屬接墊210的側表面。另外,導電構件P2可自第一金屬凸塊130的側表面連續形成至第二金屬接墊210的側表面。導電構件P2接觸第一金屬凸塊130及第二金屬接墊210的區域中形成有金屬間化合物(IMC)。導電構件P2與第一金屬凸塊130之間的接觸區域越大,則黏合越強。
The conductive member P2 may cover a predetermined area or more areas of the side surface of the
必要時,導電構件P2可藉由改變第一絕緣層100及第二絕緣層200的層疊條件而不位於第一金屬凸塊130的上表面與第二金屬接墊210的下表面之間。亦即,第一金屬凸塊130的上表面可接觸第二金屬接墊210的下表面。舉例而言,若間隙的體積大或者第一金屬凸塊130朝向第二金屬接墊210一側的壓力相對高,則導電構件P2中的所有者流動至間隙中,導電構件P2可
不位於第一金屬凸塊130的上表面與第二金屬接墊210的下表面之間。
If necessary, the conductive member P2 can be prevented from being located between the upper surface of the
圖4示出根據本發明第四實施例的印刷電路板。 Figure 4 shows a printed circuit board according to a fourth embodiment of the invention.
參照圖4,根據本發明第四實施例的印刷電路板包括上面形成有第一金屬接墊110的第一絕緣層100、上面形成有第二金屬接墊210的第二絕緣層200、形成於第一絕緣層100中的第一開口部分120、形成於第二絕緣層200中的第二開口部分220、形成於第一開口部分120中的第一金屬凸塊130、形成於第二開口部分220中的第二金屬凸塊230及形成於第二金屬接墊210的下表面上的導電構件P2。
4 , a printed circuit board according to a fourth embodiment of the present invention includes a first insulating
在根據本發明第四實施例的印刷電路板中,金屬凸塊130可形成為單個層。在此種情形中,金屬凸塊130可由例如銅等金屬製成。亦即,第一金屬凸塊130與第二金屬凸塊230可各自形成為單個層。
In the printed circuit board according to the fourth embodiment of the present invention, the
在此種情形中,導電構件P2的位置並不限於如圖4中所示者,而是可被替換為第一實施例至第三實施例中所述的導電構件P2的位置。 In this case, the position of the conductive member P2 is not limited to that shown in FIG. 4 , but may be replaced with the position of the conductive member P2 described in the first to third embodiments.
圖5示出根據本發明第五實施例的印刷電路板。 Figure 5 shows a printed circuit board according to a fifth embodiment of the invention.
參照圖5,根據本發明第五實施例的印刷電路板包括上面形成有金屬接墊110的絕緣層100、形成於絕緣層100中的開口部分120、形成於開口部分120中的金屬凸塊130及形成於金屬接墊110的下表面上的導電構件P1。此外,金屬接墊110的下表面
上形成有凹陷,且導電構件P1填充於凹陷中。
Referring to FIG. 5 , a printed circuit board according to a fifth embodiment of the present invention includes an insulating
根據本發明第五實施例的多層式印刷電路板包括上面形成有第一金屬接墊110的第一絕緣層100、上面形成有第二金屬接墊210的第二絕緣層200、形成於第一絕緣層100中的第一開口部分120、形成於第二絕緣層200中的第二開口部分220、形成於第一開口部分120中的第一金屬凸塊130、形成於開口部分220中的第二金屬凸塊230及形成於第二金屬接墊210的下表面上的導電構件P2。第二金屬接墊210的下表面上可形成有凹陷300,且凹陷300的橫截面積可小於第二金屬接墊210的橫截面積。導電構件P2填充於凹陷300中。第一金屬凸塊130可插入凹陷300中。
A multilayer printed circuit board according to the fifth embodiment of the present invention includes a first insulating
在圖5中,第一金屬凸塊130形成為兩層式結構,但第五實施例不排除呈單層式結構的第一金屬凸塊130。
In FIG. 5 , the
當第一金屬凸塊130與第一絕緣層100之間存在間隙時,導電構件P2流動至間隙中以覆蓋第一金屬凸塊130的側表面的預定區域或更多區域。
When a gap exists between the
另一方面,視例如導電構件P2的流動距離、間隙的體積、層疊壓力等條件而定,導電構件P2可移動超過凹陷300而到達第二金屬接墊210的下表面(未示出)。此外,當第二金屬接墊210與第二絕緣層200之間存在間隙時,導電構件P2可流動至間隙中以覆蓋第二金屬接墊210的側表面(未示出)。
On the other hand, depending on conditions such as the flow distance of the conductive member P2, the volume of the gap, the lamination pressure, etc., the conductive member P2 may move beyond the
在下文中,將闡述製造印刷電路板的方法。 In the following, a method of manufacturing a printed circuit board will be explained.
圖6至圖9是示出製造根據本發明實施例的印刷電路板的方法中所使用的各製程的剖視圖。 6 to 9 are cross-sectional views illustrating various processes used in a method of manufacturing a printed circuit board according to an embodiment of the present invention.
參照圖6,提供載體,在所述載體中絕緣材料C0的兩個表面上層疊有金屬箔。絕緣材料C0可為預浸體等。金屬箔可以兩層式結構形成於絕緣材料C0的每一側上,且所述兩層式結構可為銅層。接觸於絕緣材料C0的兩個表面上的金屬箔可為厚度為18微米(μm)的載體金屬箔C1,且層疊於載體金屬箔C1上的金屬箔可為厚度為5微米的晶種金屬箔C2。 Referring to FIG. 6 , a carrier in which metal foils are laminated on both surfaces of an insulating material C0 is provided. The insulating material C0 may be prepreg or the like. The metal foil may be formed on each side of the insulating material CO in a two-layer structure, and the two-layer structure may be a copper layer. The metal foil in contact with both surfaces of the insulating material C0 may be a carrier metal foil C1 with a thickness of 18 microns (μm), and the metal foil laminated on the carrier metal foil C1 may be a seed metal foil with a thickness of 5 μm. C2.
在圖6中,自第二步驟起示出絕緣材料C0的僅一個表面,但可對絕緣材料C0的兩個表面執行相同的製程。 In FIG. 6 , only one surface of the insulating material C0 is shown from the second step, but the same process can be performed on both surfaces of the insulating material C0 .
參照圖6,在金屬箔上塗覆抗蝕劑膜R,且藉由包括曝光及顯影的微影製程(photolithography process)將抗蝕劑膜R圖案化。藉由執行圖案鍍覆(pattern plating)將電路111及金屬接墊110圖案化。可藉由電解鍍覆(electrolytic plating)執行圖案鍍覆,在電解鍍覆中電子通過載體的金屬箔移動。
Referring to FIG. 6 , a resist film R is coated on the metal foil, and the resist film R is patterned through a photolithography process including exposure and development. The
移除抗蝕劑膜R,且在載體上層疊絕緣層100。絕緣層100可由LCP、環氧樹脂或PID等製成。
The resist film R is removed, and the insulating
在絕緣層100中形成開口部分120,且開口部分120位於金屬接墊110上。金屬接墊110的上表面通過開口部分120暴露出。當絕緣層100為感光性,可藉由曝光及顯影製程形成開口部分120。另一方面,當絕緣層100為非感光性,可藉由雷射製程(laser process)形成開口部分120。
An
圖7示出與圖6相關聯的製程。 FIG. 7 illustrates the process associated with FIG. 6 .
參照圖7,在執行除膠渣(desmear)以移除開口部分120中的殘留物(膠渣)之後,在開口部分120中形成金屬凸塊130。金屬凸塊130被形成為突出於絕緣層100的上表面上方。當金屬凸塊130形成為兩層式結構時,首先形成高熔點凸塊131,且在高熔點凸塊131上形成厚度相對較薄的低熔點凸塊132。可藉由電解鍍覆形成高熔點凸塊131及低熔點凸塊132。在此種情形中,電子通過載體的金屬箔移動。
Referring to FIG. 7 , after desmear is performed to remove residue (smear) in the
在絕緣層100上堆疊遮罩M,且遮罩M可在隨後欲闡述的蝕刻製程等中保護金屬凸塊130。
A mask M is stacked on the insulating
在絕緣層100上形成遮罩M之後,移除載體。載體的金屬箔的僅一部分(特別是晶種金屬箔C2)餘留下來,且可藉由單獨的蝕刻製程移除晶種金屬箔C2。此處,當金屬接墊110與晶種金屬箔C2由相同的金屬形成時,將金屬接墊110的下表面與晶種金屬箔C2一起進行蝕刻。如此一來,金屬接墊110的下表面凹陷超過絕緣層100的下表面,且金屬接墊110的下表面與絕緣層100形成空間110’。
After the mask M is formed on the insulating
與金屬接墊110的下表面相似,將電路111的下表面與晶種金屬箔C2一起蝕刻。如此一來,電路111的下表面凹陷超過絕緣層100的下表面。電路111的下表面與絕緣層100構成空間111’。
Similar to the lower surface of the
在金屬接墊110的下表面上形成導電構件P1,並將導電
構件P1印刷(填充)於由金屬接墊110的下表面與絕緣層100形成的空間110’中。可將具有用於暴露出金屬接墊110的下表面的孔的單獨的印刷遮罩貼合至絕緣層100的下表面,以提高導電構件P1的印刷準確性。
A conductive member P1 is formed on the lower surface of the
亦可在電路111的下表面上形成導電構件P3,並可將導電構件P3印刷(填充)於由電路111的下表面與絕緣層100形成的空間111’中。當印刷遮罩中設置有用於暴露出電路111的下表面的孔時,可在電路111的下表面上形成導電構件P3。然而,若印刷遮罩覆蓋電路111的下表面,則可不在電路111的下表面上形成導電構件。
The conductive member P3 may also be formed on the lower surface of the
參照圖8(a)及圖8(b),當堆疊於絕緣層100的上表面上的遮罩M及堆疊於絕緣層100的下表面上的印刷遮罩均被移除時,圖8(a)中的單元基板製作完成。
8(a) and 8(b), when the mask M stacked on the upper surface of the insulating
圖8(b)示出圖8(a)所示下表面。金屬接墊110具有的寬度較電路111所具有的寬度寬,且在金屬接墊110的整個下表面上形成導電構件P1。可視需要在電路111的下表面的至少一部分上形成導電構件P3。
Figure 8(b) shows the lower surface shown in Figure 8(a). The
參照圖9,在高溫下按壓多個單元基板10、20及30來進行平行構成式層疊以提供多層式印刷電路板。此處,第一金屬凸塊130的上部部分在位於第一金屬凸塊130上方的第二金屬接墊210的下表面上插入導電構件P2中。
Referring to FIG. 9 , a plurality of
僅將第一金屬凸塊130插入導電構件P2中,且在導電
構件P2的流動性相對小的條件下,導電構件P2不向外流動。因此可製造出根據第一實施例的印刷電路板。
Only the
在導電構件P2的流動性穩固且在第一金屬凸塊130與第一絕緣層100之間存在間隙的條件下,導電構件P2可流動至第一金屬凸塊130與第一絕緣層100之間的間隙,且可覆蓋第一金屬凸塊130的側表面的預定區域或更多區域。因此,可製造出根據第二實施例的印刷電路板。
Under the condition that the flowability of the conductive member P2 is stable and there is a gap between the
此處,視層疊條件而定,第二金屬接墊210的下表面中可存在不形成導電構件P2的區。亦即,可不在除第一金屬凸塊130與第二金屬接墊210相接的區以外的部位形成導電構件P2。
Here, depending on the lamination conditions, a region where the conductive member P2 is not formed may exist in the lower surface of the
另外,第一金屬凸塊130的上表面與第二金屬接墊210的下表面可彼此接觸。此外,導電構件P2與第二金屬接墊210的下表面可僅在第一金屬凸塊130周圍進行接觸。
In addition, the upper surface of the
另一方面,在導電構件P2的流動性穩固且在第二金屬接墊210與第二絕緣層200之間存在間隙的條件下,導電構件P2可流動至第二金屬接墊210與第二絕緣層200之間的間隙,且不僅覆蓋第一金屬凸塊130的側表面,而且覆蓋第二金屬接墊210的側表面。因此,可製造出根據本發明第三實施例的印刷電路板。
On the other hand, under the condition that the fluidity of the conductive member P2 is stable and there is a gap between the
此外,在此種情形中,導電構件P2可覆蓋第一金屬凸塊130的側表面的預定區域或更多區域。
Furthermore, in this case, the conductive member P2 may cover a predetermined area or more areas of the side surface of the
圖10至圖11是示出製造根據本發明的另一實施例的印刷電路板的方法中所使用的各製程的剖視圖。 10 to 11 are cross-sectional views illustrating various processes used in a method of manufacturing a printed circuit board according to another embodiment of the present invention.
除將金屬凸塊130形成為單個層以外,圖10及圖11中所述製造方法實質上與參照圖6至圖9所述的方法相同。在此種情形中,將金屬凸塊130形成為突出於絕緣層100的上表面上方。藉由此種方法,可製造出根據第四實施例的印刷電路板。
The manufacturing method described in FIGS. 10 and 11 is substantially the same as that described with reference to FIGS. 6 to 9 , except that the metal bumps 130 are formed as a single layer. In this case, the
圖12至圖14是示出製造根據本發明又一實施例的印刷電路板的方法中所使用的各製程的剖視圖。 12 to 14 are cross-sectional views illustrating various processes used in a method of manufacturing a printed circuit board according to yet another embodiment of the present invention.
圖12可被理解為連接在圖6所示製程之後的製程。 FIG. 12 can be understood as a process subsequent to the process shown in FIG. 6 .
參照圖12,在開口部分120中形成金屬凸塊130。將金屬凸塊130形成為突出於絕緣層100的上表面上方。當金屬凸塊130形成為兩層式結構時,首先形成高熔點凸塊131,且在高熔點凸塊131上形成厚度相對較薄的低熔點凸塊132。可藉由電解鍍覆形成高熔點凸塊131及低熔點凸塊132。在此種情形中,電子通過載體的金屬箔移動。
Referring to FIG. 12 , a
可在絕緣層100上堆疊遮罩M,且遮罩M可在隨後欲闡述的蝕刻製程等中保護金屬凸塊130。
The mask M may be stacked on the insulating
在絕緣層100上形成遮罩M之後,移除載體。載體的金屬箔的僅一部分(特別是晶種金屬箔C2)餘留下來,且可藉由單獨的蝕刻製程移除晶種金屬箔C2。此處,當金屬接墊110與晶種金屬箔C2由相同的金屬形成時,將金屬接墊110的下表面與晶種金屬箔C2一起進行蝕刻。如此一來,金屬接墊110的下表面凹陷超過絕緣層100的下表面。
After the mask M is formed on the insulating
與金屬接墊110的下表面相似,將電路111的下表面與
晶種金屬箔C2一起蝕刻。如此一來,電路111的下表面可凹陷超過絕緣層100的下表面。
Similar to the lower surface of the
使金屬接墊110的下表面經歷二次蝕刻(secondary etching)以形成凹陷300。凹陷300在面積上可小於金屬接墊110,且凹陷300可位於金屬接墊110的中心中。可在絕緣層100的下表面上層疊蝕刻遮罩之後執行用於形成凹陷300的二次蝕刻。蝕刻遮罩覆蓋電路111的下表面,以使電路111的下表面中可不形成凹陷300。
The lower surface of the
凹陷300的深度可小於或等於金屬接墊110的厚度且可慮及電導特性而被設定為預定深度。
The depth of the
具體而言,在金屬接墊110的下表面上形成導電構件P1,並將導電構件P1印刷(填充)於凹陷300中。可將具有用於暴露出凹陷300的孔的單獨的印刷遮罩貼合至絕緣層100的下表面,以提高導電構件P1的印刷準確性。
Specifically, the conductive member P1 is formed on the lower surface of the
參照圖13(a)及圖13(b),當堆疊於絕緣層100的上表面上的遮罩M及堆疊於絕緣層100的下表面上的印刷遮罩均被移除時,單元基板10及20、30製作完成。
Referring to FIGS. 13(a) and 13(b) , when the mask M stacked on the upper surface of the insulating
圖13(b)示出圖13(a)所示下表面。金屬接墊110具有的寬度較電路111的寬度寬,且形成於凹陷300中的導電構件P1的面積小於金屬接墊110的面積。必要時,可不在電路111的下表面上形成凹陷300,且可不在電路111的下表面上形成導電構件P1。
Figure 13(b) shows the lower surface shown in Figure 13(a). The
參照圖14,在高溫下按壓多個單元基板10、20及30來進行平行構成式層疊以提供多層式印刷電路板。此處,第一金屬凸塊130的上部部分在位於第一金屬凸塊130上方的第二金屬接墊210的下表面上插入凹陷300中的導電構件P2中。如此一來,可製造出根據第五實施例的印刷電路板。
Referring to FIG. 14 , a plurality of
在導電構件P2的流動性相對小的條件下,僅將第一金屬凸塊130插入導電構件P2中,且導電構件P2可不向外流動。導電構件可流動至第一金屬凸塊130與第一絕緣層100之間的間隙,且在導電構件P2的流動性穩固且在第一金屬凸塊130與第一絕緣層100之間存在間隙的條件下,導電構件P2可覆蓋第一金屬凸塊130的側表面的預定區域或更多區域。第二金屬接墊210的下表面上可存在不形成導電構件P2的區域。亦即,可不在除第一金屬接墊130與第二金屬接墊210相接的區以外的部位形成導電構件P2。
Under the condition that the fluidity of the conductive member P2 is relatively small, only the
第一金屬凸塊130的上表面與第二金屬接墊210的下表面可彼此接觸。此外,導電構件P2與第二金屬接墊210的下表面可僅在第一金屬凸塊130周圍進行接觸。
The upper surface of the
在導電構件P2的流動性穩固且第二金屬接墊210與第二絕緣層200之間存在間隙的條件下,導電構件P2可流動至第二金屬接墊210與第二絕緣層200之間的間隙,且導電構件P2可不僅覆蓋第一金屬凸塊130的側表面,而且覆蓋第二金屬接墊210的側表面。此外,在此種情形中,導電構件P2可覆蓋第一金屬凸
塊130的側表面的預定區域或更多區域。
Under the condition that the fluidity of the conductive member P2 is stable and there is a gap between the
儘管本發明包括特定實例,然而對於此項技術中具有通常知識者而言將顯而易見,在不背離申請專利範圍及其等效範圍的精神及範圍的條件下,可在該些實例中作出各種形式及細節上的變化。本文中所述實例應被視作僅用於說明意義,而非用於限制。對每一實例中的特徵或態樣的說明應被視作適用於其他實例中的相似特徵或態樣。若以不同的次序執行所述技術及/或若以不同的方式對所述系統、架構、裝置或電路中的組件加以組合及/或以其他組件或其等效組件進行替換或補充,則可達成適合的結果。因此,本發明的範圍並非由詳細說明界定,而是由申請專利範圍及其等效範圍界定,且處於申請專利範圍及其等效範圍的範圍內的所有變動皆應被視作包含於本發明中。 Although this invention includes specific examples, it will be apparent to those of ordinary skill in the art that various forms may be made in these examples without departing from the spirit and scope of the claimed scope and its equivalents. and changes in details. The examples set forth herein should be considered illustrative only and not limiting. Descriptions of features or aspects in each instance should be deemed to apply to similar features or aspects in other instances. The techniques may be performed in a different order and/or if components in the systems, architectures, devices or circuits are combined in a different manner and/or replaced or supplemented by other components or their equivalents. Achieve appropriate results. Therefore, the scope of the present invention is defined not by the detailed description, but by the patent application scope and its equivalent range, and all changes within the scope of the patent application scope and its equivalent range shall be deemed to be included in the present invention. middle.
100、200‧‧‧絕緣層 100, 200‧‧‧insulation layer
110、210‧‧‧金屬接墊 110, 210‧‧‧Metal pads
111、211‧‧‧電路 111, 211‧‧‧circuit
120、220‧‧‧開口部分 120, 220‧‧‧Opening part
130、230‧‧‧金屬凸塊 130, 230‧‧‧metal bumps
131、231‧‧‧高熔點凸塊 131, 231‧‧‧High melting point bumps
132、232‧‧‧低熔點凸塊 132, 232‧‧‧Low melting point bumps
P1、P2、P3、P4‧‧‧導電構件 P1, P2, P3, P4‧‧‧Conductive components
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US20210035818A1 (en) * | 2019-07-30 | 2021-02-04 | Intel Corporation | Sacrificial pads to prevent galvanic corrosion of fli bumps in emib packages |
CN113838760A (en) * | 2020-06-23 | 2021-12-24 | 群创光电股份有限公司 | Circuit structure and manufacturing method thereof |
CN115842254B (en) * | 2023-03-01 | 2023-05-12 | 上海合见工业软件集团有限公司 | Stacked interconnection system and circuit board |
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TW512653B (en) * | 1999-11-26 | 2002-12-01 | Ibiden Co Ltd | Multilayer circuit board and semiconductor device |
JP2007173343A (en) * | 2005-12-20 | 2007-07-05 | Sumitomo Bakelite Co Ltd | Multilayer board and electronic apparatus |
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- 2017-10-20 KR KR1020170136856A patent/KR102442386B1/en active IP Right Grant
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- 2018-07-25 JP JP2018139486A patent/JP7358715B2/en active Active
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TW512653B (en) * | 1999-11-26 | 2002-12-01 | Ibiden Co Ltd | Multilayer circuit board and semiconductor device |
JP2008515241A (en) * | 2004-10-01 | 2008-05-08 | テセラ・インターコネクト・マテリアルズ,インコーポレイテッド | Interconnect element structure and manufacturing method, and multilayer wiring board including interconnect element |
JP2007173343A (en) * | 2005-12-20 | 2007-07-05 | Sumitomo Bakelite Co Ltd | Multilayer board and electronic apparatus |
TW201247049A (en) * | 2010-12-15 | 2012-11-16 | Ngk Spark Plug Co | Wiring board |
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KR20190044428A (en) | 2019-04-30 |
JP2019080043A (en) | 2019-05-23 |
KR102442386B1 (en) | 2022-09-14 |
JP7358715B2 (en) | 2023-10-11 |
TW201918139A (en) | 2019-05-01 |
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