TWI809918B - Time amplifier - Google Patents

Abstract

A time amplifier comprises a thermometer code encoder, a signal detection and delay circuit, a current source control circuit, and a time amplifier circuit. The first switch control signal and the second switch control signal output by the current source control circuit control the time amplifier circuit, so that there is an amplification time difference between the first output signal and the second output signal output by the time amplifying circuit, and the amplified time difference is the ratio between the three charging currents of the time amplifier circuit. Since the magnitude of the charging current can be controlled by the control code received by the thermometer code encoder, the time amplifier with adjustable amplification gain is achieved.

Description

time difference amplifier

The present invention relates to a time difference amplifier, in particular to a time difference amplifier with adjustable gain.

The time precision required by modern systems is getting higher and higher. For example, time-to-digital converters, all-digital phase-locked loops, or the field of space observation all have high-resolution requirements. Generally, the clock cycle generated by a quartz crystal is used It can only reach the nanosecond level. If in special applications, such as laser rangefinder, logic analyzer and other fields, it is necessary to pursue the resolution to the picosecond level, it is necessary to use a time-to-digital converter and a time amplifier to convert the time interval Processing after zooming in. In common timing amplifiers based on SR latches, the achievable gain is fixed, and the time difference between input signals is unpredictable, which leads to more restrictions on conventional timing amplifiers.

The main purpose of the present invention is to charge the first charging capacitor and the second charging capacitor respectively by the first controllable current source and the second controllable current source of the first amplification control unit and the second amplification control circuit in the time amplification circuit, Then through the first comparator and the second comparator, the voltage between the first charging capacitor and the second charging capacitor is compared with the reference voltage, and an output signal with a time gain is output, because The time gain is determined by the magnitude of the current in the first controllable current source and the second controllable current source, and the gain can be controlled by changing the magnitude of the current source.

A time difference amplifier of the present invention includes a thermometer code encoder, a signal detection and delay circuit, a current source control circuit and a time amplification circuit, the thermometer code encoder receives a control code, and the thermometer code encoder outputs A thermometer code, the signal detection and delay circuit receives a first input signal and a second input signal, the signal detection and delay circuit is used to detect the phase between the first input signal and the second input signal Relationally output a first detection signal and a second detection signal, the signal detection and delay circuit delays the first input signal and the second delay signal to output a first delay signal and a second delay signal , the current source control circuit is electrically connected to the thermometer code encoder and the signal detection and delay circuit to receive the thermometer code, the first detection signal, the second detection signal, the first delay signal and the second Two delay signals, the current source control circuit outputs a plurality of first switch control signals and a plurality of second switch control signals, the time amplifying circuit is electrically connected to the current source control circuit, and the time amplifying circuit has a first amplifying control unit and a second amplification control unit, the first amplification control unit has a plurality of first controllable current sources, a first charging capacitor and a first comparator, and the first controllable current sources receive the first switches The control signal is controlled to be turned on or off, and the first controllable current sources that are turned on charge the first charging capacitor to generate a first charging voltage, and the first comparator receives the first charging voltage and a reference voltage to perform Comparing and outputting a first output signal, the second amplification control unit has a plurality of second controllable current sources, a second charging capacitor and a second comparator, and the second controllable current sources receive the second The switch control signal is controlled to be turned on or off, and the second controllable current sources turned on charge the second charging capacitor to generate a second charging voltage, and the second comparator receives the second charging voltage and the reference voltage Comparing and outputting a second output signal.

The present invention controls the first amplification control unit and the second amplification control unit by the current source control circuit, so that the gain provided by the time difference amplifier can be adjusted, and the input signal received by the time difference amplifier The maximum value of the time difference between can also be pre-evaluated, so that the time difference amplifier of the present invention can be used more widely.

Please refer to Fig. 1, which is an embodiment of the present invention, a time difference amplifier 100 includes a thermometer code encoder 110, a signal detection and delay circuit 120, a current source control circuit 130 and a time amplification circuit 140, the The current source control circuit 130 is electrically connected to the thermometer encoder 110 and the signal detection and delay circuit 120 , and the time amplification circuit 140 is electrically connected to the current source control circuit 130 .

Please refer to Figure 1, the thermometer code encoder 110 receives a control code B[7:0] and outputs a thermometer code D[11:0], the control code B[7:0] is input by the user and used To control the magnitude of the charging current in the time amplifying circuit 140 at the rear end. Please refer to Figures 2a and 2b, the thermometer code encoder 110 has a plurality of thermometer code encoding units 111, and each of the thermometer code encoding units 111 has an AND gate 111a and an OR gate 111b, wherein each of the thermometer code encoding units 111 Receive the two-bit control code and output the three-bit thermometer code after the logical operation of the AND gate 111a and the OR gate 111b. The thermometer code encoder 110 is used to convert the binary control code B[7 :0] is converted to thermometer code D[11:0].

Please refer to FIG. 1, the signal detection and delay circuit 120 receives a first input signal IN1 and a second input signal IN2, the signal detection and delay circuit 120 is used to detect the first input signal IN1 and the second input signal IN1 The phase relationship between the two input signals IN2 outputs a first detection signal EN1 and a second detection signal EN2, and the signal detection and delay circuit 120 delays the first input signal IN1 and the second delay signal IN2 And output a first delay signal IN1_t and a second delay signal IN2_t.

Please refer to Figures 1, 3a, 3b and 3c, the signal detection and delay circuit 120 has a detection unit 121 and a delay unit 122, the detection unit 121 receives the first input signal IN1 and the second input signal IN2 outputs the first detection signal EN1 and the second detection signal EN2. The potentials of the first and second detection signals EN1 and EN2 are used to indicate that the phase of the first input signal IN1 leads or lags behind the second The phase of the input signal IN2. The delay unit 122 receives the first input signal IN1 and the second input signal IN2 for delay and outputs the first delayed signal IN1_t and the second delayed signal IN2_t.

Please refer to FIG. 3a. In this embodiment, the detection unit 121 has a phase detector 121a, a register 121b and a multiplexer 121c. The phase detector 121a receives the first input signal IN1 and the second input signal IN2, and the phase detector 121a is used to detect the phases of the first input signal IN1 and the second input signal IN2 and output a phase detection signal Det. Please refer to Figure 3b, the phase detector 121a has a first flip-flop DFF1, a second flip-flop DFF2, a third flip-flop DFF3 and an exclusive OR gate XOR, the first flip-flop DFF1 receives the inverted first input signal IN1 and the second input signal IN2, and the first flip-flop DFF1 is triggered by the inverted first input signal IN1 to store the second input signal IN2. The second flip-flop DFF2 is electrically connected to the first flip-flop DFF1, the second flip-flop DFF2 receives the output signal of the first flip-flop DFF1 and the first input signal IN1, and the second flip-flop DFF2 The device DFF2 is triggered by the first input signal IN1 to store the output signal of the first flip-flop DFF1. The third flip-flop DFF3 receives the first input signal IN1 and the second input signal IN2, and the third flip-flop DFF3 is triggered by the first input signal IN1 to store the second input signal IN2. The exclusive OR gate XOR is electrically connected to the second flip-flop DFF2 and the third flip-flop DFF3 to receive the output signal connected to the second flip-flop DFF2 and the third flip-flop DFF3, the exclusive OR The gate XOR outputs the phase detection signal Det. Wherein, when the first input signal IN1 leads the second input signal IN2, the phase detection signal Det is at a low potential; when the second input signal IN2 leads the first input signal IN1, the phase detection signal Det for high potential.

Please refer to Figure 3a, the register 121b is electrically connected to the phase detector 121a to receive the phase detection signal Det, and the register 121b is triggered by the inverted first input signal IN1 to temporarily store the phase Detect the signal Det and output the second detection signal EN2, the multiplexer 121c receives a power supply voltage VDD, a ground potential GND and the phase detection signal Det, the multiplexer 121c receives the phase detection signal Det The potential of the first detection signal EN1 controlled to change output is the high potential of the power supply voltage VDD or the low potential of the ground potential GND. In this embodiment, when the first input signal IN1 leads the second input signal IN2, the first detection signal EN1 is at a high potential, and the second detection signal EN2 is at a low potential. When IN2 leads the first input signal IN1, the first detection signal EN1 is at low potential, and the second detection signal EN2 is at high potential.

Please refer to Fig. 3c, the delay unit 122 has a control voltage generation circuit 122a and complex Several adjustable delay circuits 122b, the control voltage generation circuit 122a receives a control voltage Vc and generates a P-type control voltage Pc, each of the adjustable delay circuits 122b receives the control voltage Vc and the P-type control voltage Pc, And the adjustable delay circuits 122b delay the first input signal IN1 and the second input signal IN2 and output the first delayed signal IN1_t and the second delayed signal IN2_t. Wherein, the control voltage Vc and the P-type control voltage Pc generated by the control voltage generation circuit 122a are used to adjust the delay time of each of the adjustable delay circuits 122b, so that the delay unit 122 can provide the same in different corners. time delay.

Please refer to FIG. 1, the current source control circuit 130 is electrically connected to the thermometer code encoder 110 and the signal detection and delay circuit 120 to receive the thermometer code D[11:0], the first detection signal EN1, The second detection signal EN2, the first delay signal IN1_t and the second delay signal IN2_t, the current source control circuit 130 outputs a plurality of first switch control signals S1, S2, S3, S10, S11, S12 and a plurality of The second switch control signals S4, S5, S6, S7, S8, S9. In this embodiment, the current source control circuit 130 has a plurality of logic gates, and these logic gates are based on the thermometer code D[11:0], the first detection signal EN1, the second detection signal EN2, the The first delay signal IN1_t and the second delay signal IN2_t output the first switch control signals S1, S2, S3, S10, S11, S12 and the second switch control signals S4, S5, S6, S7, S8, S9 . The current source control circuit 130 of this embodiment is composed of a plurality of AND gates, but since there are infinitely many combinations of logic gates that can constitute the current source control circuit 130, the current source control circuit 130 composed of AND gates is not Limitations of this case, and preferably, the first switch control signals S1, S3, S10, S11 and the second switch control signals S4, S6, S7, S9 respectively have 5 bits to control the The time amplifies the magnitude of the charging current of the circuit 140 .

Please refer to FIGS. 1 and 4 , the time amplification circuit 140 is electrically connected to the current source control circuit 130 , and the time amplification circuit 140 has a first amplification control unit 141 and a second amplification control unit 142 . The first amplification control unit 141 has a plurality of first controllable current sources 141a, a first charging capacitor 141b and a first comparator 141c, and the first controllable current sources 141a receive the first switch control signals S1 , S2, S3, S10, S11, and S12 are controlled to be turned on or off, and the first controllable current sources 141a that are turned on charge the first charging capacitor 141b to generate a first charging voltage Vc1. The device 141c receives the first charging voltage Vc1 and a reference voltage Vr for comparison and outputs a first output signal O1. The second amplification control unit 142 has a plurality of second controllable current sources 142a, a second charging capacitor 142b and a second comparator 142c, and the second controllable current sources 142a receive the second switch control signals S4 , S5, S6, S7, S8, and S9 are controlled to be turned on or off, and the second controllable current sources 142a that are turned on charge the second charging capacitor 142b to generate a second charging voltage Vc2. The device 142c receives the second charging voltage Vc2 and compares the reference voltage Vr to output a second output signal O2.

In this embodiment, each of the first controllable current sources 141a has a first switch sw1 and a first current source a1, and the two ends of each of the first switches sw1 respectively receive the power supply voltage VDD and are electrically connected to the first One end of a current source a1, and each of the first switches sw1 is controlled by each of the first control signals S1, S2, S3, S10, S11, S12 (not shown in the figure), the other end of each of the first current sources a1 One end of the first charging capacitor 141b is electrically connected, and the other end of the first charging capacitor 141b is grounded. Wherein, the first amplification control unit 141 has three sets of the first controllable current sources 141a to respectively provide three sets of charging currents Ib1, Ib2, Ib3 to the first charging capacitor 141b. In this embodiment, the first switch control signals S1, S10 are used to control the first controllable current source 141a that provides the charging current Ib1, and the first switch control signals S2, S12 are used to control the supply of charging current Ib1. The first controllable current source 141a of the current Ib2, the first switch control signals S3, S11 are used to control the first controllable current source 141a providing the charging current Ib3, and the first switch control signals S1, S2, S3 are controlled when the first input signal IN1 leads the second input signal IN2, and the first switch control signals S10, S11, S12 are controlled when the first input signal IN1 lags behind the second input signal IN2 time to control.

Please refer to Figure 5a, preferably, each of the first switches sw1 of the first controllable current source 141a that provides the charging current Ib1 and Ib3 is composed of a plurality of first switches ssw1, and each of the first current sources a1 It is composed of a plurality of first-time current sources sa1, each first-time switch ssw1 is electrically connected to each first-time current source sa1, and each first-time switch ssw1 is controlled by each first control signal S1, S3, Different bits of S10 and S11 are controlled, whereby the magnitudes of the charging currents Ib1 and Ib3 can be controlled through the first control signals S1 , S3 , S10 and S11 .

Please refer to FIG. 4, each of the second controllable current sources 142a has a second switch sw2 and a second current source a2, and the two ends of each of the second switches sw2 respectively receive the power supply voltage VDD and are electrically connected to the first One end of two current sources a2, and each of the second switches sw2 is controlled by each of the second control signals S4, S5, S6, S7, S8, S9 (not shown in the figure), and the other end of each of the second current sources a2 One end of the second charging capacitor 142b is electrically connected, and the other end of the second charging capacitor 142b is grounded. Wherein, the second amplification control unit 142 has three sets of the second controllable current sources 142a to respectively provide three sets of charging currents Ib1, Ib2, Ib3 to the second charging capacitor 142b, and the three sets of the second controllable current sources 142a The magnitudes of the three sets of charging currents Ib1, Ib2, Ib3 provided by the controllable current source 142a are the same as the magnitudes of the three sets of charging currents Ib1, Ib2, Ib3 provided by the first controllable current source 141a. The second switch control signals S4, S7 are used to control the second controllable current source 142a that provides the charging current Ib1, and the second switch control signals S5, S8 are used to control the second controllable current source 142a that provides the charging current Ib2. The controllable current source 142a, the second switch control signals S6, S9 are used to control the second controllable current source 142a that provides the charging current Ib3, and the second switch control signals S4, S5, S6 are in the The control is performed when the first input signal IN1 leads the second input signal IN2, and the second switch control signals S7, S8, S9 are controlled when the first input signal IN1 lags behind the second input signal IN2.

Please refer to Figure 5b, preferably, each of the second switches sw2 of the second controllable current source 142a that provides the charging current Ib1 and Ib3 is composed of a plurality of second switches ssw2, and each of the second current sources a2 It is composed of a plurality of second current sources sa2, each of the second switches ssw2 is electrically connected to each of the second current sources sa2, and each of the second switches ssw2 is controlled by each of the first control signals S4, S6, Different bits of S7 and S9 are controlled, thereby, the magnitudes of the charging currents Ib1 and Ib3 can be controlled through the first control signals S4, S6, S7 and S9 respectively.

Please refer to FIG. 4, taking the first input signal IN1 leading the second input signal IN2 as an example, the action of the time amplifying circuit 140 is: at time T0, the first control signals S1 and S3 are turned on to allow charging The current Ib1, Ib3 charges the first charging capacitor 141b, so that the voltage of the first charging voltage Vc1 increases by adding the currents of the charging currents Ib1, Ib3 to the capacitance value of the first charging capacitor 141b. ; Then at time T1, the second control signals S4, S6 are turned on, allowing the charging current Ib1, Ib3 to charge the second charging capacitor 142b, so that the voltage of the second charging voltage Vc2 is equal to the charging current Ib1, Ib3 The slope of the capacitance value of the second charging capacitor 142b is increased after the sum of the currents is added; at time T2, the first control signals S1, S3 cut off the charging currents Ib1, Ib3, and the first control signal S2 is turned on. Allow the charging current Ib2 to charge the first charging capacitor 141b, so that the voltage of the first charging voltage Vc1 increases with the slope of the current magnitude of the charging current Ib2 divided by the capacitance value of the first charging capacitor 141b, and at the same time, the These second control signals S4, S6 cut off the charging current Ib1, Ib3, and the second control signal S5 is turned on, allowing the charging current Ib2 to charge the second charging capacitor 142b, so that the voltage of the second charging voltage Vc2 can be charged by The slope of the current magnitude of the current Ib2 divided by the capacitance value of the second charging capacitor 142b rises; at time T3, the voltage of the first charging voltage Vc1 rises to be greater than the reference voltage Vr, so that the first output signal O1 rises to a high potential ; At time T4, the voltage of the second charging voltage Vc2 rises to be greater than the reference voltage Vr, so that the second output signal O2 rises to a high potential to complete time amplification.

In this embodiment, the first switch control signals S1, S2, S3, S10, S11, S12 and the second switch control signals S4, S5, S6, S7, S8, S9 output by the current source control circuit 130 The control of the first amplification control unit 141 and the second amplification control unit 142 can make the first output signal O1 and the second output signal O2 output by the first comparator 141c and the second comparator 142c There is an amplified time difference between them, and the amplified time difference is the product of the current magnitudes of the charging currents Ib1 and Ib3 divided by the current magnitude of the charging current Ib2. Since the current magnitudes of the charging currents Ib1 and Ib3 can be controlled by the control code B[7:0] received by the thermometer code encoder 110, the time difference amplifier 100 with adjustable amplification gain can be achieved. In addition, by design, the time The amplifying circuit 140 is completed when the first charging voltage Vc1 and the second charging voltage Vc2 are both greater than the reference voltage Vr, so that the maximum value of the time difference between the input first input signal IN1 and the second input signal IN2 is also can be calculated in advance.

Please refer to Fig. 4, the first amplification control unit 141 has a first discharge transistor 141d and a first controllable discharge current source 141e, and the second discharge unit 142 has a second discharge transistor 142d and a second Controllable discharge current source 142e. The two ends of the first discharge transistor 141d are respectively electrically connected to one end of the first charging capacitor 141b and the ground, and the two ends of the first controllable discharge current source 141e are respectively electrically connected to one end of the first charging capacitor 141b and the ground. Grounded, the two ends of the second discharge transistor 142d are respectively electrically connected to one end of the second charging capacitor 142b and the ground, and the two ends of the second controllable discharging current source 142e are electrically connected to one end of the second charging capacitor 142b respectively One end and ground. After time amplification is completed, the first charging capacitor can be charged by the first discharge transistor 141d, the first controllable discharge current source 141e, the second discharge transistor 142d and the second controllable discharge current source 142e. 141b and the second charging capacitor 142b are discharged to a low potential to complete the initialization.

The present invention uses the current source control circuit 130 to control the first amplification control unit 141 and the second amplification control unit 142, so that the gain provided by the time difference amplifier 100 can be adjusted, and the time difference amplifier 100 The maximum value of the time difference between received input signals can also be estimated in advance, so that the time difference amplifier 100 of the present invention can be used more widely.

The scope of protection of the present invention should be defined by the scope of the appended patent application. Any changes and modifications made by anyone who is familiar with this technology without departing from the spirit and scope of the present invention belong to the scope of protection of the present invention. .

100: time difference amplifier 110: thermometer code encoder 111: thermometer code coding unit 111a: and gate 111b: OR gate 120: Signal detection and delay circuit 121: Detection unit 121a: phase detector 121b: Temporary register 121c: multiplexer 122: delay unit 122a: control voltage generating circuit 122b: adjustable delay circuit 130: Current source control circuit 140: Time amplification circuit 141: The first amplification control unit 141a: the first controllable current source 141b: the first charging capacitor 141c: first comparator 141d: first discharge transistor 141e: the first controllable discharge current source 142: The second amplification control unit 142a: the second controllable current source 142b: the second charging capacitor 142c: second comparator 142d: the second discharge transistor 142e: the second controllable discharge current source Vc: control voltage sw1: first switch ssw1: first switch a1: the first current source sa1: the first current source sw2: second switch ssw2: the second switch a2: second current source sa2: second current source B[7:0]: control code D[11:0]: thermometer code IN1: The first input signal IN2: Second input signal EN1: The first detection signal EN2: Second detection signal IN1_t: the first delayed signal IN2_t: Second delay signal O1: the first output signal O2: Second output signal Det: phase detection signal Vc1: the first charging voltage Vc2: the second charging voltage Vr: reference voltage DFF1: the first flip-flop DFF2: The second flip-flop DFF3: The third flip-flop XOR: exclusive or gate VDD: power supply voltage GND: ground potential S1, S2, S3, S10, S11, S12: first switch control signal S4, S5, S6, S7, S8, S9: second switch control signal Vp: P-type control voltage

Figure 1: A block diagram of a time difference amplifier according to an embodiment of the present invention. Figure 2a: A block diagram of a thermometer code encoder according to an embodiment of the present invention. Figure 2b: According to an embodiment of the present invention, a circuit diagram of a thermometer code encoding unit. FIG. 3a: a circuit diagram of a detection unit according to an embodiment of the present invention. FIG. 3b: A circuit diagram of a phase detector according to an embodiment of the present invention. Fig. 3c: a circuit diagram of a delay unit according to an embodiment of the present invention. Fig. 4: According to an embodiment of the present invention, a circuit diagram of a time amplifying circuit. Fig. 5a: a circuit diagram of a first controllable current source according to an embodiment of the present invention. Fig. 5b: a circuit diagram of a second controllable current source according to an embodiment of the present invention.

100: time difference amplifier

110: thermometer code encoder

120: Signal detection and delay circuit

130: Current source control circuit

140: Time amplification circuit

B[7:0]: control code

IN1: The first input signal

IN2: Second input signal

EN1: The first detection signal

EN2: Second detection signal

IN1_t: the first delayed signal

IN2_t: Second delay signal

S1, S2, S3, S10, S11, S12: first switch control signal

S4, S5, S6, S7, S8, S9: second switch control signal

D[11:0]: thermometer code

O1: the first output signal

O2: Second output signal

Claims (10)

A time difference amplifier comprising: a thermometer code encoder receiving a control code, and the thermometer code encoder outputs a thermometer code; a signal detection and delay circuit receiving a first input signal and a second input signal , the signal detection and delay circuit is used to detect the phase relationship between the first input signal and the second input signal and output a first detection signal and a second detection signal, the signal detection and delay The circuit delays the first input signal and the second delayed signal to output a first delayed signal and a second delayed signal; a current source control circuit is electrically connected to the thermometer code encoder and the signal detection and delay circuit To receive the thermometer code, the first detection signal, the second detection signal, the first delay signal and the second delay signal, the current source control circuit outputs a plurality of first switch control signals and a plurality of second switch control signals switch control signal; and a time amplification circuit electrically connected to the current source control circuit, the time amplification circuit has a first amplification control unit and a second amplification control unit, the first amplification control unit has a plurality of first Controlled current source, a first charging capacitor and a first comparator, these first controllable current sources receive these first switch control signals and are controlled to be turned on or off, and these first controllable current sources that are turned on The first charging capacitor is charged to generate a first charging voltage, the first comparator receives the first charging voltage and a reference voltage for comparison and outputs a first output signal, and the second amplification control unit has a plurality of second A controllable current source, a second charging capacitor, and a second comparator, the second controllable current sources receive the second switch control signals and are controlled to be turned on or off, and the turned-on second controllable currents The source charges the second charging capacitor to generate a second charging voltage, and the second comparator receives and compares the second charging voltage with the reference voltage to output a second output signal. Such as the time difference amplifier of claim 1, wherein the signal detection and delay circuit has A detection unit and a delay unit, the detection unit receives the first input signal and the second input signal and outputs the first detection signal and the second detection signal, the first and second detection signals The potential of the first input signal is used to indicate that the phase of the first input signal is ahead or behind the phase of the second input signal, and the delay unit receives the first input signal and the second input signal for delay and outputs the first delayed signal and the second input signal 2. Delayed signals. As the time difference amplifier of claim 2, wherein the detection unit has a phase detector, a register and a multiplexer, the phase detector receives the first input signal and the second input signal, and The phase detector outputs a phase detection signal, the register is electrically connected to the phase detector to receive the phase detection signal, and the register is triggered by the reverse first input signal to temporarily store the The phase detection signal outputs the second detection signal, and the multiplexer receives the phase detection signal and is controlled by it to change the potential level of the output first detection signal. Such as the time difference amplifier of claim 2, wherein the thermometer code encoder has a plurality of thermometer code encoding units, each of which has an AND gate and an OR gate, wherein each of the thermometer code encoding units receives a two-bit The control code and output the three-bit thermometer code. As the time difference amplifier of claim 1, wherein the current source control circuit has a plurality of logic gates, and the logic gates are based on the thermometer code, the first detection signal, the second detection signal, the first delay signal and The second delayed signal outputs the first switch control signals and the second switch control signals. Such as the time difference amplifier of claim 1, wherein each of the first controllable current sources has a first switch and a first current source, and the two ends of each of the first switches receive a power supply voltage and are electrically connected to each of the first switches One end of a current source, each of the first switches is controlled by the first control signal, the other end of each of the first current sources is electrically connected to one end of the first charging capacitor, and the other end of the first charging capacitor is grounded. The time difference amplifier according to claim 6, wherein the first amplification control unit has three sets of the first controllable current sources to respectively provide three sets of charging currents to the first charging capacitor. Such as the time difference amplifier of claim item 6, wherein each of the first switches is composed of a plurality of first-time switches, each of the first current sources is composed of a plurality of first-time current sources, and each of the first-time switches is electrically Each of the first current sources is connected, and each of the first switches is controlled by a different bit of each of the first control signals. Such as the time difference amplifier of claim 6 or 7, wherein each of the second controllable current sources has a second switch and a second current source, and the two ends of each of the second switches receive a power supply voltage and are electrically connected to the One end of the second current source, the second switch is controlled by the second control signal, the other end of the second current source is electrically connected to one end of the second charging capacitor, the other end of the second charging capacitor is grounded, the first The second amplification control unit has three groups of the second controllable current source to respectively provide three groups of charging currents to the second charging capacitor, each of the second switches is composed of a plurality of second switches, and each of the second current The source is composed of a plurality of second current sources, each of the second switches is electrically connected to each of the second current sources, and each of the second switches is controlled by a different bit of each of the second control signals. Such as the time difference amplifier of claim item 8, wherein the first amplification control unit has a first discharge transistor and a first controllable discharge current source, and the second discharge unit has a second discharge transistor and a second controllable discharge current source. Controlled discharge current source, the two ends of the first discharge transistor are respectively electrically connected to one end of the first charging capacitor and the ground, and the two ends of the first controllable discharge current source are respectively electrically connected to one end of the first charging capacitor and grounding, the two ends of the second discharge transistor are respectively electrically connected to one end of the second charging capacitor and the ground, and the two ends of the second controllable discharge current source are respectively electrically connected to one end of the second charging capacitor and the ground .

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