TWI796229B - power supply protection system - Google Patents

Abstract

A power supply protection system includes a hot swap controller, a processing chip unit, a thermistor unit, a transistor switch unit, and a delay circuit unit. The hot-swap controller includes a detection terminal and a control terminal. The transistor switch unit includes a first terminal connected to the processing chip unit, a second terminal, and a third terminal controlled by the control terminal of the hot-swap controller. When the processing chip unit operates in a peak power mode, a critical current signal is input to the second terminal of the transistor switch unit. The delay circuit unit includes a delay terminal connected to the detection terminal, and a transmission terminal connected to the second terminal of the transistor switch unit. The critical current signal is detected by the transmission terminal of the delay circuit unit and the delay terminal transmits the critical current signal to the detection terminal of the hot-swap controller after the preset time, effectively ensuring the critical current The signal maintains the preset time and is output to the processing chip unit.

Description

power supply protection system

The invention relates to a protection system, in particular to a power supply protection system.

Servers often need to use high-efficiency processing chip units to perform high-speed operation and improve overall operation performance. For example, use a graphics processor (Graphic Processing Unit, GPU) to perform high-efficiency graphics processing. With the requirement of high processing speed and increased performance, it is necessary to provide more power (Power) to make the processing chip unit operate in the maximum performance mode (peak mode). Generally speaking, the power output has a certain rated power, and cooperates with the over current protection mechanism (Over Current Protection, OCP) to cut off the output current when the output current of the power supply is too large to ensure the safety of the system and avoid damage to the processing chip unit or other Risk of component damage. However, it often happens that the graphics processing unit (GPU) is executing the maximum performance mode (peak mode), and when the overcurrent protection circuit detects a surge current due to excessive instantaneous power, it immediately triggers the overcurrent protection mechanism (OCP), resulting in power failure. Or restart the problem, causing the user's troubles and troubles, there is inconvenience in use. Furthermore, during the initial power-on process, inrush current (Inrush Current) or other factors will often generate a large inrush current in an instant, which will lead to the problem of false triggering of the over-current protection mechanism (OCP) or even cause The risk of damage to internal electronic components does have problems that need to be overcome in design, and it is extremely necessary for practitioners to carefully discuss and study improvement solutions.

Therefore, the object of the present invention is to provide a power supply protection system with good performance.

Therefore, the power supply protection system of the present invention is used for receiving an input voltage of a power supply unit. The power supply protection system includes a hot-swap controller capable of receiving the input voltage, a processing chip unit, a sensing resistor, a thermistor unit, a transistor switch unit that is controlled to open and close, and a receiving the input voltage to the delay circuit unit.

The hot-swap controller includes a detection terminal and a control terminal. The processing chip unit can operate in a peak power mode. The sensing resistor includes a first terminal capable of receiving the input voltage, and a second terminal.

The thermistor unit includes a first shunt end connected to the first end of the sensing resistor, and a second shunt end connected to the processing chip unit, the second shunt end of the thermistor unit can transmit a shunt current signal to the processing chip unit.

The transistor switch unit includes a first terminal connected to the processing chip unit, a second terminal, and a third terminal controlled by the control terminal of the hot-swap controller. The second end of the sensing resistor is connected to the second end of the transistor switch unit, and the second end of the sensing resistor can transmit a supply current signal to the second end of the transistor switch unit. The hot-swap controller controls the third terminal of the transistor switch unit through the control terminal to control the opening and closing of the transistor switch unit. When the transistor switch unit receives a first control signal sent by the control terminal according to the third terminal, the transistor switch unit is in the conduction state and the current supply signal received by the second terminal of the transistor switch unit is passed through The first end is output to the processing chip unit, and the processing chip unit receives the shunt current signal transmitted by the second shunt end of the thermistor unit and the supply current signal output by the first end of the transistor switch unit. When the processing chip unit operates in the peak power mode, a limit current signal is input to the processing chip unit, and at this time, the supply current signal output from the first terminal of the transistor switch unit is a critical current signal.

The delay circuit unit includes a delay end connected to the detection end of the hot-swap controller, and a transmission end connected to the second end of the transistor switch unit. When the processing chip unit operates in the peak power mode, the delay After the circuit unit detects that the critical current signal is above the critical current signal for a preset time through the transmission terminal, the delay terminal of the delay circuit unit transmits the critical current signal to the detection terminal of the hot-swap controller, and when When the hot-swap controller judges that the detection terminal detects the critical current signal, the control terminal of the hot-swap controller sends a second control signal to the third terminal of the transistor switch unit and makes the transistor The switch unit is in a non-conductive state; when the power supply protection system is initially powered on and an inrush current (Inrush Current) is generated, the inrush current will be divided into a shunt current that flows out through the second shunt end of the thermistor unit signal, and a supply current signal flowing out from the second end of the sensing resistor.

The effect of the present invention lies in: the delay circuit unit can delay the signal received by the transmission end for the preset time before being transmitted from the delay end to the detection end of the hot-swap controller. When the processing chip When the unit operates in the peak power mode, the second terminal of the transistor switch unit inputs the critical current signal, and the transmission terminal of the delay circuit unit detects the critical current signal and after the preset time, the delay terminal Only then will the critical current signal be sent to the detection terminal of the hot-swap controller, so that the control terminal of the hot-swap controller controls the transistor switch unit to be in a non-conductive state, effectively ensuring the transistor switch unit The critical current signal output by the first terminal is output to the processing chip unit for the preset time. Furthermore, through the ingenuity that the thermistor unit can transmit the split current signal, when the power supply protection system is initially powered on and generates the surge current, the surge current will be divided into the split current signal from the thermistor unit. The shunt application of the shunt current signal flowing out of the second shunt end and the supply current signal flow out of the second end of the sensing resistor can prevent the inrush current from flowing directly from the second end of the sensing resistor to the The transistor switches the unit and causes the problem of damage.

Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same numerals.

Referring to FIG. 1 and FIG. 2 , the power supply protection system 1 of the present invention is used to receive an input voltage of a power supply unit 90 . The power supply protection system 1 includes a hot-swap controller 2 capable of receiving the input voltage, a processing chip unit 3, a sensing resistor 4, a thermistor unit 5, and a transistor switch unit controlled to open and close 6, and a delay circuit unit 7 capable of receiving the input voltage.

The hot swap controller 2 includes a detection terminal 21 and a control terminal 22 . The processing chip unit 3 can operate in a peak power mode. The sensing resistor 4 includes a first terminal 41 capable of receiving the input voltage, and a second terminal 42 .

The thermistor unit 5 includes a first shunt end 51 connected to the first end 41 of the sensing resistor 4, and a second shunt end 52 connected to the processing chip unit 3, the second shunt end of the thermistor unit 5 The shunt terminal 52 can send a shunt current signal to the processing chip unit 3 .

The transistor switch unit 6 includes a first terminal 61 connected to the processing chip unit 3 , a second terminal 62 , and a third terminal 63 controlled by the control terminal 22 of the hot swap controller 2 . The second end 42 of the sensing resistor 4 is connected to the second end 62 of the transistor switch unit 6 and the second end 42 of the sensing resistor 4 can transmit a current signal to the second end of the transistor switch unit 6 62. The hot-swap controller 2 controls the third terminal 63 of the transistor switch unit 6 via the control terminal 22 to control the switching of the transistor switch unit 6 . When the transistor switch unit 6 receives a first control signal sent by the control terminal 22 according to the third terminal 63, the transistor switch unit 6 is in a conduction state and the second terminal 62 of the transistor switch unit 6 receives The current supply signal is output to the processing chip unit 3 through the first end 61, and the processing chip unit 3 receives the split current signal transmitted by the second shunt end 52 of the thermistor unit 5 and the transistor switch unit The supply current signal output by the first end 61 of 6. When the processing chip unit 3 operates in the peak power mode, the input of the processing chip unit 3 is a limit current signal, and at this time, the supply current signal output by the first terminal 61 of the transistor switch unit 6 is a critical current signal. current signal. In this embodiment, the processing unit 3 receives the divided current signal and the supply current signal, when the processing unit 3 operates in the peak power mode, the supply current signal is above the critical current signal and the divided current signal and The sum of the supply current signals reaches the limit current, but not limited thereto.

The delay circuit unit 7 includes a delay terminal 71 connected to the detection terminal 21 of the hot-swap controller 2 , and a transmission terminal 72 connected to the second terminal 62 of the transistor switch unit 6 . When the processing chip unit 3 operates in the peak power mode, the delay circuit unit 7 detects through the transmission terminal 72 that the critical current signal reaches a preset time, and the delay terminal of the delay circuit unit 7 71 sends the critical current signal to the detection terminal 21 of the hot-swap controller 2, and when the hot-swap controller 2 judges that the detection terminal 21 detects the critical current signal, the hot-swap controller The control terminal 22 of 2 transmits a second control signal to the third terminal 63 of the transistor switch unit 6 and makes the transistor switch unit 6 in a non-conductive state. When the power supply protection system 1 is first powered on and generates an inrush current (Inrush Current), the inrush current will be divided into a shunt current signal flowing out through the second shunt terminal 52 of the thermistor unit 5, and a shunt current signal flowing through the second shunt end 52 of the thermistor unit 5, and a The second terminal 42 of the sensing resistor 4 supplies the current signal.

In use, after the power supply protection system 1 is powered on, the hot-swap controller 2 sends the first control signal to the third terminal 63 of the transistor switch unit 6 through the control terminal 22 to control the transistor switch The unit 6 is in the conduction state (On), and the first end 41 of the sensing resistor 4 receives the input voltage of the power supply unit 90 and generates the supply current signal to be input to the electric current through the second end 42 of the sensing resistor 4. The second terminal 62 of the crystal switch unit 6 is output to the processing chip unit 3 through the first terminal 61 of the transistor switch unit 6 . The processing chip unit 3 receives the shunt current signal transmitted from the second shunt end 52 of the thermistor unit 5 and the supply current signal output from the first end 61 of the transistor switch unit 6 . When the processing chip unit 3 operates in the peak power mode, the input to the processing chip unit 3 is the limit current signal, in other words, it is the sum of the divided current signal and the supply current signal received by the processing unit 3 The limit current is reached, so the processing unit 3 is operated in the peak power mode. At this time, the transmission terminal 72 of the delay circuit unit 7 detects that the input to the second terminal 62 of the transistor switch unit 6 is the critical current signal, that is to say, the current supply signal has reached the critical current and the delay circuit unit 7 will send the critical current signal to the detection terminal 21 of the hot-swap controller 2 after the preset time effectively ensure that the critical current signal output by the first terminal 61 of the transistor switch unit 6 is output to the processing chip unit 3 for the preset time. And when the hot-swap controller 2 judges that the detection terminal 21 detects the critical current signal, the current protection mechanism (OCP) is activated and the control terminal 22 of the hot-swap controller 2 transmits the second control signal to the third terminal 63 of the transistor switch unit 6 and make the transistor switch unit 6 in a non-conductive state (Off). To put it simply, after the processing chip unit 3 can maintain operation in the peak power mode for the preset time, the hot-swap controller 2 will control the transistor switch unit 6 to be in a non-conductive state (Off) and The current signal cannot be output to the processing chip unit 3 .

In addition, it should be particularly noted that, in this embodiment, if the power supply protection system 1 is first powered on and generates the inrush current (Inrush Current), the inrush current will be divided into the inrush current from the thermistor unit 5 The design shunt application of the shunt current signal flowing out of the second shunt end 52 of the sensing resistor 4 and the supply current signal flowing out of the second end 42 of the sensing resistor 4 achieves limiting the inrush current and reducing the flow into the sensing resistor through shunting 4 to avoid the peak current of the surge current from flowing directly through the second end 42 of the sensing resistor 4 and flowing out to the second end 62 of the transistor switch unit 6 to cause the hot-swap controller 2 Trigger the over-current protection mechanism (OCP), effectively improving the overall application capability of the over-current protection mechanism (OCP). In this embodiment, the thermistor unit 5 is in the form of a positive temperature coefficient (Positive Temperature Coefficient, PTC) resistor, but it is not limited thereto.

In this embodiment, the processing chip unit 3 is in the form of a graphics processing unit (Graphic Processing Unit, GPU), but it is not limited thereto, it can also be a CPU, MCU or other digital integrated circuit IC (Digital IC) and other related electronic devices. In this embodiment, the transistor switch unit 6 is in the form of an N-type metal oxide semiconductor field effect transistor (NMOS), the first end 61 of the transistor switch unit 6 is the source (S), the second The terminal 62 is a drain (D), and the third terminal 63 is a gate (G), but not limited thereto. Further, in this embodiment, the limitation condition of the peak power mode is that the processing chip unit 3 can operate at the limit current within a peak time range, and the preset time is equal to the peak time, that is, the The maximum performance that the processing chip unit 3 can perform is to maintain the peak time under the condition of operating at the limit current, and when the processing chip unit 3 operates in the peak power mode, the first Terminal 61 outputs the critical current signal to the processing chip unit 3. In other words, when the processing chip unit 3 operates in the peak power mode, the transmission terminal 72 of the delay circuit unit 7 will detect the input of the current signal. The current signal of the second terminal 62 of the crystal switch unit 6 reaches above the critical current signal, and the delay circuit unit 7 sends the critical current signal to the detection terminal of the hot-swap controller 2 after the preset time 21. In this case, through the circuit design of the delay circuit unit 7, the detection terminal 21 of the hot-swap controller 2 is delayed to detect the critical current signal after the preset time, effectively ensuring that the processing chip The unit 3 ensures that the processing chip unit 3 can operate in the peak power mode and maintain the preset time without exceeding the limit of the peak power mode, so that when the processing chip unit 3 needs to perform maximum performance, Execute the peak power mode. And when the processing chip unit 3 operates in the peak power mode and exceeds the peak time, the hot-swap controller 2 will control the transistor switch unit 6 to be in a non-conductive state (Off) and cannot output current signals to the Processing the wafer unit 3 achieves protection of the system and avoids the risk of damage to the processing unit. In this embodiment, the preset time is equal to the peak time, but it is not limited thereto. The preset time can be designed to be shorter than the peak time according to actual needs, so as to perform protection actions earlier.

It should be noted that, in this embodiment, the delay circuit unit 7 further includes a first resistor 73 and a first capacitor 74 . The first resistor 73 has a first end 731 connected to the transmission end 72 and a second end 732 . The first capacitor 74 has a first end 741 connected to the first end 731 of the sensing resistor 4, and a second end 742 connected to the second end 732 of the first resistor 73, and the delay end 71 is connected to the first end 742. A second terminal 732 of a resistor 73 and a second terminal 742 of the first capacitor 74 . In simple terms, the delay circuit unit 7 is a design of an RC delay circuit, but it is not limited thereto, as long as the delay circuit unit 7 can delay the preset time before allowing the detection of the hot-swap controller 2 It is only necessary for the detection terminal 21 to detect the critical current signal. In addition, in this embodiment, using the ingenuity of the delay circuit unit 7 as an RC delay circuit, the required preset time can be adjusted by adjusting the values of the first resistor 73 and the first capacitor 74, so as to In response to the use of different processing chip units 3 in different designs to operate in the corresponding peak power mode, it is ensured that the operation can be maintained in the peak power mode for the preset time within the required peak time range, effectively supporting a variety of different The peak power mode needs to be used, and the overall applicability is good.

By means of the delay circuit unit 7, the signal received by the transmission end 72 can be delayed for the preset time before being transmitted from the delay end 71 to the design of the detection end 21 of the hot-swap controller 2, when the processing chip When the unit 3 operates in the peak power mode, the second terminal 62 of the transistor switch unit 61 inputs the critical current signal, and the transmission terminal 72 of the delay circuit unit 7 detects the critical current signal and passes the preset The delay terminal 71 will send the critical current signal to the detection terminal 21 of the hot-swap controller 2 after a certain time, so that the control terminal 22 of the hot-swap controller 2 controls the transistor switch unit 6 to be non-conductive. The conduction state effectively ensures that the critical current signal output by the first terminal 61 of the transistor switch unit 6 is output to the processing chip unit 3 for the preset time. Furthermore, through the ingenuity that the thermistor unit 5 can transmit the divided current signal, when the power supply protection system 1 is initially powered on and generates the surge current, the surge current will be divided into the divided current signal from the thermistor unit 5. The design shunt application of the shunt current signal flowing out of the second shunt end 52 of the unit 5 and the supply current signal flow out of the second end 42 of the sensing resistor 4 can avoid the surge current directly from the sensing resistor 4. The second terminal 42 of the resistor 4 flows out to the transistor switch unit 6 to cause damage.

In addition, please refer to FIG. 2. It should be specifically explained here that in this embodiment, a protection circuit unit 8 is also included, and the protection circuit unit 8 has a signal terminal connected to the detection terminal 21 of the hot-swap controller 2. 81. A protection terminal 82 connecting the second terminal 42 of the sensing resistor 4 and the second terminal 62 of the transistor switch unit 6, a P-type metal oxide half field effect transistor connecting the signal terminal 81 and the protection terminal 82 A crystal 83 (PMOS), and a startup circuit 84 for controlling the P-type MOSFET 83 to turn on and off. The source (S) of the P-type metal oxide half field effect transistor 83 is connected to the protection end 82, the drain (D) of the P type metal oxide half field effect transistor 83 is connected to the signal end 81, and the P type metal oxide half field effect transistor 83 is connected to the signal end 81. The gate (G) of the half field effect transistor 83 is connected to the startup circuit 84 . The protection circuit unit 8 is used to protect the transistor switch unit 6 . When the power supply protection system 1 is initially powered on, the startup circuit 84 controls the P-type metal oxide semiconductor field effect transistor 83 to be in a conductive state within a protection time. At this time, the second terminal 42 of the sensing resistor 4 transmits The supply current signal will be input to the protection terminal 82 of the protection circuit unit 8 and then to the signal terminal 81 of the protection circuit unit 8 through the P-type metal oxide semiconductor field effect transistor 83, and to the hot-swap controller 2 Detection terminal 21; when the power supply protection system 1 is powered on and after the protection time, the start-up circuit 84 controls the P-type metal-oxide-semiconductor field-effect transistor 83 to be in a non-conductive state. At this time, the sense resistor 4 The supply current signal transmitted by the second terminal 42 is input into the second terminal 62 of the transistor switch unit 6 . If the power supply protection system 1 is initially powered on and generates the inrush current, within the protection time, the shunt in the inrush current flows out from the second end 42 of the sensing resistor 4 The current supply signal will be input to the protection terminal 82 of the protection circuit unit 8 and then to the signal terminal 81 of the protection circuit unit 8 through the P-type metal oxide semiconductor field effect transistor 83, and to the detection of the hot-swap controller 2 End 21. Specifically, during the power-on process, when the power supply protection system 1 starts to be powered on, the start-up circuit 84 immediately controls the P-type metal oxide semiconductor field-effect transistor 83 to be in the conduction state and maintain conduction for the protection time. At this time, Since the P-type MOS field effect transistor 83 is turned on, the current supply signal transmitted by the second end 42 of the sensing resistor 4 will directly flow into the protection end 82 of the protection circuit unit 8 and pass through the P-type MOS field effect transistor. The effect transistor 83 is connected to the signal terminal 81 of the protection circuit unit 8. If the inrush current (Inrush Current) or the overcurrent (Over current) situation occurs at the beginning of power-on, the second terminal of the sensing resistor 4 The supply current signal output by 42 will directly flow into the P-type MOSFET 83 . Further, when the power supply protection system 1 starts to be powered on, the transistor switch unit 6 cannot be turned on because the hot-swap controller 2 has not yet started up, so the transistor switch unit 6 is temporarily in a non-conductive state. , so the current supply signal output by the second end 42 of the sensing resistor 4 will directly flow into the P-type MOSFET 83 instead of inputting into the transistor switch unit 6 during the protection time, effectively avoiding When the power supply protection system 1 is first powered on, because of the inrush current (Inrush Current) or the short circuit of the processing chip unit 3 connected to the transistor switch unit 6, an overcurrent (Over current) is input into the transistor. The switch unit 6 causes the transistor switch unit 6 to be broken down or destroyed, so as to achieve a short-circuit protection measure for the system power supply. When the power supply protection system 1 is powered on and after the protection time has elapsed, the startup circuit 84 controls the P-type MOSFET 83 to be in a non-conductive state. At this time, the hot-swap controller 2 has been powered on The transistor switch unit 6 is turned on and controlled, and the supply current signal transmitted by the second terminal 42 of the sensing resistor 4 is input to the second terminal 62 of the transistor switch unit 6 . Generally speaking, when the power supply protection system 1 is initially powered on, within the protection time, the processing chip unit 3 connected to the transistor switch unit 6 is short-circuited and an overcurrent is generated to input the transistor. The timing of the switching unit 6 will be earlier than the timing of the inrush current (Inrush Current), so in this embodiment, the operation mechanism of the protection circuit unit 8 will be activated first, and then pass through the thermistor Unit 5 transmits the application of the shunt mechanism of the shunt current signal. If the protection time passes smoothly, the start-up circuit 84 controls the P-type metal oxide semiconductor field effect transistor 83 to be in a non-conductive state, and the hot-swap controller 2 has been completed. Power-on start and control make the transistor switch unit 6 in the conduction state, and the supply current signal transmitted by the second end 42 of the sensing resistor 4 will be input to the second end 62 of the transistor switch unit 6, then it can cooperate with The operation mechanism of the delay circuit unit 7 . In addition, the design of connecting the detection terminal 21 of the hot-swap controller 2 through the signal terminal 81 of the protection circuit unit 8, and when power is turned on, the detection terminal 21 of the hot-swap controller 2 can be Real-time detection of the current of the signal terminal 81 of the protection circuit unit 8, if a short circuit occurs as soon as the power is turned on and an overcurrent (Over current) is generated, the detection terminal 21 of the hot-swap controller 2 will immediately detect to the over current (Over current), but usually the over current (Over current) due to the short circuit will be much greater than the critical current signal, so when the drain (D) of the P-type metal oxide half field effect transistor 83 is output When an overcurrent (Over current) reaches the signal terminal 81, the detection terminal 21 of the hot-swap controller 2 will detect the overcurrent (Over current) of the signal terminal 81, and because the overcurrent (Over current) is greater than The value of the critical current signal, so the hot-swap controller 2 will control the transistor switch unit 6 to be in a non-conducting state at the beginning, effectively ensuring that after the protection time is exceeded, the overcurrent (Over current) generated by the short circuit will ) will not pass through the transistor switch unit 6 to avoid the risk of damage to the transistor switch unit 6 .

In addition, in this embodiment, the startup circuit 84 of the protection circuit unit 8 has a second resistor 85 , a second capacitor 86 , and a diode 87 . The second resistor 85 has a first end 851 capable of receiving the input voltage, and a second end 852, the second capacitor 86 has a first end 861 connected to the second end 852 of the second resistor 85, and A ground terminal 862 , the gate of the P-type MOSFET 83 is connected to the first terminal 861 of the second capacitor 86 and the second terminal 852 of the second resistor 85 . The anode of the diode 87 is connected to the gate of the P-type MOSFET 83 , and the cathode of the diode 87 is connected to the first end 851 of the second resistor 85 .

In summary, the power supply protection system 1 of the present invention, through the design of the delay circuit unit 7, can delay the critical current signal for the preset time before the detection terminal 21 of the hot-swap controller 2 detects The critical current signal is detected and controlled to make the transistor switch unit 6 in a non-conductive state, effectively ensuring that the critical current signal output by the first terminal 61 of the transistor switch unit 6 maintains the preset time and is output to the processing chip unit 3, and the processing chip unit 3 can achieve the maximum performance requirement. Furthermore, through the ingenuity that the thermistor unit 5 can transmit the divided current signal, when the power supply protection system 1 is initially powered on and generates the surge current, the surge current will be divided into the divided current signal from the thermistor unit 5. The shunt application of the shunt current signal flowing out of the second shunt terminal 52 of the unit 5 and the supply current signal flow out of the second end 42 of the sensing resistor 4 can prevent the surge current from directly flowing from the sensing resistor 4. The second terminal 42 of 4 flows out to the transistor switch unit 6 and causes damage.

But what is described above is only an embodiment of the present invention, and should not limit the scope of the present invention. All simple equivalent changes and modifications made according to the patent scope of the present invention and the content of the patent specification are still within the scope of the present invention. Within the scope covered by the patent of the present invention.

1: Power supply protection system 731: first end 2: Hot-swap controller 732: second end 21: Detection terminal 74: The first capacitor 22: Control terminal 741: first end 3: Processing wafer unit 742: second end 4: Sense resistor 8: Protection circuit unit 41: first end 81: signal terminal 42: second end 82: Protection end 5: Thermistor unit 83: P-type metal oxide half field effect transistor 51: The first shunt end 84: start circuit 52: The second shunt end 85: Second resistor 6: Transistor switch unit 851: first end 61: first end 852: second end 62: second end 86: Second capacitor 63: third end 861: first end 7: Delay circuit unit 862: Ground terminal 71: delay terminal 87: Diode 72: Transmission end 90: Power supply unit 73: First resistance

Other features and effects of the present invention will be clearly presented in the implementation manner with reference to the drawings, wherein: Figure 1 is a block diagram illustrating an embodiment of the power supply protection system of the present invention; and FIG. 2 is a block diagram illustrating the connection relationship among a hot-swap controller, a transistor switch unit and a protection circuit unit in this embodiment.

1: Power supply protection system

2: Hot-swap controller

21: Detection terminal

22: Control terminal

3: Processing wafer unit

4: Sense resistor

41: first end

42: second end

5: Thermistor unit

51: The first shunt end

52: The second shunt end

6: Transistor switch unit

61: first end

62: second end

63: third end

7: Delay circuit unit

71: delay terminal

72: Transmission end

8: Protection circuit unit

81: signal terminal

82: Protection end

83: P-type metal oxide half field effect transistor

84: start circuit

90: Power supply unit

Claims (9)

A power supply protection system for receiving an input voltage of a power supply unit, the power supply protection system comprising: A hot-swap controller capable of receiving the input voltage, including a detection terminal and a control terminal; a processing chip unit operable in a peak power mode; A sensing resistor, including a first terminal capable of receiving the input voltage, and a second terminal; A thermistor unit, including a first shunt end connected to the first end of the sensing resistor, and a second shunt end connected to the processing chip unit, the second shunt end of the thermistor unit can transmit a shunt a current signal to the processing chip unit; A transistor switch unit that is controlled to be turned on and off includes a first terminal connected to the processing chip unit, a second terminal, and a third terminal controlled by the control terminal of the hot-swap controller. The second end of the resistor is connected to the second end of the transistor switch unit, and the second end of the sense resistor can send a current signal to the second end of the transistor switch unit, and the hot-swap controller is controlled by the Terminal controls the third terminal of the transistor switch unit, and controls the opening and closing of the transistor switch unit. When the transistor switch unit receives a first control signal transmitted by the control terminal according to the third terminal, the transistor The crystal switch unit is in a conduction state and the current supply signal received by the second terminal of the transistor switch unit is output to the processing chip unit through the first terminal, and the processing chip unit receives the second shunt terminal of the thermistor unit The divided current signal transmitted and the supply current signal output by the first terminal of the transistor switch unit, when the processing chip unit operates in the peak power mode, input the processing chip unit as a limit current signal, at this time, The supply current signal output by the first terminal of the transistor switch unit is a critical current signal; and A delay circuit unit that can receive the input voltage, including a delay terminal connected to the detection terminal of the hot-swap controller, and a transmission terminal connected to the second terminal of the transistor switch unit, when the processing chip unit operates on the In peak power mode, the delay circuit unit detects the critical current signal through the transmission terminal and after a preset time, the delay terminal of the delay circuit unit transmits the critical current signal to the detection of the hot swap controller detection terminal, and when the hot-swap controller determines that the detection terminal detects the critical current signal, the control terminal of the hot-swap controller sends a second control signal to the third terminal of the transistor switch unit And make the transistor switch unit in a non-conductive state; when the power supply protection system is initially powered on and generates an inrush current (Inrush Current), the inrush current will be divided into a second shunt through the thermistor unit A divided current signal flowing out from the sense resistor, and a supply current signal flowing out from the second end of the sense resistor. The power supply protection system according to claim 1, wherein the delay circuit unit further includes a first resistor and a first capacitor, the first resistor has a first end connected to the transmission end, and a second end, The first capacitor has a first terminal connected to the first terminal of the sensing resistor, and a second terminal connected to the second terminal of the first resistor, and the delay terminal is connected to the second terminal of the first resistor and the second terminal of the first resistor. The second terminal of a capacitor. The power supply protection system as described in claim 1, wherein the transistor switch unit is an N-type metal oxide semiconductor field effect transistor (NMOS), the first end of the transistor switch unit is a source (S), the second Two terminals are the drain (D), and the third terminal is the gate (G). The power supply protection system as described in claim 3, further comprising a protection circuit unit, the protection circuit unit has a signal terminal connected to the detection terminal of the hot-swap controller, a second terminal connected to the sensing resistor and the The protection end of the second end of the transistor switch unit, a P-type metal oxide semiconductor field effect transistor (PMOS) connected to the signal end and the protection end, and a starting circuit for controlling the opening and closing of the P-type metal oxide half field effect transistor, The source (S) of the P-type metal oxide half field effect transistor is connected to the protection end, the drain (D) of the P type metal oxide half field effect transistor is connected to the signal end, and the P type metal oxide half field effect transistor The gate (G) of the gate is connected to the start-up circuit, and the protection circuit unit is used to protect the transistor switch unit. When the power supply protection system is first powered on, the start-up circuit controls the P-type metal oxide half-field within a protection time. The effect transistor is in the conduction state. At this time, the supply current signal transmitted by the second end of the sensing resistor will be input into the protection end of the protection circuit unit and then sent to the protection circuit unit through the P-type metal oxide semiconductor field effect transistor. The signal terminal, and to the detection terminal of the hot-swap controller; when the power supply protection system is powered on and after the protection time, the starting circuit controls the P-type metal oxide semi-field effect transistor to be in a non-conductive state, At this time, the supply current signal transmitted by the second end of the sensing resistor will be input to the second end of the transistor switch unit; when the power supply protection system is initially powered on and generates the inrush current (Inrush Current) , within the protection time, the inrush current splits the supply current signal flowing from the second end of the sensing resistor into the protection end of the protection circuit unit and is transmitted through the P-type metal oxide semiconductor field effect transistor. To the signal end of the protection circuit unit, and to the detection end of the hot-swap controller. The power supply protection system as described in claim 4, wherein, the starting circuit of the protection circuit unit has a second resistor and a second capacitor, and the second resistor has a first terminal capable of receiving the input voltage, and a The second terminal, the second capacitor has a first terminal connected to the second terminal of the second resistor, and a ground terminal, the gate of the P-type metal oxide semiconductor field effect transistor is connected to the first terminal of the second capacitor and the first terminal of the second capacitor. the second end of the second resistor. The power supply protection system as described in claim 5, wherein, the starting circuit of the protection circuit unit also has a diode connecting the second resistor and the P-type metal-oxide-semiconductor field-effect transistor, and the anode of the diode is connected to The gate of the P-type metal oxide semiconductor field effect transistor and the cathode of the diode are connected to the first end of the second resistor. The power supply protection system as described in claim 1, wherein the peak power mode is that the processing chip unit can operate the limit current within a peak time range, and when the processing chip unit operates in the peak power mode, the power The first end of the crystal switch unit outputs the critical current signal to the processing chip unit, and the preset time is less than or equal to the peak time. The power supply protection system as described in claim 1, wherein the processing unit receives the divided current signal and the supply current signal, and when the processing unit operates in the peak power mode, the supply current signal is above the critical current signal and The sum of the divided current signal and the supply current signal reaches the limit current. The power supply protection system as claimed in claim 1, wherein the thermistor unit is a positive temperature coefficient (PTC) resistor.

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