TWI794123B - Negative charge pump system - Google Patents

Abstract

A negative charge pump system includes a first negative voltage generating unit, a second negative voltage generating unit and a feedback circuit. The first negative voltage generating unit and the second negative voltage generating unit are used to generate negative voltage. The feedback circuit receives the negative voltage and outputs a feedback signal to the first and second negative voltage generating units for controlling, wherein the first and second bypass transistors of the first and second negative voltage generating units can be respectively bypassing the first and second negative voltage generating units, the use of the negative charge pump system is more diverse.

Description

Negative Voltage Charge Pump System

The invention relates to a charge pump system, in particular to a negative voltage charge pump system.

Currently widely used portable mobile devices, such as smartphones, tablets and notebook computers, are powered by built-in batteries. However, since many electronic circuits in mobile devices require voltages of different potentials, the settings in mobile devices There is a DC-DC converter to convert the battery voltage to the voltage required by the electronic circuit.

DC-DC converters can be roughly divided into boost converters using inductive elements, buck converters, single-ended primary inductive converters (SEPIC), and charge pumps using capacitive elements. In the generation of negative voltage, negative voltage converters in the form of boost converters and buck converters usually require an additional negative voltage reference signal or an off-chip inductance element to establish the required input signal. produces a negative voltage. In contrast, the negative voltage converter in the form of a charge pump does not require an additional reference signal and has the advantages of low difficulty in circuit design, low manufacturing cost, and small layout area.

The main purpose of the present invention is to provide a negative voltage charge pump system, which generates a negative voltage through the first negative voltage pump and the second negative voltage pump, and can pass through the first bypass transistor and the second bypass transistor respectively The first negative voltage pump and the second negative voltage pump are bypassed to have more diverse applications.

A negative voltage charge pump system of the present invention comprises a first negative voltage generating unit, a second negative voltage generating unit and a feedback circuit, the first negative voltage generating unit has a first negative voltage pump, a first negative voltage generating unit A negative voltage level shifter, a first bypass transistor and a first four-phase non-overlapping clock generator, a first voltage input terminal of the first negative voltage pump receives an input voltage, and the One of the first voltage output terminals of the first negative voltage pump outputs a first output negative voltage, and the first negative voltage level shifter is used to generate a first bypass control voltage, and one of the first bypass transistors is first An input end is electrically connected to the first voltage input end of the first negative voltage pump, and a first control end of the first bypass transistor is electrically connected to the first negative voltage level shifter to receive the first negative voltage level shifter. A bypass control voltage, a first output terminal of the first bypass transistor is electrically connected to the first voltage output terminal of the first negative voltage pump, the first four-phase non-overlapping clock generator circuit connected to the first negative voltage pump, and the first four-phase non-overlapping clock generator receives a feedback signal and outputs a plurality of first clock signals to the first negative voltage pump for control. The two negative voltage generating units have a second negative voltage pump, a second negative voltage level shifter, a second bypass transistor and a second four-phase non-overlapping clock generator, the second negative voltage A second voltage input terminal of the pump is electrically connected to the first voltage output terminal of the first negative voltage pump to receive the first output negative voltage, and a second voltage output terminal of the second negative voltage pump Outputting a second output negative voltage, the second negative voltage level shifter is used to generate a second bypass control voltage, a second input end of the second bypass transistor is electrically connected to the second negative voltage pump The second voltage input terminal, the second control terminal of the second bypass transistor is electrically connected to the second negative voltage level shifter to receive the second bypass control voltage, the second bypass transistor A second output terminal is electrically connected to the second voltage output terminal of the second negative voltage pump, the second four-phase non-overlapping clock generator is electrically connected to the second negative voltage pump, and the The second four-phase non-overlapping clock generator receives the feedback signal and outputs a plurality of second clock signals to the second negative voltage pump for control, and the feedback circuit is electrically connected to the first and second negative voltages A generating unit, the feedback circuit receives the second output negative voltage of the second negative voltage pump, and the feedback circuit outputs the feedback signal to the first and second four-phase non-overlapping clock generators.

In the present invention, the first negative voltage generating unit and the second negative voltage generating unit generate a negative voltage, and the first bypass transistor and the second bypass transistor enable the circuit to use the first negative voltage The pump and the second negative voltage pump are bypassed to change the magnitude of the output negative voltage, increasing the multiple applicability of the negative voltage charge pump system.

Please refer to Fig. 1, which is a first embodiment of the present invention, a block diagram of a negative voltage charge pump system NCP, in this embodiment, the negative voltage charge pump system NCP has a first negative voltage generator The unit 100 , a second negative voltage generating unit 200 and a feedback circuit 300 . The first negative voltage generating unit 100 receives an input voltage Vin and outputs a first output negative voltage Vo1, and the second negative voltage generating unit 200 is electrically connected to the first negative voltage generating unit 100 to receive the first output negative voltage. Vo1 and output a second output negative voltage Vo2, the feedback circuit 300 is electrically connected to the first and second negative voltage generating units 100, 200, the feedback circuit 300 receives the second negative voltage pump 210 The negative voltage Vo2 is output, and the feedback circuit 300 outputs a feedback signal Sf to the first and second negative voltage generating units 100, 200.

Please refer to FIG. 1, the first negative voltage generating unit 100 has a first negative voltage pump 110, a first negative voltage level shifter 120, a first bypass transistor 130 and a first four-phase inverter. In the overlapping clock generator 140, a first voltage input terminal in1 of the first negative voltage pump 110 receives the input voltage Vin, and a first voltage output terminal ot1 of the first negative voltage pump 110 outputs the first - Output negative voltage Vo1. The first negative voltage level shifter 120 is used to generate a first bypass control voltage S1, and a first input terminal of the first bypass transistor 130 is electrically connected to the first negative voltage pump 110. A voltage input terminal in1, a first control terminal of the first bypass transistor 130 is electrically connected to the first negative voltage level shifter 120 to receive the first bypass control voltage S1, the first bypass transistor A first output terminal of the crystal 130 is electrically connected to the first voltage output terminal ot1 of the first negative voltage pump 110 . The first four-phase non-overlapping clock generator 140 is electrically connected to the first negative voltage pump 110 and the feedback circuit 300, and the first four-phase non-overlapping clock generator 140 receives the feedback signal Sf also outputs a plurality of first clock signals clk11-clk14 to the first negative voltage pump 110 for control, so that the first negative voltage pump 110 outputs a negative voltage.

In this embodiment, the first bypass transistor 130 is an NMOS high voltage transistor, the first input end of the first bypass transistor 130 is a drain, and the first bypass transistor 130 The first control terminal is the gate, the first output terminal of the first bypass transistor 130 is the source, and the first input terminal is only electrically connected to the first voltage input of the first negative voltage pump 110 terminal in1.

The second negative voltage generating unit 200 has a second negative voltage pump 210, a second negative voltage level shifter 220, a second bypass transistor 230 and a second four-phase non-overlapping clock generator 240. A second voltage input terminal in2 of the second negative voltage pump 210 is electrically connected to the first voltage output terminal ot1 of the first negative voltage pump 110 to receive the first output negative voltage Vo1, and the second negative voltage A second voltage output terminal ot2 of the voltage pump 210 outputs the second output negative voltage Vo2. The second negative voltage level shifter 220 is used to generate a second bypass control voltage S2, and a second input end of the second bypass transistor 230 is electrically connected to the first negative voltage pump 210. Two voltage input terminal in2, a second control terminal of the second bypass transistor 230 is electrically connected to the second negative voltage level shifter 220 to receive the second bypass control voltage S2, the second bypass transistor A second output terminal of the crystal 230 is electrically connected to the second voltage output terminal ot2 of the second negative voltage pump 210 . The second four-phase non-overlapping clock generator 240 is electrically connected to the second negative voltage pump 210, and the second four-phase non-overlapping clock generator 240 receives the feedback signal Sf and outputs a plurality of first Two clock signals clk21-clk24 are sent to the second negative voltage pump 210 for control, so that the second negative voltage pump 210 outputs a negative voltage.

Preferably, the second bypass transistor 230 is an NMOS high voltage transistor, the second input terminal of the second bypass transistor 230 is a drain, and the second bypass transistor 230 The control terminal is a gate, and the second output terminal of the second bypass transistor 230 is a source.

Preferably, since the bases (Bulk) of the first bypass transistor 130 and the second bypass transistor 230 will operate in a negative voltage, the first bypass transistor 130 and the second bypass transistor 130 The structure of the circuit crystal 230 has a deep P-well (Deep P-well) and an N-type buried layer (N+ Buried layer) as an insulating ring to prevent the diodes of the internal PN junction from conducting.

Please refer to Figures 1 and 2, the first negative voltage pump 110 has a first N-type transistor 111, a first auxiliary capacitor 112, a second N-type transistor 113, a first pump capacitor 114, A third N-type transistor 115 , a second auxiliary capacitor 116 , a fourth N-type transistor 117 , a second pump capacitor 118 and a cross-coupled transistor pair 119 . A source of the first N-type transistor 111 receives the input voltage Vin, a gate of the first N-type transistor 111 is electrically connected to a first node n1, and a drain of the first N-type transistor 111 The pole is electrically connected to a second node n2. One end of the first auxiliary capacitor 112 receives one of the first clock signals clk11, and the other end of the first auxiliary capacitor 112 is electrically connected to the first node n1. A gate of the second N-type transistor 113 receives the input voltage Vin, a source of the second N-type transistor 113 is electrically connected to the first node n1, and a drain of the second N-type transistor 113 The pole is electrically connected to the second node n2. One end of the first pump capacitor 114 is electrically connected to the second node n2, and the other end of the first pump capacitor 114 receives one of the first clock signals clk12. A drain of the third N-type transistor 115 receives the input voltage Vin, a gate of the third N-type transistor 115 is electrically connected to a third node n3, a source of the third N-type transistor 115 The pole is electrically connected to a fourth node n4. One end of the second auxiliary capacitor 116 receives one of the first clock signals clk13, and the other end of the second auxiliary capacitor 116 is electrically connected to the third node n3. A gate of the fourth N-type transistor 117 receives the input voltage Vin, a drain of the fourth N-type transistor 117 is electrically connected to the third node n3, a source of the fourth N-type transistor 117 The pole is electrically connected to the fourth node n4. One end of the second pump capacitor 118 is electrically connected to the fourth node n4, and the other end of the second pump capacitor 118 receives one of the first clock signals clk14. The cross-coupled transistor pair 119 is electrically connected to the second node n2 and the fourth node n4, and the cross-coupled transistor pair 119 outputs the first output negative voltage Vo1.

In this embodiment, the cross-coupled transistor pair 119 has a first cross-coupled transistor 119a and a second cross-coupled transistor 119b, and a source of the first cross-coupled transistor 119a is electrically connected to the second At the node n2, one gate of the first cross-coupling transistor 119a is electrically connected to the fourth node n4. One drain of the second cross-coupling transistor 119b is electrically connected to the fourth node n4, one gate of the second cross-coupling transistor 119b is electrically connected to the second node n2, and the second cross-coupling transistor 119b One source is electrically connected to the drain of the first cross-coupling transistor 119a, and the source of the second cross-coupling transistor 119b and the drain of the first cross-coupling transistor 119a output the first Output negative voltage Vo1.

In this embodiment, through the control of the first clock signals clk11-clk14, the first negative voltage pump 110 is operated in the upper and lower stages. Since the circuit operation and signal changes in the upper and lower stages are in a mirror image relationship, only For the description of the previous stage, please refer to page 6 for the timing diagram of the first clock signals clk11-clk14. The last stage can be divided into five periods. In the first period, the input voltage Vin is at low potential, the first clock signals clk11 and clk12 are at low potential, and the first clock signals clk13 and clk14 are at high potential , at this time, the potentials of the first node n1 and the second node n2 are -VDD, the potential of the third node n3 is VDD-Vth, the potential of the fourth node n4 is 0, and the third N-type transistor 115 and the second cross-coupling transistor 119b are turned on to exchange charges, the first N-type transistor 111 and the first cross-coupling transistor 119a are turned off, and the second N-type transistor 113 is also turned on to ensure that the first The N-type transistor 111 and the first cross-coupled transistor 119a are completely turned off. In the second period, the first clock signal clk13 drops to a low potential, at this time, the potential of the third node n3 drops to -Vth and the third N-type transistor 115 is turned off, and the fourth N-type transistor 117 is slightly turned on. In the third period, the first clock signal clk14 drops to a low potential. At this time, the potentials of the third and fourth nodes n3 and n4 drop to -VDD, and the second N-type transistor 113 and the fourth N-type transistor 113 Mode transistor 117 is turned on to ensure that the remaining switches are turned off. In the fourth period, the first clock signal clk12 rises to a high potential, at this time, the potential of the first node n1 rises to -Vth, and the potential of the second node n2 rises to 0. In the fifth period, the first clock signal clk11 rises to a high potential, at this time, the potential of the first node n1 rises to VDD-Vth, the second N-type transistor 113 is turned off, and the first N-type transistor 111 and the first cross-coupling transistor 119a are turned on to exchange charges, thereby enabling the first negative voltage pump 110 to output a negative voltage -VDD.

Preferably, since the bases (Bulk) of the transistors in the first negative voltage pump 110 all operate at negative voltages, the first N-type transistor 111, the second N-type transistor 113, the The structures of the third N-type transistor 115, the fourth N-type transistor 117, the first cross-coupling transistor 119a and the second cross-coupling transistor 119b have a deep P-well (Deep P-well) and a The N-type buried layer (N+ Buried layer) is used as an insulating ring to prevent the diodes of the PN junction from conducting.

Please refer to FIG. 1 , the circuit structure and operation of the second negative voltage pump 210 of the second negative voltage generating unit 200 are the same as those of the first negative voltage pump 110 , so details are not repeated here.

Please refer to Figures 1 and 3, the first negative voltage level shifter 120 has a first high voltage PMOS transistor 121, an inverter 122, a second high voltage PMOS transistor 123, a first high voltage NMOS transistor 124 and a second high voltage NMOS transistor 125 . One source of the first high-voltage PMOS transistor 121 receives a high-potential voltage VH. In this embodiment, the high-potential voltage VH is a power supply voltage VDD, and one gate of the first high-voltage PMOS transistor 121 receives a high-potential voltage VH. The first level shift control signal Bc1. The inverter 122 receives the first level-shift control signal Bc1 and outputs an inverted first level-shift control signal Bc1, a source of the second high voltage PMOS transistor 123 receives the high potential voltage VH, the A gate of the second high voltage PMOS transistor 123 is electrically connected to the inverter 122 to receive the reversed first level shift control signal. A drain of the first high-voltage NMOS transistor 124 is electrically connected to a drain of the first high-voltage PMOS transistor 121, and a gate of the first high-voltage NMOS transistor 124 is electrically connected to the second high-voltage PMOS transistor. A drain of 123 and a source of the first high-voltage NMOS transistor 124 receive a low potential voltage VL. In this embodiment, the low potential voltage VL is the first negative voltage output from the first negative voltage pump 110. Output negative voltage Vo1. A drain of the second high voltage NMOS transistor 125 is electrically connected to a drain of the second high voltage PMOS transistor 123 , and a gate of the second high voltage NMOS transistor 125 is electrically connected to the first high voltage PMOS transistor 121 The drain, the source of the second high-voltage NMOS transistor 125 receives the low potential voltage VL, wherein the drains of the second high-voltage PMOS transistor 123 and the second high-voltage NMOS transistor 125 output the first A bypass control voltage S1 to the gate of the first bypass transistor 130 .

Please refer to FIG. 4, when the first level shift control signal Bc1 is at a high potential, the first high voltage PMOS transistor 121 and the second high voltage NMOS transistor 125 are turned off, and the second high voltage PMOS transistor 123 and the The first high-voltage NMOS transistor 124 is turned on, and at this time, the output first bypass control voltage S1 is the high potential voltage VH. And when the first level-shift control signal Bc1 is at low potential, the first high-voltage PMOS transistor 121 and the second high-voltage NMOS transistor 125 are turned on, and the second high-voltage PMOS transistor 123 and the first high-voltage NMOS transistor are turned on. The crystal 124 is turned off, and at this moment, the outputted first bypass control voltage S1 is the low potential voltage VL. The first negative voltage level shifter 120 is used to convert the first level shift control signal Bc1 whose working range is from 0V~VDD to the first bypass control voltage S1 whose working range is VL~VDD, thereby being used for The first bypass transistor 130 whose base (Bulk) is negative voltage is controlled to be turned on or off.

Preferably, since the bases (Bulk) of the first high-voltage NMOS transistor 124 and the second high-voltage NMOS transistor 125 also operate at negative voltages, the first high-voltage NMOS transistor 124 and the second high-voltage NMOS transistor The structure of the high-voltage NMOS transistor 125 has a deep P-well (Deep P-well) and an N-type buried layer (N+ Buried layer) as an insulating ring to prevent the diodes of the PN junction from conducting.

Please refer to FIG. 1 , the circuit structure and operation of the second negative voltage level shifter 220 of the second negative voltage generating unit 200 are the same as those of the first negative voltage level shifter 120 , so details will not be repeated here.

Please refer to Figure 1, the first bypass transistor 130 and the second bypass transistor 230 are controlled by the first bypass control voltage S1 and the second bypass control voltage S2, so that the first bypass When the pass transistor 130 and the second bypass transistor 230 are turned on, they can respectively bypass the first negative voltage pump 110 and the second negative voltage pump 210, so that the negative voltage charge pump system NCP can selectively Either the first negative voltage pump 110 or the second negative voltage pump 210 is used alone to generate negative voltage, or the first negative voltage pump 110 and the second negative voltage pump 210 are used simultaneously to generate negative voltage.

Please refer to FIG. 1, the feedback circuit 300 has a voltage divider 310, a comparator 320 and a voltage controlled oscillator 330, the voltage divider 310 is electrically connected to the second negative voltage generating unit 200 to receive The second output negative voltage Vo2, and the voltage divider 310 outputs a shunt voltage Vd, the comparator 320 is electrically connected to the voltage divider 310, the comparator 320 receives the shunt voltage Vd and a reference voltage Vr is compared to output a comparison voltage Vc, the voltage-controlled oscillator 330 is electrically connected to the comparator 320 to receive the comparison voltage Vc, and the voltage-controlled oscillator 330 outputs the feedback signal Sf to the first four-phase inverter The overlapping clock generator 140 and the second four-phase non-overlapping clock generator 240 . Controlling the first negative voltage generating unit 100 and the second negative voltage generating unit 200 through the oscillating signal generated by the voltage-controlled oscillator 330 of the feedback circuit 300 as the feedback signal Sf can reduce the first negative voltage The switching loss of the pump 110 and the second negative voltage pump 210 improves the conversion efficiency of the negative voltage charge pump system NCP.

Please refer to FIG. 1. Preferably, the feedback signal Sf is sent to the first four-phase non-overlapping clock generator 140 and the second gate Ad2 through a first sum gate Ad1 and a second sum gate Ad2 respectively. The four-phase non-overlapping clock generator 240, and the first AND gate Ad1 and the second AND gate Ad2 also receive a first activation signal en1 and a second activation signal en2 respectively, and can pass through the first activation signal en1 and the second enable signal en2 selectively turn on or turn off the first negative voltage generating unit 100 and the second negative voltage generating unit 200 .

Please refer to Figures 1 and 5, the first four-phase non-overlapping clock generator 140 receives the output signal of the first AND gate Ad1, because the first enable signal en1 is at a high potential, the first The potential of the output signal of the AND gate Ad1 is the same as the feedback signal Sf, so the input signal in FIG. 5 is represented by the feedback signal Sf. Please refer to FIG. 6 at the same time, through the circuit design in the first four-phase non-overlapping clock generator 140, the upper and lower edges of the first clock signals clk11-14 can be made according to the feedback signal Sf Staggered to generate four groups of non-overlapping first clock signals clk11-14, and then control the first negative voltage pump 110 by the non-overlapping first clock signals clk11-14 to avoid simultaneous conduction power consumption. Since there are many forms of circuit designs that can realize the first clock signals clk11-14, the circuit structure in FIG. 5 is only an embodiment of this case, and is not a limitation of this case.

Please refer to FIG. 7, which is a second embodiment of the present invention. The difference from the first embodiment is that the negative voltage charge pump system NCP has a third negative voltage generating unit 400 and a fourth negative voltage The generation unit 500 can provide a larger negative voltage, and through the setting of these bypass transistors 130, 230, 430, 530, the desired negative voltage generation unit can be turned on arbitrarily, making the use more flexible.

The present invention uses the first negative voltage generating unit 100 and the second negative voltage generating unit 200 to generate a negative voltage, and uses the first bypass transistor 130 and the second bypass transistor 230 to enable the loop to The first negative voltage pump 110 and the second negative voltage pump 210 are bypassed to change the magnitude of the output negative voltage, increasing the multiple applicability of the negative voltage charge pump system NCP.

The scope of protection of the present invention should be defined by the scope of the appended patent application. Any changes and modifications made by anyone who is familiar with this technology without departing from the spirit and scope of the present invention belong to the scope of protection of the present invention. .

NCP: negative voltage charge pump system 100: the first negative voltage generating unit 110: The first negative voltage pump in1: the first voltage input terminal ot1: the first voltage output terminal 111: The first N-type transistor 112: the first auxiliary capacitor 113: The second N-type transistor 114: First pump capacitor 115: The third N-type transistor 116: the second auxiliary capacitor 117: The fourth N-type transistor 118: Second pump capacitor 119: Cross-coupled transistor pair 119a: first cross-coupled transistor 119b: second cross-coupled transistor 120: the first negative voltage level shifter 121: The first high-voltage PMOS transistor 122: Inverter 123: The second high voltage PMOS transistor 124: The first high-voltage NMOS transistor 125: Second high-voltage NMOS transistor 130: The first bypass transistor 140: The first four-phase non-overlapping clock generator 200: the second negative voltage generating unit 210: Second negative voltage pump in2: the second voltage input terminal ot2: the second voltage output terminal 220: second negative voltage level shifter 230: Second bypass transistor 240: The second four-phase non-overlapping clock generator 300: feedback circuit 310: Voltage divider circuit 320: comparator 330:Voltage Controlled Oscillator VDD: power supply voltage Vin: input voltage Vo1: the first output negative voltage S1: The first bypass control voltage Sf: Feedback signal clk11-clk14: first clock signal Vo2: Second output negative voltage S2: Second bypass control voltage VH: high potential voltage Bc1: first level displacement control signal VL: low potential voltage n1: the first node n2: second node n3: the third node n4: the fourth node Vd: shunt voltage Vr: reference voltage Vc: comparison voltage en1: the first start signal en2: Second start signal 400: the third negative voltage generating unit 430: The third bypass transistor 500: the fourth negative voltage generating unit 530: The fourth bypass transistor clk21-clk24: second clock signal GND: ground potential

Figure 1: A block diagram of a negative voltage charge pump system according to a first embodiment of the present invention. Fig. 2: According to the first embodiment of the present invention, a circuit diagram of a first negative voltage pump. Fig. 3: According to the first embodiment of the present invention, a circuit diagram of a first negative voltage level shifter. Fig. 4: According to the first embodiment of the present invention, the timing diagram of the signal of the first negative voltage level shifter. Fig. 5: According to the first embodiment of the present invention, a circuit diagram of a first four-phase non-overlapping clock generator. FIG. 6: A timing diagram of signals of the first four-phase non-overlapping clock generator according to the first embodiment of the present invention. Fig. 7: A block diagram of a negative voltage charge pump system according to a second embodiment of the present invention.

NCP: negative voltage charge pump system

100: the first negative voltage generating unit

110: The first negative voltage pump

in1: the first voltage input terminal

ot1: the first output terminal

120: the first negative voltage level shifter

130: The first bypass transistor

140: The first four-phase non-overlapping clock generator

200: the second negative voltage generating unit

210: Second negative voltage pump

in2: the second voltage input terminal

ot2: the second output terminal

220: second negative voltage level shifter

230: Second bypass transistor

240: The second four-phase non-overlapping clock generator

300: feedback circuit

310: Voltage divider circuit

320: Comparator

330:Voltage Controlled Oscillator

VDD: power supply voltage

Vin: input voltage

Vo1: the first output negative voltage

S1: The first bypass control voltage

Sf: Feedback signal

clk11-clk14: first clock signal

Vo2: Second output negative voltage

S2: Second bypass control voltage

Bc1: first level displacement control signal

Vd: shunt voltage

Vr: reference voltage

Vc: comparison voltage

en1: the first start signal

en2: Second start signal

clk21-clk24: second clock signal

Claims (10)

A negative voltage charge pump system comprising: A first negative voltage generating unit has a first negative voltage pump, a first negative voltage level shifter, a first bypass transistor and a first four-phase non-overlapping clock generator, the first A first voltage input terminal of a negative voltage pump receives an input voltage, and a first voltage output terminal of the first negative voltage pump outputs a first output negative voltage, and the first negative voltage level shifter is used for A first bypass control voltage is generated, a first input end of the first bypass transistor is electrically connected to the first voltage input end of the first negative voltage pump, and a first input end of the first bypass transistor A control terminal is electrically connected to the first negative voltage level shifter to receive the first bypass control voltage, and a first output terminal of the first bypass transistor is electrically connected to the first negative voltage pump. The first voltage output terminal, the first four-phase non-overlapping clock generator is electrically connected to the first negative voltage pump, and the first four-phase non-overlapping clock generator receives a feedback signal and outputs a complex number a first clock signal to the first negative voltage pump for control; A second negative voltage generating unit has a second negative voltage pump, a second negative voltage level shifter, a second bypass transistor and a second four-phase non-overlapping clock generator, the first One of the second voltage input terminals of the two negative voltage pumps is electrically connected to the first voltage output terminal of the first negative voltage pump to receive the first output negative voltage, and one of the second negative voltage pumps is second The voltage output end outputs a second output negative voltage. The second negative voltage level shifter is used to generate a second bypass control voltage. A second input end of the second bypass transistor is electrically connected to the second negative voltage. The second voltage input terminal of the voltage pump, the second control terminal of the second bypass transistor is electrically connected to the second negative voltage level shifter to receive the second bypass control voltage, the second bypass transistor A second output end of the circuit crystal is electrically connected to the second voltage output end of the second negative voltage pump, and the second four-phase non-overlapping clock generator is electrically connected to the second negative voltage pump , and the second four-phase non-overlapping clock generator receives the feedback signal and outputs a plurality of second clock signals to the second negative voltage pump for control; and A feedback circuit electrically connected to the first and second negative voltage generating units, the feedback circuit receives the second output negative voltage of the second negative voltage pump, and the feedback circuit outputs the feedback signal to the The first and second four-phase non-overlapping clock generators. Such as the negative voltage charge pump system of claim 1, wherein the first bypass transistor is an NMOS high voltage transistor, the first input terminal of the first bypass transistor is a drain, and the first bypass The first control end of the transistor is a gate, the first output end of the first bypass transistor is a source, and the first input end is only electrically connected to the first negative voltage pump. voltage input. Such as the negative voltage charge pump system of claim 2, wherein the second bypass transistor is an NMOS high voltage transistor, the second input terminal of the second bypass transistor is a drain, and the second bypass transistor The second control end of the transistor is a gate, and the second output end of the second bypass transistor is a source. The negative voltage charge pump system according to claim 3, wherein the structure of the first and second bypass transistors has a deep P-well (Deep P-well) and an N-type buried layer (N+ Buried layer). The negative voltage charge pump system according to claim 1, wherein the first negative voltage level shifter has a first high voltage PMOS transistor, an inverter, a second high voltage PMOS transistor, and a first high voltage NMOS transistor and a second high-voltage NMOS transistor, one source of the first high-voltage PMOS transistor receives a high potential voltage, one gate of the first high-voltage PMOS transistor receives a first level shift control signal, and the reverse The device receives the first level shift control signal and outputs the reverse first level shift control signal, one source of the second high voltage PMOS transistor receives the high potential voltage, one of the second high voltage PMOS transistor The gate is electrically connected to the inverter to receive the reversed first level-shift control signal, and the drain of the first high-voltage NMOS transistor is electrically connected to the drain of the first high-voltage PMOS transistor. A gate of the first high-voltage NMOS transistor is electrically connected to a drain of the second high-voltage PMOS transistor, a source of the first high-voltage NMOS transistor receives a low potential voltage, and a gate of the second high-voltage NMOS transistor receives a low potential voltage. A drain is electrically connected to a drain of the second high-voltage PMOS transistor, a gate of the second high-voltage NMOS transistor is electrically connected to the drain of the first high-voltage PMOS transistor, and the second high-voltage NMOS transistor One source receives the low potential voltage, wherein the drains of the second high voltage PMOS transistor and the second high voltage NMOS transistor output the first bypass control voltage. The negative voltage charge pump system according to claim 5, wherein the structure of the first and second high-voltage NMOS transistors has a deep P-well (Deep P-well) and an N-type buried layer (N+ Buried layer). Such as the negative voltage charge pump system of claim 1, wherein the first negative voltage pump has a first N-type transistor, a first auxiliary capacitor, a second N-type transistor, a first pump capacitor, A third N-type transistor, a second auxiliary capacitor, a fourth N-type transistor, a second pump capacitor and a pair of cross-coupled transistors, one source of the first N-type transistor receives the input voltage, a gate of the first N-type transistor is electrically connected to a first node, a drain of the first N-type transistor is electrically connected to a second node, and one end of the first auxiliary capacitor receives the A first clock signal, the other end of the first auxiliary capacitor is electrically connected to the first node, a gate of the second N-type transistor receives the input voltage, a source of the second N-type transistor one pole of the second N-type transistor is electrically connected to the second node, one end of the first pump capacitor is electrically connected to the second node, and the first pump capacitor The other end of the third N-type transistor receives the first clock signal, the drain of the third N-type transistor receives the input voltage, and the gate of the third N-type transistor is electrically connected to a third node. One source of the third N-type transistor is electrically connected to a fourth node, one end of the second auxiliary capacitor receives one of the first clock signals, and the other end of the second auxiliary capacitor is electrically connected to the third node, one gate of the fourth N-type transistor receives the input voltage, one drain of the fourth N-type transistor is electrically connected to the third node, and one source of the fourth N-type transistor is electrically connected to the third node. connected to the fourth node, one end of the second pump capacitor is electrically connected to the fourth node, the other end of the second pump capacitor receives one of the first clock signals, and the cross-coupled transistor is electrically connected to The second node and the fourth node are connected, and the cross-coupled transistor pair outputs the first output negative voltage. The negative voltage charge pump system according to claim 7, wherein the pair of cross-coupled transistors has a first cross-coupled transistor and a second cross-coupled transistor, and a source of the first cross-coupled transistor is electrically connected On the second node, one gate of the first cross-coupling transistor is electrically connected to the fourth node, one drain of the second cross-coupling transistor is electrically connected to the fourth node, and the second cross-coupling transistor A gate is electrically connected to the second node, a source of the second cross-coupled transistor is electrically connected to a drain of the first cross-coupled transistor, and the source of the second cross-coupled transistor And the drain of the first cross-coupling transistor outputs the first output negative voltage. The negative voltage charge pump system according to claim 1, wherein the feedback circuit has a voltage divider circuit, a comparator and a voltage controlled oscillator, and the voltage divider circuit is electrically connected to the second negative voltage generating unit to receiving the second output negative voltage, and the voltage divider circuit outputs a shunt voltage, the comparator is electrically connected to the voltage divider circuit, the comparator receives the shunt voltage and a reference voltage for comparison and outputs a comparison voltage, the voltage controlled oscillator is electrically connected to the comparator to receive the comparison voltage, and the voltage controlled oscillator outputs the feedback signal to the first four-phase non-overlapping clock generator and the second four-phase non-overlapping clock generator Overlapping clock generator. The negative voltage charge pump system according to claim 9, wherein the first four-phase non-overlapping clock generator generates four sets of non-overlapping first clock signals according to the feedback signal.

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