TWI787817B - Manufacture method of semiconductor device - Google Patents

Abstract

A method, for making a semiconductor device, includes forming a first fin over a substrate. The method includes forming a dummy gate stack on the first fin. The method includes forming a first gate spacer along a side of the dummy gate stack. The first gate spacer includes a first dielectric material. The method includes forming a second gate spacer along a side of the first gate spacer. The second gate spacer includes a semiconductor material. The method includes forming a source/drain region in the first fin adjacent the second gate spacer. The method includes removing at least a portion of the second gate spacer to form a void extending between the first gate spacer and the source/drain region.

Description

Manufacturing method of semiconductor element

Some embodiments of the present disclosure relate to semiconductor devices and, in particular, to methods of fabricating non-planar transistors.

Semiconductor components are used in a variety of electronic applications such as personal computers, cell phones, digital cameras and other electronic devices. Semiconductor components are usually manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and components thereon .

The semiconductor industry continues to improve the bulk density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the size of the smallest features, so that more components can be integrated into a given area. However, as the size of the smallest features shrinks, additional issues arise that should be dealt with.

Some embodiments of the present disclosure provide a method of manufacturing a semiconductor device, including: forming a first fin on a substrate; forming a dummy gate stack on the first fin; forming a first gate along one side of the dummy gate stack a spacer, the first gate spacer comprises a first dielectric material; along one side of the first gate spacer, a second gate spacer is formed, the second gate spacer comprises a semiconductor material; a source/ a drain region in the first fin adjacent to the second gate spacer; and removing at least a portion of the second gate spacer to form a gap extending between the first gate spacer and the source/drain region .

Some embodiments of the present disclosure provide a method of manufacturing a semiconductor device, including: forming a first fin and a second fin on a substrate, the first fin and the second fin are adjacent to each other; forming a dummy gate stack on the first fin and the second fin On the fin; along one side of the dummy gate stack, a first gate spacer is formed, the first gate spacer comprising a first dielectric material; along one side of the first gate spacer, a second gate is formed a pole spacer, a second gate spacer comprising a semiconductor material; forming source/drain regions in both the first fin adjacent to the second gate spacer and the second fin, the source/drain region comprising a merged partially between the first fin and the second fin; and removing at least a portion of the second gate spacer to form a gap extending between the first gate spacer and the source/drain region.

Some embodiments of the present disclosure provide a method of manufacturing a semiconductor device, comprising: forming a fin on a substrate; forming a dummy gate stack on the fin; forming a gate spacer along one side of the dummy gate stack, Gate spacers include a first layer formed of a dielectric material, and a second layer formed of a semiconductor material; source/drain regions are formed in fins adjacent to the gate spacers; active gate stacks are used instead of dummy gates and removing at least a portion of the second layer of the gate spacer to form a gap extending between the active gate stack and the source/drain regions.

50: Substrate

50P: area

50N: area

52: fin

56: Isolation area

58: Channel area

60: Dummy dielectric layer

62: Dummy gate layer

64: mask layer

70: Dummy gate dielectric layer

72:Dummy gate

74: mask

80: The first gate spacer layer

82: Shallowly doped source/drain regions

84:Second gate spacer layer

86:First gate spacer

88:Second gate spacer

90: The third gate spacer layer

92: Source/drain region

94: Gap

96: residual spacer

98: Contact etch stop layer

100: FinFET

101: interlayer dielectric layer

104: concave part

106: gate dielectric layer

108: Gate

108A: Lining layer

108B: work function control layer

108C: Filling material

114: dielectric layer

116: Dielectric embolism

1600: method

1602, 1602, 1604, 1606, 1608, 1610, 1612, 1614, 1616, 1618, 1620, 1622, 1624, 1626, 1628: Operation

A-A, B-B, C-C, D-D, E-E: cross section

Aspects of the present disclosure are best understood from the following detailed description, taken in conjunction with the accompanying drawings. Note that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

FIG. 1 is a perspective view of a Fin-Effect Transistor (Field-Effect Transistors; FinFET) according to some embodiments.

2nd, 3rd, 4th, 5th, 6th, 7A, 7B, 7C, 7D, 7E, 8A, 8B, 8C, 8D, 8E, 9A, 9B, 9C, 9D, 9E, 10A, 10B, 10C, 10D, 10E , 11A, 11B, 11C, 11D, 11E, 12A, 12B, 12C, 12D, 12E, 12F, 13A, 13B, 13C, 13D, 13E, 14A, 14B, 14C, 14D, 14E, 15A, 15B, 15C, 15D and Figure 15E is a cross-sectional view of various stages of fabrication of the exemplary FinFET of Figure 1 depicted in accordance with some embodiments.

Figure 16 depicts a flowchart of an exemplary method of fabricating a non-planar transistor device, according to some embodiments.

The following disclosure provides different embodiments or examples for implementing the features of the provided object. Specific examples of components, materials, values, steps, arrangements, etc. are described below to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. Other components, materials, values, steps, arrangements, etc. are contemplated. For example, in the description below, forming a first feature on or over a second feature may include embodiments in which direct contact points between the first and second features are formed, and may also include embodiments in which a direct contact point is formed between the first and second features. Embodiments where additional features are formed such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat element numbers and/or letters in various instances. This repetition is for simplicity and clarity and does not in itself dictate a relationship between the various embodiments or configurations discussed.

In addition, for ease of description, spatially relative terms such as "under", "under", "below", "above", "above" may be used herein to describe Describes the relationship of one element or feature to another element or feature as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

According to some embodiments, a plurality of gate spacers form a Fin Field-Effect Transistor (FinFET), and at least a portion of the gate spacers are removed to form A gap is defined in the FinFET. The gap fills at least a portion of the area that uniformly fills the removed gate spacers and remains in the final FinFET device. The gap can be filled with air, or can be in a vacuum so that the gate and source/drain regions in a FinFET can have a low relative permittivity. The capacitance between the gate and source/drain contacts of the FinFET can thus be reduced, thereby reducing current leakage in the FinFET.

FIG. 1 is a perspective view of a simplified exemplary FinFET (Field-Effect Transistors (FinFETs) 100 according to various embodiments. Some other features of FinFETs (discussed below) are omitted for clarity. The illustrated FinFET can operate with one transistor or multiple transistors (eg, two transistors) electrically connected or coupled in sequence.

A Fin Field Effect Transistor (FinFET) 100 includes a fin 52 extending from a substrate 50 . Isolation regions 56 are disposed on substrate 50 , and fins 52 protrude above and from between adjacent isolation regions 56 . Although the isolation region 56 is described/illustrated as being separate from the substrate 50, as referred to herein, the term "substrate" may be used to mean only a semiconductor substrate or a semiconductor substrate including the isolation region. Furthermore, although fin 52 is depicted as a single continuous material of substrate 50 , fin 52 and/or substrate 50 may comprise a single material or a plurality of materials. Herein, fin 52 refers to a portion extending between adjacent isolation regions 56 .

A gate dielectric layer 106 is located along the sidewalls of the fin 52 and on the top surface of the fin 52 , and a gate 108 is located on the gate dielectric layer 106 . source The drain region 92 is disposed on opposite sides of the fin 52 with respect to the gate dielectric layer 106 and the gate 108 . A first gate spacer 86 separates the source/drain region 92 from the gate dielectric layer 106 and the gate 108 . In embodiments where multiple transistors are formed, source/drain region 92 may be shared among multiple transistors. In embodiments where a single transistor is formed in multiple fins 52, adjacent source/drain regions 92 may be electrically connected, such as by epitaxial growth to synthesize source/drain regions 92, or by combining source/drain Drain region 92 is coupled to the same source/drain contact.

Figure 1 further depicts several reference cross-sections. For example, cross-section A-A is along the portion of isolation region 56 below adjacent source/drain region 92; cross-section B-B is parallel to cross-section A-A and along the longitudinal axis of fin 52; cross-section C-C is parallel to cross-section A-A, and along the portion of isolation region 56 between the combined source/drain regions 92; cross-section D-D is perpendicular to cross-section A-A, and along the longitudinal axis of gate 108; and cross-section E-E is perpendicular to cross-section A-A, and across adjacent source/drain regions 92 . For clarity, the subsequent figures refer to such indicative cross-sections.

Some of the embodiments discussed herein are discussed in the context of FinFETs formed using a gate last process. In other embodiments, a gate-first process may be used. Also, some embodiments contemplate aspects for use in planar components such as planar FETs and/or other non-planar components such as gate-all-around (GAA) transistors.

Figures 2, 3, 4, 5 and 6 illustrate In the formula, a perspective view of an intermediate stage in the manufacture of an exemplary FinFET 100 is shown.

A substrate 50 is provided in FIG. 2 . The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor or a semiconductor-on-insulator (SOI) substrate, etc., and may be doped (eg, with p-type or n-type dopants) or undoped. . The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, or a silicon oxide layer. An insulating layer is provided on a substrate, usually a silicon or glass substrate. Other substrates, such as multilayer substrates or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors include silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors include SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof.

The substrate 50 has a region 50N and a region 50P. The region 50N can be used to form an n-type element, such as an N-type Metal-Oxide-Semiconductor (NMOS) transistor, such as an n-type FinFET. The region 50P can be used to form a p-type element, such as a P-type metal-oxide-semiconductor (NMOS) transistor, such as a p-type FinFET. Region 50N may be physically separated from region 50P, and may be provided between region 50N and region 50P Any number of component features (eg, other active components, doped regions, isolation structures, etc.).

As shown in FIG. 3 , fins 52 are formed in substrate 50 . Fin 52 is a semiconductor strip. In some embodiments, the fins 52 may be formed in the substrate 50 by etching trenches in the substrate 50 . Etching can be any acceptable etching process, such as reactive ion etch (reactive ion etch; RIE), neutral beam etch (neutral beam etch; NBE), etc. or a combination thereof. Etching can be anisotropic.

Fins 52 may be patterned by any suitable method. For example, one or more photolithography processes may be used to pattern the fins 52, including a double patterning process or a multiple patterning process. Typically, a double or multiple patterning process combines photolithography and self-alignment processes to create, for example, patterns with pitches that are smaller than achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. Next, the sacrificial layer is removed, and the remaining spacers can be used to pattern the fins.

In FIG. 4 , isolation regions 56 (sometimes referred to as shallow trench isolation (STI) regions 56 ) are formed on the substrate 50 and between adjacent fins 52 . As an example of forming STI region 56 , an insulating material is formed on the intermediate structure. The insulating material can be an oxide, such as silicon oxide, nitride, etc., or a combination thereof, and can be deposited by high density plasma chemical vapor deposition (high density plasma chemical vapor deposition; HDP-CVD), flowable chemical vapor deposition (FCVD) (e.g., chemical vapor deposition (CVD) deposition of substrate material in a remote plasma system and post-cure to transform it into another materials, such as oxides) or a combination thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the insulating material is silicon oxide formed by FCVD process. Once the insulating material is formed, an annealing process may be performed. In one embodiment, the insulating material is formed such that excess insulating material covers the fins 52 . Multiple layers may be utilized in some embodiments. For example, in some embodiments, liners (not shown) may be formed along the surface of the substrate 50 and the fins 52 first. Thereafter, the fill material discussed above may be formed on the liner. A removal process is applied to the insulating material to remove excess insulating material on the fins 52 . In some embodiments, a planarization process such as chemical mechanical polish (CMP), etch back process, combinations of the foregoing, etc. may be used. The planarization process exposes the fins 52 such that the top surfaces of the fins 52 and the insulating material are coplanar after the planarization process is completed. Next, the insulating material is recessed, and the remaining portion of the insulating material forms the STI region 56 . The insulating material is recessed such that upper portions of fins 52 in regions 50N and 50P protrude from between adjacent STI regions 56 . Additionally, the top surface of the STI region 56 may have a flat surface as shown, a convex surface, a concave surface (eg, a depression), or a combination thereof. The top surface of STI region 56 may be recessed, raised and/or recessed by a suitable etching process. STI region 56 may be recessed using an acceptable etch process, such as for insulating The material of the material has a selective etch process (eg, the material of the insulating material etches the material of the insulating material at a faster rate than the material of the fin 52 ). For example, chemical oxide removal may use a suitable etch process such as dilute hydrofluoric (dHF) acid.

The above process is just one example of how the fins 52 are formed. In some embodiments, the fins can be formed by an epitaxial growth process. For example, a dielectric layer may be formed on the top surface of the substrate 50 and trenches may be etched into the dielectric layer to expose the underlying substrate 50 . The epitaxial structure can be epitaxially grown in the trench, and the dielectric layer can be recessed such that the epitaxial structure protrudes from the dielectric layer to form a fin. Additionally, in some embodiments, a heteroepitaxy structure may be used for fins 52 . For example, after the insulating material of STI region 56 is planarized with fin 52 , fin 52 may be recessed, and a material other than fin 52 may be epitaxially grown over recessed fin 52 . In such an embodiment, the fin 52 includes a recessed material and a material epitaxially grown on the recessed material. In such other embodiments, a dielectric layer may be formed on the top surface of the substrate 50 and trenches may be etched through the dielectric layer. Next, a heteroepitaxy structure can be epitaxially grown in the trench using a material different from the substrate 50 , and the dielectric layer can be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 52 . In some embodiments where the epitaxially grown homoepitaxial structure or heteroepitaxy structure can be used together, the epitaxially grown material can be doped in situ during the growth process, combining prior and subsequent implant.

Still further, it may be advantageous to epitaxially grow a different material in region 50N (eg, NMOS region) than in region 50P (eg, PMOS region). In various embodiments, the upper portion of fin 52 may be made of silicon germanium (SixGe1 _{-x ,} where x may range from 0 to 1), silicon carbide, pure or substantially pure germanium, III Group to Group V compound semiconductors, Group II to Group VI compound semiconductors, etc. For example, usable materials forming Group III to Group V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.

Additionally, suitable wells (not shown) may be formed in fin 52 and/or substrate 50 . In some embodiments, a P-well may be formed in region 50N and an N-well may be formed in region 50P. In some embodiments, a P-well or an N-well is formed in both region 50N and region 50P.

In different well type embodiments, photoresists or other masks (not shown) may be used to implement different implant steps for regions 50N and 50P. For example, a photoresist may be formed over fin 52 and STI region 56 in region 50N. The photoresist is patterned to expose a region 50P of the substrate 50 , such as a PMOS region. The photoresist may be formed through the use of spin coating techniques and may be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in region 50P, and the photoresist can be used as a mask to substantially prevent n-type impurity implantation into region 50N, such as an NMOS region. The n-type impurities may be implanted into the phosphorus, arsenic, antimony, etc. in the region at a concentration equal to or less than 10 ¹⁸ cm ⁻³ , for example between about 10 ¹⁷ cm ⁻³ and about 10 ¹⁸ cm ⁻³ . After implantation, the photoresist is removed via, for example, an acceptable ashing process.

After region 50P is implanted, a photoresist is formed over fin 52 and STI region 56 in region 50P. The photoresist is patterned to expose a region 50N of the substrate 50 , such as an NMOS region. The photoresist may be formed through the use of spin coating techniques and may be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation is performed in region 50N, and the photoresist can be used as a mask to substantially prevent p-type impurity implantation into region 50P, such as a PMOS region. The p-type impurity can be implanted into boron, boron difluoride (BF ₂ ), indium, etc. in the region at a concentration equal to or less than 10 ¹⁸ cm ^-3 , for example between about 10 ¹⁷ cm ^-3 and about 10 ¹⁸ cm ^-3 between. After implantation, the photoresist is removed via, for example, an acceptable ashing process.

After the regions 50N and 50P are implanted, an anneal may be performed to activate the implanted p-type impurities and/or n-type impurities. In some embodiments, the growth material of the epitaxial fin can be doped in situ during growth, combined with implantation, although in situ and implant doping can be used together.

In FIG. 5 , a dummy dielectric layer 60 is formed on the fin 52 . The dummy dielectric layer 60 can be, for example, silicon oxide, silicon nitride, or combinations thereof, and is deposited or thermally grown according to acceptable techniques. A dummy gate layer 62 is formed on the dummy dielectric layer 60 , and a mask layer 64 is formed on the dummy gate layer 62 . Dummy gate layer 62 may be deposited on dummy dielectric layer 60 using, for example, CMP, and then planarized. A mask layer 64 may be deposited over the dummy gate layer 62 . The dummy gate layer 62 can be a conductive material, and can be selected from amorphous silicon, polysilicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides and metal groups. Dummy gate layer 62 may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques known in the art and used to deposit conductive materials. The dummy gate layer 62 may be made of other materials that have high etch selectivity to the etching of the isolation regions. The mask layer 64 may include, for example, SiN or SiON. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed across the regions 50N and 50P. It should be noted that the dummy dielectric layer 60 is shown covering only the fins 52 for illustration purposes only. In some embodiments, dummy dielectric layer 60 may be deposited such that dummy dielectric layer 60 covers STI region 56 , extending between dummy gate layer 62 and STI region 56 .

In FIG. 6, mask layer 64 is patterned to form mask 74 using acceptable photolithography and etching techniques. The pattern of mask 74 is then transferred to dummy gate layer 62 by acceptable etching techniques to form dummy gate 72 . The pattern of the mask 74 is further transferred to the dummy dielectric layer 60 to form the dummy gate dielectric layer 70 . Dummy gates 72 cover individual channel regions of fins 52 . The dummy gate dielectric layer 70 and the dummy gate 72 are sometimes collectively referred to as a "dummy gate stack". The pattern of mask 74 may be used to physically separate each dummy gate 72 from adjacent dummy gates. The dummy gates 72 may also have a length direction substantially perpendicular to the length direction of each epitaxial fin 52 .

7A-15E are cross-sectional views of more intermediate stages in the fabrication of FET 10, according to some embodiments. Figure 7A to Figure Figure 15E depicts features of either of regions 50N and 50P. For example, the depicted structure may apply to both region 50N and region 50P. Structural differences, if any, between regions 50N and 50P are described in the text accompanying each figure. In a brief overview, Figure 7A, Figure 8A, Figure 9A, Figure 10A, Figure 11A, Figure 12A, Figure 13A, Figure 14A are drawn along the reference cross-section A-A shown in Figure 1 and Fig. 15A; Fig. 7B, Fig. 8B, Fig. 9B, Fig. 10B, Fig. 11B, Fig. 12B, Fig. 13B, Fig. 14B are drawn along the reference cross section B-B shown in Fig. 1 and Fig. 15B; Fig. 7C, Fig. 8C, Fig. 9C, Fig. 10C, Fig. 11C, Fig. 12C, Fig. 13C, Fig. 14C are drawn along the reference cross section C-C shown in Fig. 1 and Figure 15C; Figure 7D, Figure 8D, Figure 9D, Figure 10D, Figure 11D, Figure 12D, Figure 13D, Figure 14D along the reference cross section D-D shown in Figure 1 and Fig. 15D; and Fig. 7E, Fig. 8E, Fig. 9E, Fig. 10E, Fig. 11E, Fig. 12E, Fig. 13E, Fig. 14E along the reference cross section E-E shown in Fig. 1 Figures and Figure 15E.

In FIGS. 7A-7E , first gate spacer layer 80 is formed on exposed surfaces of mask 74 , dummy gate 72 , dummy gate dielectric layer 70 , STI region 56 , and/or fin 52 . The first gate spacer layer 80 is formed of a dielectric material such as silicon nitride, silicon carbon nitride, silicon oxycarbonitride, silicon oxycarbide, silicon, metal oxide, etc., or a combination thereof, and may be By such as CVD, or plasma chemical vapor deposition (Plasma-Enhanced CVD; PECVD) and other conformal deposition processes.

After forming the first gate spacer layer 80 , implantation of lightly doped source/drain (LDD) regions 82 is performed. In a different element type implementation, a mask such as a photoresist may be formed over region 50N while exposing region 50P, and an appropriate type (eg, p-type) impurity may be implanted into fin 52 exposed in region 50P. Next, the mask can be removed. Subsequently, a mask, such as a photoresist, may be formed over region 50P while exposing region 50N, and an appropriate type of impurity (eg, n-type) may be implanted into fin 52 exposed in region 50N. Next, the mask can be removed. The n-type impurity can be any n-type impurity discussed previously, and the p-type impurity can be any p-type impurity discussed previously. The lightly doped source/drain regions may have an impurity concentration of about 10 ¹⁵ cm ⁻³ to about 10 ¹⁶ cm ⁻³ . Annealing can be used to activate the implanted impurities.

After forming the LDD regions 82 , a second gate spacer layer 84 is formed over the first gate spacer layer 80 . The second gate spacer layer 84 is formed of a semiconductor material such as Si _1-x Ge _x containing less than 50% Ge in molar ratio (x<0.5). For example, in the second gate spacer layer 84 of Si _1-x Ge _x , Ge may comprise a molar ratio of about 10% to 40%. The second gate spacer layer 84 is formed by a conformal deposition process such as molecular beam deposition (Molecular-Beam Deposition; MBD), atomic layer deposition (Atomic Layer Deposition; ALD) and plasma chemical vapor deposition (Plasma-Enhanced CVD; PECVD). ) and so on. The second gate spacer layer 84 is doped, and may be doped with n-type impurities (eg, phosphorus) or p-type impurities (eg, boron). As shown, the second gate spacer layer 84 is a different material than the first gate spacer layer 80 . The second gate spacer layer 84 and the first gate spacer layer 80 have high etch selectivity in the same etching process, for example, the etching rate of the second gate spacer layer 84 is greater than that of the first gate spacer layer 80 the etching rate. In some embodiments, the second gate spacer layer 84 may be doped in a subsequent process, thereby further improving the etching selectivity between the second gate spacer layer 84 and the first gate spacer layer 80, Further discussion is provided below.

After forming the second gate spacer layer 84 , a third gate spacer layer 90 is formed over the second gate spacer layer 84 . The third gate spacer layer 90 is formed from a dielectric material selected from the candidate dielectric materials of the first gate spacer layer 80 and possibly from a method selected from the candidate methods of forming the first gate spacer layer 80 Formed, or can be formed by different methods. In some other embodiments, the third gate spacer layer 90 is formed of a different material than the first gate spacer layer 80 . Specifically, the third gate spacer layer 90 may have high etch selectivity to the first gate spacer layer 80 . As will be discussed further below, the third gate spacer layer 90 is also doped in subsequent processing, further increasing the etch selectivity between the third gate spacer layer 90 and the first gate spacer layer 80 sex.

In FIGS. 8A-8E , epitaxial source/drain regions 92 are formed in fins 52 to apply stress to respective channel regions 58 from and improve execution. Epitaxial source/drain regions 92 are formed in fins 52 such that each dummy gate 72 is disposed between adjacent pairs of epitaxial source/drain regions 92 . In some embodiments, the epitaxial source/drain region 92 may extend into the fin 52 or may pass through the fin 52 . First gate spacer layer 80 , second gate spacer layer 84 , and third gate spacer layer 90 may be used to separate epitaxial source/drain regions 92 from dummy gates 72 by a suitable lateral distance, Such that the epitaxial source/drain regions 92 do not short-circuit the gates of subsequently formed FinFETs.

Epitaxial source/drain regions 92, such as NMOS regions, in region 50N may be formed in fin 52 via mask region 50P, such as a PMOS region, and etching the source/drain regions of fin 52 in region 50N. sunken. Source/drain regions 92 in region 50N are then epitaxially grown in the recess. Epitaxial source/drain regions 92 may comprise any acceptable material, such as a material suitable for n-type FinFETs. For example, if fin 52 is silicon, epitaxial source/drain region 92 in region 50N may include a material that imparts tensile strain in channel region 58 , such as silicon, SiC, SiCP, or SiP, among others. Epitaxial source/drain regions 92 in region 50N may have surfaces raised from corresponding surfaces of fins 52 and may have facets.

Epitaxial source/drain regions 92, such as PMOS regions, in region 50P may be formed in fin 52 via masking region 50N, such as an NMOS region, and etching the source/drain regions of fin 52 in region 50P. sunken. Source/drain regions 92 in region 50P are then epitaxially grown in the recess. Epitaxial source/drain regions 92 may include any Any acceptable materials, such as those suitable for p-type FinFETs. For example, if fin 52 is silicon, epitaxial source/drain region 92 in region 50P may include a material that imparts tensile strain in channel region 58 , such as silicon, SiC, SiCP, or SiP, among others. Epitaxial source/drain regions 92 in region 50P may have surfaces raised from corresponding surfaces of fins 52 and may have facets.

In some embodiments, the third gate spacer layer 90 is formed before the source/drain regions 92, and the third gate spacer layer 90 may be formed in each region. For example, third gate spacer layer 90 may be formed with epitaxial source/drain regions 92 in region 50N while region 50P is masked, and third gate spacer layer 90 may be formed with epitaxial source/drain regions 92 in region 50P. Epitaxial source/drain regions 92 are formed together, while region 50N is masked. During recessing of the source/drain regions of fin 52, third gate spacer layer 90 acts as an additional etch mask, protecting second gate spacer layer 84 while etching the source/drain regions of fin 52. the vertical portion of the . Therefore, source/drain recesses can be formed with greater depth and narrower width.

During recessing of the source/drain regions of fin 52 , first gate spacer layer 80 , second gate spacer layer 84 , and third gate spacer layer 90 are etched. Openings are formed in the first gate spacer layer 80 , the second gate spacer layer 84 and the third gate spacer layer 90 exposing the source/drain regions of the fin 52 and extending to the fin 52 to form recesses for the epitaxial source/drain regions 92 . Etching may be, for example, anisotropic etching, such as dry etching. first gate spacer layer 80, The second gate spacer layer 84, and the third gate spacer layer 90 may (or may not) be etched in different processes.

Dopants may be implanted into epitaxial source/drain regions 92 and/or fins 52 followed by annealing similar to the previously discussed process for forming shallowly doped source/drain regions. The source/drain regions may have an impurity concentration of about 10 ¹⁹ cm ⁻³ to about 10 ²¹ cm ⁻³ . The n-type and/or p-type impurities of the source/drain regions can be any of the impurities discussed previously. In some embodiments, epitaxial source/drain regions 92 may be doped in situ during growth.

The epitaxial process is used to thus form epitaxial source/drain regions in regions 50N and 50P, the upper surfaces of the epitaxial source/drain regions have junctions extending laterally outward beyond the sidewalls of fins 52 . In some embodiments, as shown, these junctions result in the merging of adjacent epitaxial source/drain regions of the same FinFET. A gap 94 may be formed below the merged epitaxial source/drain region 92 between adjacent fins 52, as better shown in FIG. 8E. Two or more adjacent regions may merge. In other embodiments (discussed further below), adjacent epitaxial source/drain regions 92 remain separated after the epitaxial process is complete. In cross-sectional views cut over isolation region 56 and between fins 52 (e.g., FIG. 8A, and FIGS. 9A, 10A, 11A, 12A, 13A, 15A), a remaining portion of the third gate spacer layer 90 can be observed, for example, extending along (physically contacting) the bottom surface and at least one sidewall of the source/drain region. However, it should be understood that the remaining portion of the third gate spacer layer 90 may be Etching, for example, forms part of the gap 94, however remains within the scope of this disclosure.

During doping of the epitaxial source/drain regions 92 , the first gate spacer layer 80 , the second gate spacer layer 84 and the third gate spacer layer 90 may also be doped. For example, when doping by implantation, some impurities may be implanted into various spacers. Also, when in-situ doping is performed during growth, various spacers can be exposed to the dopant precursors of the epitaxial process. Since the third gate spacer layer 90 covers the second gate spacer layer 84 , the second gate spacer layer 84 may have a lower dopant concentration than the third gate spacer layer 90 . Likewise, since the second gate spacer layer 84 covers the first gate spacer layer 80 , the first gate spacer layer 80 may have a lower dopant concentration than the second gate spacer layer 84 . In addition, some regions (eg, upper regions) of the first gate spacer layer 80, the second gate spacer layer 84, and the third gate spacer layer 90 may be doped more heavily than other regions of the spacer layers (eg, Lower region) higher impurity concentration. Due to the masking step described above, the first gate spacer layer 80, the second gate spacer layer 84, and the third gate spacer layer 90 in region 50N are doped with the same doping as the epitaxial source/drain. Impurities. Likewise, first gate spacer layer 80 , second gate spacer layer 84 , and third gate spacer layer 90 in region 50P are doped with the same impurities as the epitaxial source/drain. In this way, the conductivity type (eg, majority carrier type) of each epitaxial source/drain region 92 is compatible with the first gate spacer layer 80, the second gate electrode adjacent to the source/drain region 92. Parts of the spacer layer 84 and the third gate spacer layer 90 are identical.

After forming epitaxial source/drain regions 92, the remaining portions of first gate spacer layer 80 and second gate spacer layer 84 form first gate spacer 86 and second gate spacer 88, respectively. . In addition, the third gate spacer layer 90 may be partially removed. It can be removed by a suitable etching process, such as wet etching using hot phosphoric acid (H ₃ PO ₄ ). In some embodiments, after removal, a remnant portion of third gate spacer layer 90 remains, the remnant portion being disposed between second gate spacer 88 and the raised surface of epitaxial source/drain region 92 between, and in the gap 94 of the epitaxial source/drain region 92 . The remnants of the third gate spacer layer 90 are referred to as remnant spacers 96 .

In FIGS. 9A-9E , contact etch stop layer (CESL) 98 is formed along second gate spacers 88 and between epitaxial source/drain regions 92 and residual spacers 96 above. CESL 98 may be formed from a dielectric material selected from among the candidate dielectric materials for first gate spacer layer 80 ( 86 ) or may include a different dielectric material. CESL 98 may be formed by a method selected from the candidate methods for forming first gate spacer layer 80 , or may be formed by a different method. As shown, CESL 98 is formed of a different material than second gate spacer layer 84 (second gate spacer 88 ). The second gate spacer layer 84 and the CESL 98 have high etch selectivity in the same etching process, eg, the etch rate of the second gate spacer layer 84 is greater than that of the CESL 98 . In some embodiments, CESL 98 and first gate spacer layer 80 are formed of the same dielectric material.

Additionally, a first interlayer dielectric (ILD) 101 is deposited over CESL 98 . ILD 101 may be formed from a dielectric material and may be by any suitable method such as CVD, plasma chemical vapor deposition (PECVD), or FCVD. The dielectric material may include Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Phospho-Doped Phospho-Silicate Glass (BPSG), or undoped Miscellaneous silicate glass (urdoped Silicate Glass; USG) and so on. Other insulating materials may be formed using any acceptable method.

In FIGS. 10A-10E , a planarization process such as chemical mechanical polishing (CMP) may be performed to make the top surface of ILD 101 coplanar with the top surface of dummy gate 72 or mask 74 . The planarization process removes portions of CESL 98 over mask 74 and may also remove dummy gate 72 over mask 74 . After the planarization process, the top surface of the dummy gate 72 , the first gate spacer 86 , the second gate spacer 88 , the CESL 98 and the ILD 101 are coplanar. Thus, the top surface of dummy gate 72 is exposed through ILD 101 . In some implementations, mask 74 may remain, in which case the planarization process makes the top surface of ILD 101 coplanar with the top surface of mask 74 .

Referring to FIGS. 11A-11E , dummy gate 72 and mask 74 (if present) are removed in one or more etching steps, thereby forming recess 104 . The dummy gate dielectric layer 70 in the recess 104 may also be removed. In some embodiments, only the dummy gate 72 is removed, And the dummy gate dielectric layer 70 remains and is exposed by the concave portion 104 . In some embodiments, the dummy gate dielectric layer 70 is removed from the recess 104 in a first region of the die (eg, the core logic region) and remains in a second region of the die (eg, the input/output area) in the recess 104. In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate 72 without etching the first gate spacer 86, the second gate spacer 88, the CESL 98, or ILD 101. Each recess 104 exposes the channel region 58 of the corresponding fin 52 . Each channel region 58 is disposed between adjacent pairs of epitaxial source/drain regions 92 . During removal, dummy gate dielectric layer 70 may serve as an etch stop layer when dummy gate 72 is etched. Then, after dummy gate 72 is removed, dummy gate dielectric layer 70 may be selectively removed.

In FIGS. 12A-12E , a gate dielectric layer 106 and a gate 108 are formed to replace the gate. Figure 12F shows a detailed view of the area 11 of Figure 12B. A gate dielectric layer 106 is conformally deposited in the recess 104 , eg, on the top surface and sidewalls of the fin 52 , and on the sidewalls of the first gate spacer 86 . A gate dielectric layer 106 may be formed on the top surface of the ILD 101 . According to some embodiments, the gate dielectric layer 106 includes silicon oxide, silicon nitride, or multiple layers thereof. In some embodiments, the gate dielectric layer 106 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 106 may have a k value greater than about 7.0 and may include Hf, Al, Zr, Metal oxides or silicates of La, Mg, Ba, Ti, Pb and combinations thereof. The forming method of the gate dielectric layer 106 may include molecular beam deposition (MBD), ALD, and PECVD. In embodiments where the dummy gate dielectric layer 70 remains in the recess 104 , the gate dielectric layer 106 includes the material of the dummy gate dielectric layer 70 (eg, SiO ₂ ).

The gates 108 are respectively deposited on the gate dielectric layer 106 and fill the remaining portion of the recess 104 . The gate 108 may include, for example, TiN, TiO, TaN, TaC, Co, Ru, Al, W, combinations thereof, or multiple layers thereof. For example, although a single-layer gate 108 is shown in FIGS. 12A to 12D, the gate 108 may include any number of liner layers 108A, any number of work function modulation layers 108B, and filling materials 108C, as shown in FIG. 12F. As shown in the figure. After filling the gate 108 , an implantation process such as CMP may be performed to remove excess portions of the gate dielectric layer 106 and the material of the gate 108 , wherein the excess portions are above the top surface of the ILD 101 . The remaining portion of the material of gate 108 and gate dielectric layer 106 thus forms the replacement gate of the resulting FinFET. Gate 108 and gate dielectric layer 106 are sometimes collectively referred to as an "active gate stack." Active gate stacks may extend along sidewalls of channel region 58 of fin 52 .

The formation of the gate dielectric layer 106 in the region 50N and the region 50P may occur simultaneously, so the gate dielectric layer 106 in each region is formed of the same material, and the formation of the gate electrode 108 may occur simultaneously, The gates 108 in each region are thus formed from the same material. In some embodiments, the gate dielectric layer 106 in each region may be formed by a different process, so the gate dielectric layer 106 may be different. materials, and/or the gates 108 in each region may be formed by different processes, so the gates 108 may be of different materials. When using different processes, various masking steps can be used to mask and expose the appropriate areas.

In FIGS. 13A-13E , the second gate spacer 88 is removed so that the gap 94 extends along the active gate stack. According to various embodiments, because of the high etch selectivity between the second gate spacer 88 and both the first gate spacer 86 and the residual spacer 96, when the second gate spacer 88 is removed, the first Gate spacers 86 and residual spacers 96 may remain substantially intact. Thus, gap 94 may inherit the size and profile of second gate spacer 88 , which may have a conformal spacing along gap 94 . In some other embodiments, when the second gate spacer 88 is removed, adjacent layers/features along the gap 94 (e.g., first gate spacer 86, residual spacer 96, CESL 98) are also etched, but Significantly less. Accordingly, the gaps 94 may exhibit non-uniform spacing along the gaps 94 . For example, the etch selectivity between the gate spacers (first gate spacer 86 and second gate spacer 88 ), and between second gate spacer 88 and residual spacer 96 may be different, This may result in gaps 94 having different pitches at different intervals.

As described in FIG. 8A , the residual spacer 96 may keep the bottom surface and sidewalls of the merged portion of the adjacent source/drain regions 92 extended when the source/drain regions 92 are formed. In this way, the residual spacer 96 can further protect the source/drain region 92 when the second gate spacer 88 is removed. In addition, because the second gate spacer 88, ILD 101 between With high etch selectivity, ILD 101 remains substantially intact even though a protective mask is not formed on top of ILD 101 . After removal, gap 94 separates the active gate stack from epitaxial source/drain regions 92 . Specifically, gap 94 physically separates portions of first gate spacer 86 from CESL 98 and ILD 101 .

The second gate spacers 88 are removed by one or more etching processes. As described above, the material of the second gate spacer 88 has a high etch selectivity relative to the materials of the first gate spacer 86 , the residual spacer 96 , and the ILD 101 . Thus, the etch process may etch the material of the second gate spacers 88 at a faster rate than the materials of the first gate spacers 86 , the residual spacers 96 , and the ILD 101 .

In some embodiments, the etch process is a single etch process. The single etch process may include a dry etch process using a plasma, such as a fluorine-containing plasma using hydrogen fluoride (HF) gas and/or fluorine gas (F ₂ ). HF can assist in partially removing Ge due to the migration of hydrogen atoms. The etching process includes performing at a temperature below about 50°C, specifically below about 40°C, and more specifically in a range of about 25°C to 35°C. When the gap 94 extends along the active gate stack, the active gate stack has less lateral support. Performing the etch process at low temperature and low pressure can help avoid deformation of the active gate stack when lateral support is lowered.

In some embodiments, the etching process includes multiple etching processes, eg, a first etching process and a second etching process. As described above, when the source/drain region 92 is formed, the second gate spacer 88 may be doped with the impurity of the source/drain region 92 and the upper region may be doped with a higher impurity concentration than the lower region. The first etch process has a faster etch rate at a higher impurity concentration and is used to remove the upper region of the second gate spacer 88, and the second etch process has a faster etch rate at a lower impurity concentration. fast etch rate and is used to remove the lower region of the second gate spacer 88 . Each of the first etching process and the second etching process may include a dry etching process using plasma, such as a fluorine-containing plasma using hydrogen fluoride (HF) gas and/or fluorine gas (F ₂ ). Each of the first etching process and the second etching process is performed below about 50°C, specifically below about 40°C, and more specifically in a range of about 25°C to 35°C.

In some embodiments, region 50P and second gate spacers 88 in region 50P may be removed at different rates. Specifically, the second gate spacer 88 doped with n-type impurities (for example, in the region 50N), compared with the second gate spacer 88 doped with p-type impurities (for example, in the region 50P), will are removed at a faster rate. Accordingly, some residue (not shown) may remain in region 50P, but not in region 50N. The residue may be the dielectric material of the second gate spacer 88 .

In FIGS. 14A-14E , a dielectric layer 114 is formed on the first gate spacer 86 , the ILD 101 , the gate dielectric layer 106 and the gate 108 . The dielectric layer 114 may be formed of a dielectric material such as silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbide, or silicon oxycarbide, and may be formed by a deposition process such as ALD. As shown, dielectric layer 114 partially fills an upper portion of gap 94 . gap 94 It is thus sealed such that material may not be deposited in gap 94 during subsequent processing.

In FIGS. 15A-15E , a planarization process may be performed to remove portions of the dielectric layer 114 overlying the ILD 101 . The planarization process can be grinding or CMP, etc. The remaining portion of dielectric layer 114 forms a dielectric plug 116 that seals gap 94 . After the planarization process, the top surfaces of ILD 101 , dielectric plug 116 , first gate spacer 86 , CESL 98 , gate dielectric layer 106 , and gate 108 are coplanar.

FIG. 16 is a flowchart of a method 1600 for forming non-planar transistor devices according to one or more embodiments of the present disclosure. For example, at least some of the operations (or steps) of method 1600 may be used to form FinFET 100 . However, it should be understood that some of the operations of method 1600 may be used to fabricate any of other various types of non-planar devices, such as nanosheet transistor devices, nanowire transistor devices, vertical transistor devices, or wraparound gate (GAA) transistor elements, etc., but are still included within the scope of this disclosure. It should be noted that the method 1600 is only an example and is not intended to limit the present disclosure. Accordingly, it is understood that additional operations may be provided before, during, and after the method 1600 of FIG. 16, and only some other operations are briefly described herein.

In some embodiments, the operations of method 1600 may be performed in conjunction with FIGS. 2, 3, 4, 5, 6, 7A-7E, 8A-8E, 9A to 9E Figures 10A to 10E, 11A to 11E, 12A to 12E, 13A to 13E, 14A to 14E, and 15A to 15E The cross-sectional views of the exemplary FinFET 100 in various stages of fabrication are associated in FIG.

Method 1600 begins with providing a substrate (eg, substrate 50 of FIG. 2 ) at operation 1602 . Continuing with method 1600 to operation 1604 , a plurality of fins (eg, fins 52 of FIG. 3 ) are formed. Continuing from method 1600 to operation 1606, an isolation region (eg, isolation region 56 of FIG. 4) is formed. Continuing from method 1600 to operation 1608 , dummy dielectric layers, dummy gate layers, and mask layers (eg, dummy dielectric layer 60 , dummy gate layer 62 , and mask layer 64 , respectively, are shown in FIG. 5 ) are formed. Proceeding from method 1600 to operation 1610 , one or more dummy gate stacks (eg, dummy gate dielectric layer 70 and dummy gate 72 of FIG. 6 ) are formed. Continuing with method 1600 to operation 1612, a first gate spacer layer, a second gate spacer layer, and a third gate spacer layer (eg, first gate spacer layer 80, FIG. Second gate spacer layer 84 and third gate spacer layer 90. Continuing with method 1600 to operation 1614, source/drain regions (eg, source/drain regions of FIGS. 8A-8E ) are formed. Continuing from method 1600 to operation 1616, forming an ILD (eg, ILD 101 of FIGS. 9A to 9E).Continuing from method 1600 to operation 1618, performing CMP (eg, from FIGS. 10A to 10E).Continuing from method 1600 to operation 1620, Remove the dummy gate stack (eg, Figures 11A-11E).Continuing with method 1600 to operation 1622, form the gate dielectric layer and gate (eg, Figures 12A-12F Individual gate dielectric layer 106 and gate 108). Continuing with method 1600 to operation 1624, the second gate spacer layer (eg, FIGS. 13A-13E ) is removed. A gap may be formed or extended by removing the second gate spacer layer. Continuing from method 1600 to operation 1626 , a dielectric layer (eg, the dielectric layer of FIGS. 14A-14E ) is formed. Continuing from method 1600 to operation 1628 , a dielectric plug (eg, dielectric plug 116 of FIGS. 15A-15E ) is formed. The dielectric plug is formed by planarizing the dielectric layer to seal the gap.

Several advantages can be realized by various implementations of the present disclosure. Gap 94 includes air or vacuum, both of which have a lower relative permittivity than the dielectric material in the material from which second gate spacer 88 was removed. In smaller component sizes, the capacitance between the source/drain contacts connected to the source/drain region 92 (not shown) and the gate 108 can be a significant source of circuit capacitance. Reducing the relative dielectric constant between the source/drain contacts and the gate 108 reduces the aforementioned capacitance. Capacitance reduction can improve the final device performance of the resulting FinFET 100 .

In one aspect of the disclosure, a method of manufacturing a semiconductor device is disclosed. The method includes forming a first fin on a substrate. The method includes forming a dummy gate stack on the first fin. The method includes forming a first gate spacer along one side of the dummy gate stack. The first gate spacer includes a first dielectric material. The method includes forming a second gate spacer along a side of the first gate spacer. The second gate spacer includes a semiconductor material. The method includes forming source/drain regions in the first fin adjacent to the second gate spacer. This method involves removing at least some The second gate spacer is formed to form a gap extending between the first gate spacer and the source/drain region.

In some embodiments, the method further includes: depositing an interlayer dielectric layer on the source/drain region, the interlayer dielectric layer including a second dielectric material; and removing at least a portion of the second gate spacer In the step, the top surface of the interlayer dielectric layer is exposed. In some embodiments, during the step of removing at least a portion of the second gate spacer, the first gate spacer and the interlayer dielectric layer remain intact. In some embodiments, the gap further extends between the first gate spacer and the interlayer dielectric layer. In some embodiments, the semiconductor material includes silicon germanium. In some embodiments, the step of removing at least a portion of the second gate spacer includes performing a dry etching process using at least one of hydrogen fluoride gas or fluorine gas. In some embodiments, the method further includes: depositing a dielectric layer on the gap; and using a planarization process, removing portions of the dielectric layer disposed outside the gap such that the remaining portions of the dielectric layer form a plurality of dielectric layers. Electroembolization to seal the gap. In some embodiments, the method further includes forming a second fin on the substrate, a dummy gate stack is further formed on the second fin, a source/drain region is further formed in the second fin, the gap further extends to the source /drain area below. In some embodiments, the method further includes replacing the dummy gate stack with an active gate stack, the first gate spacer extending along a side of the active gate stack. In some embodiments, the gap further extends between the active gate stack and the source/drain regions.

In another aspect of the disclosure, a manufacturing semi method of conducting elements. The method includes forming a first fin and a second fin on a substrate. The first fin and the second fin are adjacent to each other. The method includes forming a dummy gate stack on the first fin and the second fin. The method includes forming a first gate spacer along one side of the dummy gate stack, the first gate spacer comprising a first dielectric material. The method includes forming a second gate spacer along a side of the first gate spacer. The second gate spacer includes a semiconductor material. The method includes forming source/drain regions in both the first fin and the second fin adjacent to the second gate spacer. The source/drain region includes a merged portion between the first fin and the second fin. The method includes removing at least a portion of the second gate spacer to form a gap extending between the first gate spacer and the source/drain regions.

In some embodiments, the gap extends further below the merged portion of the source/drain regions. In some embodiments, the semiconductor material includes silicon germanium. In some embodiments, the method further includes: depositing an interlayer dielectric layer on the source/drain region, the interlayer dielectric layer including a second dielectric material; and removing at least a portion of the second gate spacer In the step, the top surface of the interlayer dielectric layer is exposed. In some embodiments, the method further includes: during the step of removing at least a portion of the second gate spacer, the first gate spacer and the interlayer dielectric layer remain intact. In some embodiments, the gap further extends between the first gate spacer and the interlayer dielectric layer. In some embodiments, the step of removing at least a portion of the second gate spacer includes performing a dry etching process using at least one of hydrogen fluoride gas or fluorine gas. In some embodiments, the method further includes replacing the dummy gate with an active gate stack stack, the first gate spacer extends along one side of the active gate stack, and the gap further extends between the active gate stack and the source/drain regions.

In yet another aspect of the disclosure, a method of manufacturing a semiconductor device is disclosed. The method includes forming fins on a substrate. The method includes forming dummy gate stacks on the fins. The method includes forming gate spacers along one side of the dummy gate stack. The gate spacer includes a first layer formed of a dielectric material, and a second layer formed of a semiconductor material. The method includes forming source/drain regions in the fins adjacent to the gate spacers. This approach involves replacing the dummy gate stack with an active gate stack. The method includes removing at least a portion of the second layer of the gate spacer to form a gap extending between the active gate stack and the source/drain regions.

In some embodiments, the method further includes: depositing an interlayer dielectric layer on the source/drain region; and exposing a top portion of the interlayer dielectric layer during the step of removing at least a portion of the second layer of the gate spacer surface.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should understand that those skilled in the art can easily use this disclosure as a basis for designing or modifying other processes and structures, so as to achieve the same purpose and/or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also realize that these equivalent structures do not depart from the spirit and scope of the present disclosure, and that various changes and substitutions can be made to these equivalent structures without departing from the spirit and scope of the present disclosure. and change Even.

50: Substrate

52: fin

56: Isolation area

86:First gate spacer

92: Source/drain region

100: FinFET

106: gate dielectric layer

108: Gate

A-A, B-B, C-C, D-D, E-E: cross section

Claims (10)

A method of manufacturing a semiconductor device, comprising: forming a first fin on a substrate; forming a dummy gate stack on the first fin; forming a first gate interval along one side of the dummy gate stack member, the first gate spacer includes a first dielectric material; along one side of the first gate spacer, a second gate spacer is formed, the second gate spacer includes a semiconductor material , wherein the semiconductor material comprises silicon germanium; forming a source/drain region in the first fin adjacent to the second gate spacer, wherein the second gate spacer is along the source/drain region and removing at least a portion of the second gate spacer to form a gap extending from the bottom surface of the first gate spacer and the source/drain region and the Between the sidewalls, wherein the step of removing the at least a portion of the second gate spacer includes performing a dry etching process using at least one of hydrogen fluoride gas or fluorine gas. The method as claimed in claim 1, further comprising: depositing an interlayer dielectric layer on the source/drain region, the interlayer dielectric layer comprising a second dielectric material; and removing at least a portion of the In the second gate spacer step, a top surface of the interlayer dielectric layer is exposed. The method as claimed in claim 1, further comprising: depositing a dielectric layer on the gap; and using a planarization process, removing portions of the dielectric layer disposed outside the gap, such that the dielectric layer The plurality of retained portions form a plurality of dielectric plugs to seal the gap. The method as claimed in claim 1, further comprising forming a second fin on the substrate, the dummy gate stack is further formed on the second fin, and the source/drain region is further formed in the second fin , the gap further extends below the source/drain region. The method of claim 1, further comprising replacing the dummy gate stack with an active gate stack, the first gate spacer extending along a side of the active gate stack. The method of claim 5, wherein the gap further extends between the active gate stack and the source/drain region. A method of manufacturing a semiconductor device, comprising: forming a first fin and a second fin on a substrate, the first fin and the second fin being adjacent to each other; forming a dummy gate stack on the first fin and the second fin On the two fins; along one side of the dummy gate stack, a first gate spacer is formed, and the first gate spacer includes a first dielectric material; along one side of the first gate spacer, forming a second gate spacer comprising a semiconductor material, wherein the semiconductor material comprises silicon germanium; forming a source/drain region in both the first fin and the second fin adjacent to the second gate spacer, wherein the second gate spacer extends along a bottom surface and sidewalls of the source/drain region, the source/drain region includes a merged portion between the first fin and the second fin; and at least a portion of the second gate spacer is removed to form a gap extending from the first gate between the spacer and the bottom surface and the sidewall of the source/drain region, wherein the step of removing the at least a portion of the second gate spacer includes using at least one of hydrogen fluoride gas or fluorine gas , performing a dry etching process. The method of claim 7, wherein the gap further extends below the merged portion of the source/drain region. A method of manufacturing a semiconductor device, comprising: forming a fin on a substrate; forming a dummy gate stack on the fin; forming a gate spacer along one side of the dummy gate stack, the gate spacer The device includes a first layer formed of a dielectric material, and a second layer formed of a semiconductor material, wherein the semiconductor material includes silicon germanium; forming a source/drain region in the fin adjacent to the gate spacer, wherein the second layer extends along a bottom surface and sidewalls of the source/drain region; using an active gate stack instead the dummy gate stack; and removing at least a portion of the second layer of the gate spacer to form a gap extending between the active gate stack and the bottom surface and the sidewall of the source/drain region During, the step of removing the at least a portion of the second layer of the gate spacer includes performing a dry etching process using at least one of hydrogen fluoride gas or fluorine gas. The method as claimed in claim 9, further comprising: depositing an interlayer dielectric layer on the source/drain region; and in the step of removing at least a portion of the second layer of the gate spacer, exposing A top surface of the interlayer dielectric layer.

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