TWI782817B - Semiconductor package and semiconductor device - Google Patents

Semiconductor package and semiconductor device Download PDF

Info

Publication number
TWI782817B
TWI782817B TW110146753A TW110146753A TWI782817B TW I782817 B TWI782817 B TW I782817B TW 110146753 A TW110146753 A TW 110146753A TW 110146753 A TW110146753 A TW 110146753A TW I782817 B TWI782817 B TW I782817B
Authority
TW
Taiwan
Prior art keywords
solder ball
wiring substrate
conductive plug
semiconductor package
electrically connected
Prior art date
Application number
TW110146753A
Other languages
Chinese (zh)
Other versions
TW202238889A (en
Inventor
沖嶋拓也
赤間圭一
Original Assignee
日商鎧俠股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2021042776A external-priority patent/JP2022142564A/en
Application filed by 日商鎧俠股份有限公司 filed Critical 日商鎧俠股份有限公司
Publication of TW202238889A publication Critical patent/TW202238889A/en
Application granted granted Critical
Publication of TWI782817B publication Critical patent/TWI782817B/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Die Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

Embodiments provide a packaged semiconductor chip and a semiconductor device which can improve the reliability of operation and achieve a longer life. According to one embodiment, a packaged semiconductor device includes a wiring substrate with a bonding pad on a first surface, a wiring layer, a first conductive plug extending through the wiring substrate from the wiring layer to the first surface, a second conductive plug extending through the wiring substrate from the wiring layer to a second surface, and a third conductive plug extending through the wiring substrate from the wiring layer to the second surface. A semiconductor chip is mounted on the first surface and has a pad terminal electrically connected to the bonding pad. A first solder ball is on the second surface of the wiring substrate and electrically connected to the second conductive plug. A second solder ball is on the second surface of the wiring substrate and electrically connected to the third conductive plug.

Description

半導體封裝及半導體裝置Semiconductor package and semiconductor device

本文所描述之實施例大體上係關於一種半導體封裝及一種半導體裝置。Embodiments described herein generally relate to a semiconductor package and a semiconductor device.

已知利用一球柵陣列(BGA)來將一經封裝之半導體晶片電連接至一印刷電路板之半導體裝置。Semiconductor devices are known that utilize a ball grid array (BGA) to electrically connect a packaged semiconductor die to a printed circuit board.

實施例提供一種經封裝之半導體晶片及一種半導體裝置，其可改良操作之可靠性並達成一更長之壽命。Embodiments provide a packaged semiconductor chip and a semiconductor device that can improve operational reliability and achieve a longer lifetime.

一般而言，根據一項實施例，一半導體封裝包含具有一第一表面及與該第一表面相對之一第二表面之一佈線基板。一接合墊位於該佈線基板之該第一表面上。一佈線層位於該佈線基板中介於該第一表面與該第二表面之間。一第一導電插塞自該佈線層延伸穿過該佈線基板至該第一表面。該第一導電插塞連接至該接合墊。一第二導電插塞自該佈線層延伸穿過該佈線基板至該第二表面。該第二導電插塞亦電連接至該接合墊。一第三導電插塞自該佈線層延伸穿過該佈線基板至該第二表面。該第三導電插塞亦電連接至該接合墊。一半導體晶片經安裝在該第一表面上，且具有電連接至該接合墊之一墊端子。一第一焊球位於該佈線基板之該第二表面上，並電連接至該第二導電插塞。一第二焊球位於該佈線基板之該第二表面上，並電連接至該第三導電插塞。In general, according to one embodiment, a semiconductor package includes a wiring substrate having a first surface and a second surface opposite to the first surface. A bonding pad is located on the first surface of the wiring substrate. A wiring layer is located in the wiring substrate between the first surface and the second surface. A first conductive plug extends from the wiring layer through the wiring substrate to the first surface. The first conductive plug is connected to the bonding pad. A second conductive plug extends from the wiring layer through the wiring substrate to the second surface. The second conductive plug is also electrically connected to the bonding pad. A third conductive plug extends from the wiring layer through the wiring substrate to the second surface. The third conductive plug is also electrically connected to the bonding pad. A semiconductor chip is mounted on the first surface and has a pad terminal electrically connected to the bonding pad. A first solder ball is located on the second surface of the wiring substrate and is electrically connected to the second conductive plug. A second solder ball is located on the second surface of the wiring substrate and is electrically connected to the third conductive plug.

下文中，將參考圖式描述特定實例實施例。Hereinafter, specific example embodiments will be described with reference to the drawings.

(第一實施例)(first embodiment)

圖1係根據一第一實施例之一半導體裝置100之一橫截面視圖。圖2A係一半導體封裝1之一俯視圖。圖2B係半導體封裝1之一仰視圖。在以下描述中，假定與半導體裝置100中之一佈線基板12之前表面平行之一平面係xy平面，且假定正交於一xy平面之一方向係一z方向。在以下描述中，可參考一上下關係，其假定一第一表面12a所定位之佈線基板12之側係一上側，且一第二表面12b所定位之佈線基板12之側係一下側。此等方向性參考係出於解釋半導體裝置100內之組件及態樣之相對定位之目的，且不一定與一重力定向或類似者對應。FIG. 1 is a cross-sectional view of a semiconductor device 100 according to a first embodiment. FIG. 2A is a top view of a semiconductor package 1 . FIG. 2B is a bottom view of the semiconductor package 1 . In the following description, it is assumed that a plane parallel to the front surface of a wiring substrate 12 in the semiconductor device 100 is an xy plane, and a direction orthogonal to an xy plane is assumed to be a z direction. In the following description, a top-bottom relationship may be referred to, which assumes that the side of the wiring substrate 12 positioned by a first surface 12a is an upper side, and the side of the wiring substrate 12 positioned by a second surface 12b is a lower side. These directional references are for the purpose of explaining the relative positioning of components and aspects within semiconductor device 100 and do not necessarily correspond to a gravitational orientation or the like.

在圖1中，展示藉由沿一xz平面切割半導體裝置100而獲得之一xz橫截面之結構。半導體裝置100包含半導體封裝1及一印刷佈線板2。半導體封裝1包含外部端子3、一半導體晶片10、一膜黏合劑11、一佈線基板12、囊封樹脂13、接合墊14、導電組件15及一凸形組件121。In FIG. 1 , the structure of an xz cross section obtained by cutting the semiconductor device 100 along an xz plane is shown. The semiconductor device 100 includes a semiconductor package 1 and a printed wiring board 2 . The semiconductor package 1 includes external terminals 3 , a semiconductor chip 10 , a film adhesive 11 , a wiring substrate 12 , encapsulation resin 13 , bonding pads 14 , conductive components 15 and a convex component 121 .

佈線基板12包含一佈線層120、一金屬插塞122a及一金屬插塞122b。例如，佈線基板12係一絕緣樹脂佈線基板或一陶瓷佈線基板，其在其前表面上或內部具有多層佈線層120。在此實例中，包括玻璃環氧樹脂之一印刷佈線基板被用作一佈線基板12。在圖1中，展示佈線層120之一部分。一般而言，佈線基板12之前表面經覆蓋有一阻焊劑，以保護如在佈線層120中所包含之此佈線。佈線基板12具有一第一表面12a及一第二表面12b。The wiring substrate 12 includes a wiring layer 120 , a metal plug 122 a and a metal plug 122 b. For example, the wiring substrate 12 is an insulating resin wiring substrate or a ceramic wiring substrate having a multilayer wiring layer 120 on or inside its front surface. In this example, a printed wiring substrate including glass epoxy was used as a wiring substrate 12 . In FIG. 1 , a portion of the wiring layer 120 is shown. Generally, the front surface of the wiring substrate 12 is covered with a solder resist to protect the wiring as included in the wiring layer 120 . The wiring substrate 12 has a first surface 12a and a second surface 12b.

在佈線基板12之第一表面12a上形成一接合墊14。設置穿過第一表面12a上之阻焊劑至佈線層120之一通孔用於進行電連接。通孔係導電金屬，且其中形成金屬插塞122a。接合墊14及佈線層120藉由金屬插塞122a電連接。A bonding pad 14 is formed on the first surface 12 a of the wiring substrate 12 . A via hole is provided through the solder resist on the first surface 12a to the wiring layer 120 for electrical connection. The via hole is a conductive metal, and a metal plug 122a is formed therein. The bonding pad 14 and the wiring layer 120 are electrically connected by the metal plug 122a.

在佈線基板12之第一表面12a上設置一半導體晶片10。一半導體晶片10之非限制性實例包含一NAND快閃記憶體晶片。一般而言，可使用任何半導體晶片類型(或類型之組合)，諸如一記憶體組件(諸如動態隨機存取記憶體(DRAM)晶片)、一算術組件(諸如一微處理器晶片)或一信號處理組件。一膜黏合劑11位於半導體晶片10之整個後表面上。在此背景內容中，後表面係半導體晶片10之面向佈線基板12之側。A semiconductor chip 10 is provided on the first surface 12 a of the wiring substrate 12 . A non-limiting example of a semiconductor chip 10 includes a NAND flash memory chip. In general, any semiconductor chip type (or combination of types) can be used, such as a memory component (such as a dynamic random access memory (DRAM) chip), an arithmetic component (such as a microprocessor chip), or a signal Processing components. A film adhesive 11 is located on the entire rear surface of the semiconductor wafer 10 . In this context, the rear surface is the side of the semiconductor wafer 10 facing the wiring substrate 12 .

膜黏合劑11可係熱固性樹脂。例如，膜黏合劑11可係環氧基樹脂、聚醯亞胺基樹脂、丙烯酸基樹脂或此等樹脂之一組合。一晶粒貼附膜(DAF)、其中可嵌入一導電導線之膜包線(Film on Wire) (FOW)或類似者可被用作膜黏合劑11。半導體晶片10經由膜黏合劑11牢固地固定至佈線基板12。The film adhesive 11 can be a thermosetting resin. For example, the film adhesive 11 may be epoxy-based resin, polyimide-based resin, acrylic-based resin or a combination of these resins. A die attach film (DAF), film on wire (FOW) in which a conductive wire can be embedded, or the like can be used as the film adhesive 11 . The semiconductor wafer 10 is firmly fixed to the wiring substrate 12 via a film adhesive 11 .

如圖2A中所展示，在半導體晶片10之前表面上形成一墊101。在此背景內容中，前表面係半導體晶片10之背對佈線基板12之側。墊101及接合墊14 (在佈線基板12上)使用一導電組件15進行電連接，該導電組件15可係一導電導線(諸如一接合佈線)。各墊101在一對一之基礎上連接至一接合墊14。例如，如圖2A中所描繪，一墊101a連接至一接合墊14a，一墊101b連接至一接合墊14b，且一墊101c連接至一接合墊14c。半導體晶片10經囊封在設置於佈線基板12之上表面側上之囊封樹脂13中。As shown in FIG. 2A , a pad 101 is formed on the front surface of the semiconductor wafer 10 . In this context, the front surface is the side of the semiconductor wafer 10 facing away from the wiring substrate 12 . Pad 101 and bond pad 14 (on wiring substrate 12) are electrically connected using a conductive element 15, which may be a conductive wire (such as a bonding wire). Each pad 101 is connected to a bond pad 14 on a one-to-one basis. For example, as depicted in FIG. 2A, one pad 101a is connected to a bond pad 14a, one pad 101b is connected to a bond pad 14b, and one pad 101c is connected to a bond pad 14c. The semiconductor chip 10 is encapsulated in an encapsulating resin 13 provided on the upper surface side of the wiring substrate 12 .

在佈線基板12之第二表面12b上設置用於一BGA型封裝之外部端子3。此實例中之各外部端子3係一突出(凸出)之端子，諸如一焊球。在以下描述中，外部端子3被稱為焊球3。一焊球3可電連接至佈線基板12之佈線層120。明確而言，設置在覆蓋佈線基板12之第二表面12b之阻焊劑中至佈線層120之一通孔。通孔經填充有導電金屬，且形成金屬插塞122b。一焊球3及佈線層120可藉由金屬插塞122b電連接。在一些例項中，金屬插塞122b亦可被稱為一焊盤(land) 122b。在第一實施例之半導體裝置100中，使用兩種類型之焊球3 (焊球3a及焊球3b)。在第一實施例之描述中，假定對一「焊球3」之引用係指焊球3a及焊球3b兩者。On the second surface 12b of the wiring substrate 12, external terminals 3 for a BGA type package are provided. Each external terminal 3 in this example is a projected (protruded) terminal such as a solder ball. In the following description, the external terminals 3 are referred to as solder balls 3 . A solder ball 3 can be electrically connected to the wiring layer 120 of the wiring substrate 12 . Specifically, a through hole to the wiring layer 120 is provided in the solder resist covering the second surface 12 b of the wiring substrate 12 . The vias are filled with conductive metal and form metal plugs 122b. A solder ball 3 and the wiring layer 120 can be electrically connected through the metal plug 122b. In some examples, the metal plug 122b may also be called a land 122b. In the semiconductor device 100 of the first embodiment, two types of solder balls 3 (solder ball 3a and solder ball 3b) are used. In the description of the first embodiment, it is assumed that reference to a "solder ball 3" refers to both the solder ball 3a and the solder ball 3b.

印刷佈線板2 (印刷電路板)包括由一絕緣材料(諸如玻璃環氧樹脂)製成之一安裝板23及形成在安裝板23之上表面上之一佈線層24。可在佈線層24中形成各種電路圖案結構及連接。佈線層24係由一導電金屬形成，諸如金(Au)、銀(Ag)、銅(Cu)、鋁(Al)、鎳(Ni)、鈀(Pd)及鎢(W)。可在佈線層24之前表面上形成包括一阻焊劑之一電路保護層20。在電路保護層20中，穿過電路保護層20之一通孔允許佈線層24與焊球3之間之電連接，且可在通孔內形成由導電金屬形成之一安裝板端子21。將焊膏22塗覆至(例如，印刷在)安裝板端子21之上表面側，以將一焊球3連接至一安裝板端子21。The printed wiring board 2 (printed circuit board) includes a mounting board 23 made of an insulating material such as glass epoxy and a wiring layer 24 formed on the upper surface of the mounting board 23 . Various circuit pattern structures and connections can be formed in the wiring layer 24 . The wiring layer 24 is formed of a conductive metal such as gold (Au), silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), palladium (Pd), and tungsten (W). A circuit protection layer 20 including a solder resist may be formed on the front surface of the wiring layer 24 . In the circuit protection layer 20, a via hole passing through the circuit protection layer 20 allows electrical connection between the wiring layer 24 and the solder ball 3, and a mounting board terminal 21 formed of conductive metal may be formed in the via hole. Solder paste 22 is applied to (for example, printed on) the upper surface side of mounting board terminal 21 to connect a solder ball 3 to a mounting board terminal 21 .

焊球3b與焊球3a具有彼此相同之組態，惟z方向上之長度除外。在以下描述中，一焊球3在z方向上之長度有時被稱為一高度。焊球3b之組合物與焊球3a之組合物相同。亦即，焊球3a與3b係相同之材料。例如，焊球3a及3b係由一Sn-Ag-Cu基(SAC基)合金製成。例如，合金成分係Sn：96.5wt%；Ag：3.0wt%，Cu：0.5wt%。此等組合物與由日本電子工業發展協會(JEIDA)所推薦之組合物對應。The solder ball 3b and the solder ball 3a have the same configuration as each other except for the length in the z direction. In the following description, the length of a solder ball 3 in the z direction is sometimes referred to as a height. The composition of the solder ball 3b is the same as that of the solder ball 3a. That is, the solder balls 3a and 3b are made of the same material. For example, the solder balls 3a and 3b are made of a Sn-Ag-Cu-based (SAC-based) alloy. For example, the alloy composition is Sn: 96.5wt%, Ag: 3.0wt%, Cu: 0.5wt%. These compositions correspond to those recommended by the Japan Electronics Industries Development Association (JEIDA).

焊球3b在z方向上之長度短於焊球3a在z方向上之長度。焊球3b經由一凸形組件121連接至佈線基板12之金屬插塞122b。例如，凸形組件121具有一圓柱體之形狀。凸形組件121包含一基底組件123及一金屬插塞124 (參見圖2B)。基底組件123係由絕緣樹脂材料形成之一圓環形(環形)絕緣結構。金屬插塞124係導電金屬，其填充基底組件123內部之區域。焊球3b經由插置其間之金屬插塞124連接至佈線基板12之金屬插塞122b。設定凸形組件121在z方向上之長度，使得凸形組件121在z方向上之長度與焊球3b在z方向上之長度之總和之值將幾乎與焊球3a在z方向上之長度相同。在一些背景內容中，凸形組件121可被稱為一間隔元件121或一間隔插塞121。The length of the solder ball 3b in the z direction is shorter than the length of the solder ball 3a in the z direction. The solder ball 3b is connected to the metal plug 122b of the wiring substrate 12 through a convex component 121 . For example, the male component 121 has a cylindrical shape. The male component 121 includes a base component 123 and a metal plug 124 (see FIG. 2B ). The base assembly 123 is an annular (ring-shaped) insulating structure formed of insulating resin material. The metal plug 124 is a conductive metal that fills the area inside the base component 123 . The solder balls 3b are connected to the metal plugs 122b of the wiring substrate 12 via the metal plugs 124 interposed therebetween. The length of the male component 121 in the z direction is set such that the sum of the length of the male component 121 in the z direction and the length of the solder ball 3b in the z direction will have almost the same value as the length of the solder ball 3a in the z direction . In some context, male component 121 may be referred to as a spacer element 121 or a spacer plug 121 .

如圖2B中所展示，複數個插塞群組(例如，PG1、PG2、PG3)位於佈線基板12之第二表面12b上。各插塞群組包含金屬插塞122b之一或多者及金屬插塞124之一或多者。焊球3a連接至金屬插塞122b。焊球3b連接至金屬插塞124。各插塞群組電連接至一個接合墊14。例如，圖2A中所展示之接合墊14a電連接至圖2B中所展示之一插塞群組PG1。亦即，經由一接合墊14自一墊101輸出之一信號被傳送至特定接合墊14之一對應插塞群組之至少一個金屬插塞122b及至少一個金屬插塞124。例如，經由接合墊14a自墊101a輸出之一信號被傳送至插塞群組PG1中所提供之一金屬插塞122b_11及一金屬插塞124_12。亦即，各墊101電連接至至少一個焊球3a及至少一個焊球3b。As shown in FIG. 2B , a plurality of plug groups (eg, PG1 , PG2 , PG3 ) are located on the second surface 12 b of the wiring substrate 12 . Each plug group includes one or more metal plugs 122 b and one or more metal plugs 124 . The solder ball 3a is connected to the metal plug 122b. The solder ball 3 b is connected to the metal plug 124 . Each plug group is electrically connected to one bond pad 14 . For example, bond pad 14a shown in FIG. 2A is electrically connected to one plug group PG1 shown in FIG. 2B. That is, a signal output from a pad 101 via a bond pad 14 is transmitted to at least one metal plug 122 b and at least one metal plug 124 of a corresponding plug group of a particular bond pad 14 . For example, a signal output from the pad 101a via the bonding pad 14a is transmitted to a metal plug 122b_11 and a metal plug 124_12 provided in the plug group PG1. That is, each pad 101 is electrically connected to at least one solder ball 3a and at least one solder ball 3b.

與其中半導體封裝1及印刷佈線板2經由一引線框架連接之一四面扁平封裝(QFP)相比，使用一BGA型封裝之一半導體裝置100通常更適合於使連接端子更密集及使半導體裝置100小型化。因此，在行動數位設備中更經常地使用使用一BGA之半導體裝置100。要求行動數位設備具有對由電子設備之開-關引起之熱循環疲勞的抗性(下文稱為抗熱疲勞性)，以及對在使用期間之跌落的抗性(下文稱為抗跌落衝擊性)。Compared with a quad flat package (QFP) in which the semiconductor package 1 and the printed wiring board 2 are connected via a lead frame, a semiconductor device 100 using a BGA type package is generally more suitable for making connection terminals denser and making the semiconductor device 100 miniaturization. Therefore, the semiconductor device 100 using a BGA is more often used in mobile digital equipment. Mobile digital equipment is required to have resistance to thermal cycle fatigue caused by the on-off of electronic equipment (hereinafter referred to as thermal fatigue resistance), and resistance to dropping during use (hereinafter referred to as drop shock resistance) .

一般而言，焊球3之高度(z方向長度)越大，由焊球3提供之一彈簧效應越大，此允許焊球3自身吸收誘發之應力，且因此使抗熱疲勞性更高。另一方面，焊球3之高度越大，應力越容易集中在焊球3與金屬插塞122b之間之一接頭處，此減小抗跌落衝擊性。亦即，一焊球3之高度越大，抗熱疲勞性越好，但抗跌落衝擊性越低。相反，焊球3之高度越小，抗跌落衝擊性越好，但抗熱疲勞性越低。例如，可藉由溫度循環測試來量測抗熱疲勞性。例如，可藉由衝擊測試來量測抗跌落衝擊性。In general, the greater the height (z-direction length) of the solder ball 3, the greater the spring effect provided by the solder ball 3, which allows the solder ball 3 itself to absorb the induced stress and thus makes the thermal fatigue resistance higher. On the other hand, the greater the height of the solder ball 3 is, the easier the stress is concentrated at a joint between the solder ball 3 and the metal plug 122b, which reduces the drop impact resistance. That is, the larger the height of a solder ball 3 is, the better the thermal fatigue resistance is, but the lower the drop impact resistance is. On the contrary, the smaller the height of the solder ball 3 is, the better the drop impact resistance is, but the lower the thermal fatigue resistance is. For example, thermal fatigue resistance can be measured by temperature cycling tests. For example, drop shock resistance can be measured by a shock test.

第一實施例之半導體裝置100包含在高度上彼此不同之兩種類型之焊球3a及3b，且各接合墊14連接至一個或更多個焊球3a及一個或更多個焊球3b。亦即，各接合墊14連接至提供更高之抗熱疲勞性之至少一個焊球3a及提供更高之抗跌落衝擊性之至少一個焊球3b。此外，此組態使得當一焊球3b已被熱疲勞損壞時，可經由一焊球3a將一信號傳輸至印刷佈線板2及自印刷佈線板2接收一信號，且當一焊球3a已被跌落衝擊損壞時，可經由一焊球3b將信號傳輸至印刷佈線板2及自印刷佈線板2接收信號。此改良操作之可靠性，並使得可能達成一更長之裝置壽命。The semiconductor device 100 of the first embodiment includes two types of solder balls 3 a and 3 b different in height from each other, and each bonding pad 14 is connected to one or more solder balls 3 a and one or more solder balls 3 b. That is, each bonding pad 14 is connected to at least one solder ball 3a providing higher resistance to thermal fatigue and at least one solder ball 3b providing higher resistance to drop shock. In addition, this configuration makes it possible to transmit and receive a signal to and from the printed wiring board 2 via a solder ball 3a when a solder ball 3b has been damaged by thermal fatigue, and when a solder ball 3a has been damaged When damaged by a drop impact, a signal can be transmitted to and received from the printed wiring board 2 via a solder ball 3b. This improves the reliability of operation and makes it possible to achieve a longer device lifetime.

凸形組件121之形狀不限於一柱形。凸形組件121可具有任何其他形狀，只要凸形組件121可將一焊球3b穩定地連接至佈線基板12之金屬插塞122b。此外，焊球3a及3b之組合物不限於上文所提及之材料。例如，可使用另一合金，諸如一Sn-Cu基合金或一Sn-Ag基合金。此外，材料組合物可具有與上文所提及之不同之組合物比率，諸如Sn：95.5wt%、Ag：4.0wt%、Cu：0.5wt%，諸如由國家電子製造促進會(NEMI)所推薦。The shape of the male component 121 is not limited to a cylinder. The male component 121 may have any other shape as long as the male component 121 can stably connect a solder ball 3 b to the metal plug 122 b of the wiring substrate 12 . In addition, the composition of the solder balls 3a and 3b is not limited to the materials mentioned above. For example, another alloy such as a Sn-Cu based alloy or a Sn-Ag based alloy may be used. In addition, the material composition may have a composition ratio different from that mentioned above, such as Sn: 95.5wt%, Ag: 4.0wt%, Cu: 0.5wt%, such as those specified by the National Electronics Manufacturing Institute (NEMI). recommend.

(第二實施例)(second embodiment)

接下來，將描述根據一第二實施例之一半導體裝置100。第二實施例之半導體裝置100與第一實施例之半導體裝置100在特定焊球3之組態上不同。在第二實施例中，與第一實施例之態樣及/或組件相同之態樣及/或組件被給予相同之參考符號，且可省略其等之詳細說明。Next, a semiconductor device 100 according to a second embodiment will be described. The semiconductor device 100 of the second embodiment differs from the semiconductor device 100 of the first embodiment in the configuration of specific solder balls 3 . In the second embodiment, the same aspects and/or components as those of the first embodiment are given the same reference symbols, and detailed description thereof may be omitted.

圖3係展示根據本發明之第二實施例之半導體裝置100之結構之一橫截面視圖。圖4係圖3中所展示之一半導體封裝1之一仰視圖。在第二實施例之半導體裝置100中，半導體封裝1及一印刷佈線板2藉由兩種不同類型之焊球3c及3d連接。焊球3c與焊球3d具有彼此相同之大小，但焊球3c與焊球3d在材料組合物上彼此不同。例如，焊球3c及3d兩者由不同之Sn-Ag-Cu基(SAC基)合金製成。例如，焊球3c之合金成分係Ag：3wt%、Cu：0.8wt%、Bi：3wt%、Ni：0.02wt%、Sn：(餘量)。焊球3d之合金成分係Ag：1.2wt%、Cu：0.5wt%、Ni：0.05wt%、Sn：(餘量)。FIG. 3 is a cross-sectional view showing the structure of a semiconductor device 100 according to a second embodiment of the present invention. FIG. 4 is a bottom view of a semiconductor package 1 shown in FIG. 3 . In the semiconductor device 100 of the second embodiment, the semiconductor package 1 and a printed wiring board 2 are connected by two different types of solder balls 3c and 3d. The solder ball 3c and the solder ball 3d have the same size as each other, but the solder ball 3c and the solder ball 3d are different from each other in material composition. For example, both solder balls 3c and 3d are made of different Sn-Ag-Cu-based (SAC-based) alloys. For example, the alloy composition of the solder ball 3c is Ag: 3wt%, Cu: 0.8wt%, Bi: 3wt%, Ni: 0.02wt%, Sn: (remainder). The alloy composition of the solder ball 3d is Ag: 1.2wt%, Cu: 0.5wt%, Ni: 0.05wt%, Sn: (remainder).

焊球3c具有提供更好之抗熱疲勞性之特性。焊球3c之合金成分與第一實施例中之焊球3a及3b之合金成分之不同之處在於添加鉍(Bi)並增加銅(Cu)之含量。藉由添加Bi，達成固溶體強化。藉由增加Cu之含量，達成沉澱強化。亦即，在藉由Bi進行固溶體強化及藉由Cu進行沉澱強化之情況下，使對應之焊球更硬，並抵抗變形。此增加抗熱疲勞性。The solder ball 3c has the property of providing better thermal fatigue resistance. The alloy composition of the solder ball 3c is different from that of the solder balls 3a and 3b in the first embodiment in that bismuth (Bi) is added and the content of copper (Cu) is increased. Solid solution strengthening is achieved by adding Bi. By increasing the content of Cu, precipitation strengthening is achieved. That is, in the case of solid solution strengthening by Bi and precipitation strengthening by Cu, the corresponding solder balls are made harder and resist deformation. This increases thermal fatigue resistance.

另一方面，焊球3d具有提供更好之抗跌落衝擊性之特性。焊球3d之合金成分與第一實施例中之焊球3a及3b之合金成分之不同之處在於銀(Ag)含量減小。銀含量之一減小使焊球更軟，此增加抗跌落衝擊性。上述焊球3c及3d之具體材料組合物僅係實例，且可採用其他材料組合物。On the other hand, the solder ball 3d has the property of providing better drop impact resistance. The alloy composition of the solder ball 3d differs from those of the solder balls 3a and 3b in the first embodiment in that the silver (Ag) content is reduced. A reduction in silver content makes the solder balls softer, which increases drop shock resistance. The specific material compositions of the above-mentioned solder balls 3c and 3d are just examples, and other material compositions may be used.

如圖4中所展示，複數個插塞群組(例如，PG1、PG2、PG3)位於一佈線基板12之第二表面12b上。各插塞群組包含複數個金屬插塞122b。一焊球3c連接至屬於各插塞群組之一個或更多個金屬插塞122b。一焊球3d連接至屬於各插塞群組之一個或更多個金屬插塞122b。例如，金屬插塞122b_11及122b_12屬於一插塞群組PG1。一焊球3c連接至金屬插塞122b_11，且一焊球3d連接至金屬插塞122b_12。亦即，至少一個焊球3c及至少一個焊球3d連接至各插塞群組。As shown in FIG. 4 , a plurality of plug groups (eg, PG1 , PG2 , PG3 ) are located on the second surface 12 b of a wiring substrate 12 . Each plug group includes a plurality of metal plugs 122b. A solder ball 3c is connected to one or more metal plugs 122b belonging to each plug group. A solder ball 3d is connected to one or more metal plugs 122b belonging to each plug group. For example, metal plugs 122b_11 and 122b_12 belong to a plug group PG1. A solder ball 3c is connected to the metal plug 122b_11, and a solder ball 3d is connected to the metal plug 122b_12. That is, at least one solder ball 3c and at least one solder ball 3d are connected to each plug group.

各插塞群組電連接至接合墊14中之一對應一者。因此，經由一接合墊14自一墊101輸出之一信號被傳送至電連接至接合墊14之插塞群組之複數個金屬插塞122b。亦即，各墊101電連接至一個或更多個焊球3c及一個或更多個焊球3d。Each plug group is electrically connected to a corresponding one of the bond pads 14 . Therefore, a signal output from a pad 101 via a bonding pad 14 is transmitted to a plurality of metal plugs 122 b of the plug group electrically connected to the bonding pad 14 . That is, each pad 101 is electrically connected to one or more solder balls 3c and one or more solder balls 3d.

第二實施例之半導體裝置100包含組合物不同之兩種類型之焊球3c及3d。與第一實施例之情況一樣，當焊球3d被熱疲勞損壞時，根據第二實施例之半導體裝置100可經由焊球3c將一信號傳輸至印刷佈線板2及自印刷佈線板2接收一信號，且當焊球3c被跌落衝擊損壞時，可經由焊球3d將一信號傳輸至印刷佈線板2及自印刷佈線板2接收一信號。此增加操作之可靠性，並使得可達成一更長之壽命。The semiconductor device 100 of the second embodiment includes two types of solder balls 3c and 3d with different compositions. As in the case of the first embodiment, when the solder ball 3d is damaged by thermal fatigue, the semiconductor device 100 according to the second embodiment can transmit a signal to and receive a signal from the printed wiring board 2 via the solder ball 3c. signal, and when the solder ball 3c is damaged by the drop impact, a signal can be transmitted to and received from the printed wiring board 2 via the solder ball 3d. This increases the reliability of operation and makes it possible to achieve a longer lifetime.

(第三實施例)(third embodiment)

接下來，將描述根據一第三實施例之一半導體裝置100。第三實施例之半導體裝置100與第二實施例之半導體裝置100之不同之處在於一安裝板端子21與一焊球3之間之一連接。與第二實施例之組件及態樣相同之組件及態樣由相同之參考符號表示，且省略其等之詳細說明。Next, a semiconductor device 100 according to a third embodiment will be described. The difference between the semiconductor device 100 of the third embodiment and the semiconductor device 100 of the second embodiment lies in a connection between a board terminal 21 and a solder ball 3 . The same components and aspects as those of the second embodiment are denoted by the same reference symbols, and their detailed descriptions are omitted.

圖5係展示根據第三實施例之半導體裝置100之結構之一橫截面視圖。在第三實施例之半導體裝置100中，一半導體封裝1及一印刷佈線板2藉由兩種類型之焊球3 (3c及3d)連接。焊球3c具有提供更高之抗熱疲勞性之特性，且焊球3d具有提供更高之抗跌落衝擊性之特性。例如，焊球3c及3d之材料組合物可與第二實施例之材料組合物相同。FIG. 5 is a cross-sectional view showing the structure of a semiconductor device 100 according to a third embodiment. In the semiconductor device 100 of the third embodiment, a semiconductor package 1 and a printed wiring board 2 are connected by two types of solder balls 3 (3c and 3d). The solder ball 3c has the property of providing higher thermal fatigue resistance, and the solder ball 3d has the property of providing higher drop shock resistance. For example, the material composition of the solder balls 3c and 3d can be the same as that of the second embodiment.

焊球3c連接至一金屬插塞122b1。焊球3d連接至一金屬插塞122b2。各接合墊14連接至兩個金屬插塞122b1及122b2。因此，經由一接合墊14自一墊101輸出之一信號被傳送至兩個金屬插塞122b1及122b2。亦即，各墊101分別經由兩個金屬插塞122b1及122b2電連接至一焊球3c及一焊球3d。電連接至各墊101之不同類型之複數個焊球3 (例如，焊球3c及焊球3d)經由焊膏22電連接至各安裝板端子21。The solder ball 3c is connected to a metal plug 122b1. The solder ball 3d is connected to a metal plug 122b2. Each bonding pad 14 is connected to two metal plugs 122b1 and 122b2. Therefore, a signal output from a pad 101 via a bonding pad 14 is transmitted to two metal plugs 122b1 and 122b2. That is, each pad 101 is electrically connected to a solder ball 3c and a solder ball 3d through two metal plugs 122b1 and 122b2 respectively. A plurality of solder balls 3 of different types (eg, solder ball 3 c and solder ball 3 d ) electrically connected to each pad 101 are electrically connected to each mounting board terminal 21 via solder paste 22 .

在第三實施例中，與第二實施例之情況一樣，半導體封裝1o包含在材料組合物上不同之兩種類型之焊球3c及3d。當半導體裝置100經歷一高位準之熱疲勞且一焊球3d最終斷裂時，仍可經由一焊球3c將一信號傳輸至印刷佈線板2及自印刷佈線板2接收一信號。類似地，當由半導體裝置100經歷一大跌落衝擊且一焊球3c斷裂時，仍可經由一焊球3d將一信號傳輸至印刷佈線板2及自印刷佈線板2接收一信號。此外，由於兩種不同類型之焊球3 (3c及3d)電連接至各墊101且連接至同一安裝板端子21，因此可傳送比第二實施例之情況中更多之信號。In the third embodiment, as in the case of the second embodiment, the semiconductor package 1o includes two types of solder balls 3c and 3d which differ in material composition. When the semiconductor device 100 experiences a high level of thermal fatigue and a solder ball 3d finally breaks, a signal can still be transmitted to and received from the printed wiring board 2 via a solder ball 3c. Similarly, when the semiconductor device 100 experiences a large drop impact and a solder ball 3c breaks, a signal can still be transmitted to and received from the printed wiring board 2 via a solder ball 3d. Furthermore, since two different types of solder balls 3 (3c and 3d) are electrically connected to each pad 101 and to the same mounting board terminal 21, more signals can be transmitted than in the case of the second embodiment.

上文所描述之實例實施例處理其中一信號自半導體晶片10輸出至印刷佈線板2之一情況；該實施例亦可應用於其中一信號自印刷佈線板2輸入至半導體晶片10之一情況。The example embodiment described above deals with the case where a signal is output from the semiconductor chip 10 to the printed wiring board 2 ; the embodiment can also be applied to the case where a signal is input from the printed wiring board 2 to the semiconductor chip 10 .

上文所提及之實施例可儘可能地彼此組合。例如，第一實施例可與第三實施例組合。The embodiments mentioned above can be combined with each other as much as possible. For example, the first embodiment can be combined with the third embodiment.

雖然已描述特定實施例，但此等實施例已僅以實例之方式呈現，並不旨在限制本發明之範疇。實際上，本文所描述之新穎實施例可以各種其他形式體現；此外，在不脫離本發明之精神之情況下，可以本文所描述之實施例之形式進行各種省略、替換及更改。隨附發明申請專利範圍及其等之等效物旨在涵蓋如將落入本發明之範疇及精神內之此等形式或修改。 相關申請案之交叉引用 While specific embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in various other forms; moreover, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the invention. Cross References to Related Applications

本申請案基於並主張來自2021年3月16日申請之第2021-042776號日本專利申請案及2021年8月25日申請之第17/411950號美國專利申請案之優先權之權益，其全部內容以引用之方式併入本文中。This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2021-042776, filed March 16, 2021, and U.S. Patent Application No. 17/411950, filed August 25, 2021, all of which The contents are incorporated herein by reference.

1: 半導體封裝 2: 印刷佈線板 3, 3a, 3b, 3c, 3d: 焊球 10: 半導體晶片 11: 膜黏合劑 12: 佈線基板 12a: 第一表面 12b: 第二表面 13: 囊封樹脂 14: 接合墊 14a, 14b, 14c: 接合墊 15: 導電組件 20: 電路保護層 21: 安裝板端子 22: 焊膏 23: 安裝板 24, 120: 佈線層 100: 半導體裝置 101: 墊 101a, 101b, 101c: 墊 121: 凸形組件 122a, 122b, 124: 金屬插塞 122b1: 金屬插塞 122b2: 金屬插塞 122b_11: 金屬插塞 122b_12: 金屬插塞 124_12: 金屬插塞 123: 基底組件 PG: 插塞群組 PG1: 插塞群組 PG2: 插塞群組 PG3: 插塞群組 1: Semiconductor package 2: Printed Wiring Board 3, 3a, 3b, 3c, 3d: solder balls 10: Semiconductor Wafer 11: Membrane Adhesive 12: Wiring substrate 12a: First surface 12b: Second surface 13: Encapsulation resin 14: Bonding pad 14a, 14b, 14c: Bonding pads 15: Conductive components 20: Circuit protection layer 21: Mounting plate terminal 22: Solder paste 23: Mounting plate 24, 120: wiring layer 100: Semiconductor devices 101: pad 101a, 101b, 101c: Pads 121: Male component 122a, 122b, 124: Metal plugs 122b1: Metal plug 122b2: Metal plug 122b_11: Metal plug 122b_12: Metal plug 124_12: Metal plug 123: Base Assembly PG: plug group PG1: Plug group PG2: Plug group PG3: Plug group

圖1係根據一第一實施例之一半導體裝置之一橫截面視圖。FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment.

圖2A係一半導體封裝之一俯視圖。FIG. 2A is a top view of a semiconductor package.

圖2B係一半導體封裝之一仰視圖。FIG. 2B is a bottom view of a semiconductor package.

圖3係根據一第二實施例之一半導體裝置之一橫截面視圖。3 is a cross-sectional view of a semiconductor device according to a second embodiment.

圖4係一半導體封裝之一仰視圖。FIG. 4 is a bottom view of a semiconductor package.

圖5係根據一第三實施例之一半導體裝置之一橫截面視圖。5 is a cross-sectional view of a semiconductor device according to a third embodiment.

1: 半導體封裝 2: 印刷佈線板 3, 3a, 3b: 焊球 10: 半導體晶片 11: 膜黏合劑 12: 佈線基板 12a: 第一表面 12b: 第二表面 13: 囊封樹脂 14: 接合墊 15: 導電組件 20: 電路保護層 21: 安裝板端子 22: 焊膏 23: 安裝板 24, 120: 佈線層 100: 半導體裝置 101: 墊 121: 凸形組件 122a, 122b: 金屬插塞 1: Semiconductor package 2: Printed Wiring Board 3, 3a, 3b: Solder balls 10: Semiconductor Wafer 11: Membrane Adhesive 12: Wiring substrate 12a: First surface 12b: Second surface 13: Encapsulation resin 14: Bonding pad 15: Conductive components 20: Circuit protection layer 21: Mounting plate terminal 22: Solder paste 23: Mounting plate 24, 120: wiring layer 100: Semiconductor devices 101: pad 121: Male component 122a, 122b: metal plug

Claims (20)

一種半導體封裝，其包括： 一佈線基板，其具有一第一表面及與該第一表面相對之一第二表面； 一接合墊，其位於該佈線基板之該第一表面上； 一佈線層，其位於該佈線基板中介於該第一表面與該第二表面之間； 一第一導電插塞，其自該佈線層延伸穿過該佈線基板至該第一表面，該第一導電插塞連接至該接合墊； 一第二導電插塞，其自該佈線層延伸穿過該佈線基板至該第二表面，該第二導電插塞電連接至該接合墊； 一第三導電插塞，其自該佈線層延伸穿過該佈線基板至該第二表面，該第三導電插塞電連接至該接合墊； 一半導體晶片，其經安裝在該第一表面上，且具有電連接至該接合墊之一墊端子； 一第一焊球，其位於該佈線基板之該第二表面上，並電連接至該第二導電插塞；及 一第二焊球，其位於該佈線基板之該第二表面上，並電連接至該第三導電插塞。 A semiconductor package comprising: A wiring substrate having a first surface and a second surface opposite to the first surface; a bonding pad located on the first surface of the wiring substrate; a wiring layer located in the wiring substrate between the first surface and the second surface; a first conductive plug extending from the wiring layer through the wiring substrate to the first surface, the first conductive plug being connected to the bonding pad; a second conductive plug extending from the wiring layer through the wiring substrate to the second surface, the second conductive plug being electrically connected to the bonding pad; a third conductive plug extending from the wiring layer through the wiring substrate to the second surface, the third conductive plug being electrically connected to the bonding pad; a semiconductor chip mounted on the first surface and having a pad terminal electrically connected to the bonding pad; a first solder ball located on the second surface of the wiring substrate and electrically connected to the second conductive plug; and A second solder ball is located on the second surface of the wiring substrate and is electrically connected to the third conductive plug. 如請求項1之半導體封裝，其中該等第一及第二焊球具有相同之組合物。The semiconductor package of claim 1, wherein the first and second solder balls have the same composition. 如請求項2之半導體封裝，其進一步包括： 一間隔元件，其位於該第二表面上介於該第二焊球與該第三導電插塞之間。 Such as the semiconductor package of claim 2, which further includes: A spacing element is located on the second surface between the second solder ball and the third conductive plug. 如請求項3之半導體封裝，其中該間隔元件包括一環形絕緣樹脂結構及該環形絕緣樹脂結構內之一金屬插塞。The semiconductor package according to claim 3, wherein the spacing element comprises an annular insulating resin structure and a metal plug in the annular insulating resin structure. 如請求項1之半導體封裝，其進一步包括： 一間隔元件，其位於該第二表面上介於該第二焊球與該第三導電插塞之間。 Such as the semiconductor package of claim 1, which further includes: A spacing element is located on the second surface between the second solder ball and the third conductive plug. 如請求項5之半導體封裝，其中該間隔元件包括一環形絕緣樹脂結構及該環形絕緣樹脂結構內之一金屬插塞。The semiconductor package as claimed in claim 5, wherein the spacing element comprises an annular insulating resin structure and a metal plug in the annular insulating resin structure. 如請求項1之半導體封裝，其中該等第一及第二焊球沿正交於該第二表面之一方向具有不同之長度。The semiconductor package according to claim 1, wherein the first and second solder balls have different lengths along a direction normal to the second surface. 如請求項1之半導體封裝，其中該等第一及第二焊球具有不同之組合物。The semiconductor package of claim 1, wherein the first and second solder balls have different compositions. 如請求項1之半導體封裝，其中該第二焊球之銀含量低於該第一焊球之銀含量。The semiconductor package according to claim 1, wherein the silver content of the second solder ball is lower than the silver content of the first solder ball. 如請求項1之半導體封裝，其中該第一焊球之銅含量高於該第二焊球之銅含量。The semiconductor package according to claim 1, wherein the copper content of the first solder ball is higher than the copper content of the second solder ball. 如請求項1之半導體封裝，其中 該第一焊球係一含鉍合金，且 該第二焊球不含鉍。 Such as the semiconductor package of claim 1, wherein The first solder ball is a bismuth-containing alloy, and The second solder ball does not contain bismuth. 如請求項1之半導體封裝，其進一步包括： 樹脂，其覆蓋該佈線基板之該第一表面、該接合墊及該半導體晶片。 Such as the semiconductor package of claim 1, which further includes: resin covering the first surface of the wiring substrate, the bonding pad and the semiconductor chip. 如請求項1之半導體封裝，其進一步包括： 一印刷電路板，其具有其上具有板端子之一安裝表面。 Such as the semiconductor package of claim 1, which further includes: A printed circuit board having a mounting surface with board terminals thereon. 如請求項13之半導體封裝，其中該等第一及第二焊球連接至該印刷電路板之該第一表面上之不同板端子。The semiconductor package of claim 13, wherein the first and second solder balls are connected to different board terminals on the first surface of the printed circuit board. 如請求項13之半導體封裝，其中該等第一及第二焊球連接至該印刷電路板之該第一表面上之同一板端子。The semiconductor package of claim 13, wherein the first and second solder balls are connected to the same board terminal on the first surface of the printed circuit board. 一種半導體裝置，其包括： 一佈線基板，其具有一第一表面及與該第一表面相對之一第二表面； 一接合墊，其位於該佈線基板之該第一表面上； 一佈線層，其位於該佈線基板中介於該第一表面與該第二表面之間； 一第一導電插塞，其自該佈線層延伸穿過該佈線基板至該第一表面，該第一導電插塞連接至該接合墊； 一第二導電插塞，其自該佈線層延伸穿過該佈線基板至該第二表面，該第二導電插塞電連接至該接合墊； 一第三導電插塞，其自該佈線層延伸穿過該佈線基板至該第二表面，該第三導電插塞電連接至該接合墊； 一半導體晶片，其經安裝在該第一表面上，且具有電連接至該接合墊之一墊端子； 一第一焊球，其位於該佈線基板之該第二表面上，並電連接至該第二導電插塞； 一第二焊球，其位於該佈線基板之該第二表面上，並電連接至該第三導電插塞；及 一印刷電路板，其具有其上具有板端子之一安裝表面，其中 該第一焊球及該第二焊球連接至該等板端子。 A semiconductor device comprising: A wiring substrate having a first surface and a second surface opposite to the first surface; a bonding pad located on the first surface of the wiring substrate; a wiring layer located in the wiring substrate between the first surface and the second surface; a first conductive plug extending from the wiring layer through the wiring substrate to the first surface, the first conductive plug being connected to the bonding pad; a second conductive plug extending from the wiring layer through the wiring substrate to the second surface, the second conductive plug being electrically connected to the bonding pad; a third conductive plug extending from the wiring layer through the wiring substrate to the second surface, the third conductive plug being electrically connected to the bonding pad; a semiconductor chip mounted on the first surface and having a pad terminal electrically connected to the bonding pad; a first solder ball located on the second surface of the wiring substrate and electrically connected to the second conductive plug; a second solder ball located on the second surface of the wiring substrate and electrically connected to the third conductive plug; and A printed circuit board having a mounting surface having board terminals thereon, wherein The first solder ball and the second solder ball are connected to the board terminals. 如請求項16之半導體裝置，其中該等第一及第二焊球具有不同之組合物。The semiconductor device according to claim 16, wherein the first and second solder balls have different compositions. 如請求項16之半導體裝置，其進一步包括： 一間隔元件，其位於該第二表面上介於該第二焊球與該第三導電插塞之間，其中 該等第一及第二焊球沿正交於該第二表面之一方向具有不同之長度。 The semiconductor device according to claim 16, further comprising: a spacing element located on the second surface between the second solder ball and the third conductive plug, wherein The first and second solder balls have different lengths along a direction perpendicular to the second surface. 如請求項16之半導體裝置，其中該等第一及第二焊球連接至該印刷電路板之該安裝表面上之不同板端子。The semiconductor device according to claim 16, wherein the first and second solder balls are connected to different board terminals on the mounting surface of the printed circuit board. 如請求項16之半導體裝置，其中該等第一及第二焊球連接至該印刷電路板之該安裝表面上之同一板端子。The semiconductor device according to claim 16, wherein the first and second solder balls are connected to the same board terminal on the mounting surface of the printed circuit board.
TW110146753A 2021-03-16 2021-12-14 Semiconductor package and semiconductor device TWI782817B (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2021042776A JP2022142564A (en) 2021-03-16 2021-03-16 Semiconductor package and semiconductor device
JP2021-042776 2021-03-16
US17/411,950 US20220302001A1 (en) 2021-03-16 2021-08-25 Semiconductor package and semiconductor device
US17/411,950 2021-08-25

Publications (2)

Publication Number Publication Date
TW202238889A TW202238889A (en) 2022-10-01
TWI782817B true TWI782817B (en) 2022-11-01

Family

ID=83246331

Family Applications (1)

Application Number Title Priority Date Filing Date
TW110146753A TWI782817B (en) 2021-03-16 2021-12-14 Semiconductor package and semiconductor device

Country Status (2)

Country Link
CN (1) CN115084078A (en)
TW (1) TWI782817B (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180122790A1 (en) * 2015-10-30 2018-05-03 Samsung Electronics Co., Ltd. Semiconductor package
US20190035738A1 (en) * 2013-11-11 2019-01-31 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package
TW201947679A (en) * 2017-05-18 2019-12-16 精材科技股份有限公司 Chip package and method for forming the same
TW202006842A (en) * 2018-07-16 2020-02-01 聯華電子股份有限公司 Semiconductor package structure and method for forming the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190035738A1 (en) * 2013-11-11 2019-01-31 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package
US20180122790A1 (en) * 2015-10-30 2018-05-03 Samsung Electronics Co., Ltd. Semiconductor package
TW201947679A (en) * 2017-05-18 2019-12-16 精材科技股份有限公司 Chip package and method for forming the same
TW202006842A (en) * 2018-07-16 2020-02-01 聯華電子股份有限公司 Semiconductor package structure and method for forming the same

Also Published As

Publication number Publication date
TW202238889A (en) 2022-10-01
CN115084078A (en) 2022-09-20

Similar Documents

Publication Publication Date Title
US6201302B1 (en) Semiconductor package having multi-dies
US7579690B2 (en) Semiconductor package structure
US7982298B1 (en) Package in package semiconductor device
US6781242B1 (en) Thin ball grid array package
US8072770B2 (en) Semiconductor package with a mold material encapsulating a chip and a portion of a lead frame
US20060076665A1 (en) Package stack and manufacturing method thereof
US11869829B2 (en) Semiconductor device with through-mold via
TWI756275B (en) Improved fan-out ball grid array package structure and process for manufacturing the same
US7696618B2 (en) POP (package-on-package) semiconductor device
US20040188818A1 (en) Multi-chips module package
US20100289145A1 (en) Wafer chip scale package with center conductive mass
KR100839075B1 (en) Semi-conduct package and manufacturing method thereof
TWI782817B (en) Semiconductor package and semiconductor device
US20220302001A1 (en) Semiconductor package and semiconductor device
TWI582905B (en) Chip package structure and manufacturing method thereof
US20090284941A1 (en) Semiconductor package, mounting circuit board, and mounting structure
US20120292756A1 (en) Semiconductor device with heat spreader
JP2010219554A (en) Semiconductor device and electronic controller using the same
US20050167827A1 (en) Solder alloy and semiconductor device
CN113130473A (en) Chip packaging structure
JP2005057271A (en) Semiconductor chip package and stacked module having functional part and packaging part arranged horizontally on common plane
KR100437821B1 (en) semiconductor package and metod for fabricating the same
US8531022B2 (en) Routable array metal integrated circuit package
KR100641564B1 (en) Method for fabricating chip size package using anisotropic conductive film
JP3462465B2 (en) Semiconductor package mounting structure