TWI776338B - Compiler adapted in graph processing unit and non-transitory computer-readable medium - Google Patents

Abstract

A compiler includes a front-end module, an optimization module, and a back-end module. The front-end module pre-processes a source code to generate an intermediate code. The optimization module optimizes the intermediate code. The back-end module translates the optimized intermediate code to generate a machine code. Optimization includes translating a branch instruction in the intermediate code into performing the following operations: building a post dominator tree for the branch instruction to find an immediate post dominator of the branch instruction as a convergent node of a first path and a second path of the branch instruction; inserting a specific instruction in the front end of the convergent node, so that on the condition that the specific instruction in the first path is executed, it jumps to executes the instructions of the second path.

Description

Compiler and non-transitory computer-readable storage medium for graphics processor

The present invention relates to the technical field of compilers, in particular to a compiler applied to a graphics processor.

In recent years, the rise of the Internet of Things (IoT) and the rapid development of artificial intelligence, machine learning and other fields have greatly increased the amount of data processing. Traditional cloud computing has been unable to cope with such real-time huge data processing, so it is replaced by decentralized computing (for example, fog computing, edge computing, end user computing). Application Architecture. For example, edge computing moves the computing of applications, data and services from the central node of the network to the edge nodes in the network logic for processing. In other words, edge computing decomposes large-scale services that were originally handled entirely by central nodes, cut them into smaller and easier-to-manage parts, and distribute them to edge nodes for processing. The edge node is closer to the user terminal device, which can speed up the processing and transmission of data and reduce the delay.

Therefore, the General Purpose Graph Processing Unit (GPGPU) has been widely used in such applications that need to calculate a large amount of data and can be highly parallelized. In addition to processing graphics data, this type of graphics processing unit can also be used to calculate general-purpose computing tasks originally handled by the central processing unit, and these general-purpose computing tasks usually have nothing to do with graphics processing. Due to the powerful parallel processing capabilities and programmable pipelines of modern graphics processors, general graphics processing is easier to handle when faced with single instruction stream, multiple data streams (SIMD) and the amount of data processing is much larger than the needs of data scheduling and transmission. The performance of the device can greatly exceed the traditional central processing unit.

However, most graphics processors use each vendor's own system architecture and compiler, which usually only support applications using their own defined architecture and language. Even if these manufacturers have released some services for open source software support, the compiler and other related software or hardware still have to use their definitions. For example, the traditionally adopted Open Computing Language (OpenCL) compiler is AMD CLOC, which is closed source software and only available for use on the X86 platform. In other words, developers cannot modify it, add instructions, or optimize it. Therefore, there are certain difficulties in development and use. Therefore, how to provide a portable OpenCL compilation platform and an optimizing compiler to improve the performance of a graphics processor supporting OpenCL is a current issue.

An object of the present invention is to provide a compiler applied to a graphics processor and a non-transitory computer-readable storage medium.

In order to achieve the above object, the present invention provides a compiler applied to a graphics processor capable of general-purpose operations, configured to compile an application program executed by the graphics processor to generate machine code corresponding to the application program For execution by a plurality of streaming multiprocessors in the graphics processor. The compiler includes front-end modules, optimization modules, and back-end modules. The front end module is configured to preprocess the source code corresponding to the application to generate intermediate code. The optimization module is configured to optimize the intermediate code. The backend module is configured to translate the optimized intermediate code to generate machine code. The optimization process includes translating each branch instruction in the intermediate code to perform the following operations: building an inverse dominance tree for the branch instruction to find a direct inverse dominance point of the branch instruction as the instruction of the first path of the branch instruction and the first path of the branch instruction. A convergent node of the instructions of the two paths; and inserting a specific instruction at the front end of the convergent node, so that when the instruction of the first path of the branch instruction is executed, after the specific instruction on the first path is executed, jump to the execution of the branch instruction. The instruction of the second path does not continue to execute the instruction started by the convergent node until the specific instruction on the second path is executed.

In an embodiment of the present invention, branch instructions are simultaneously executed by a plurality of stream processors included in one of the assigned stream multiprocessors, wherein the instructions of the first path are executed by the streams A plurality of first stream processors and a plurality of second stream processors in the processor are executed concurrently using the first thread mask, and instructions of the second path are executed by the first stream processors and the second stream processors The stream processors use the second thread mask to execute concurrently.

In an embodiment of the present invention, when the specific instructions on the first path are executed, only the results executed by the first stream processors are stored, and before the specific instructions on the second path are executed , only the results of execution by the second stream processors are stored.

In an embodiment of the present invention, when executing the instruction of the first path of the branch instruction, after the specific instruction is executed, the first thread mask is terminated; and when executing the instruction of the second path of the branch instruction When executing the instruction, after the specific instruction is executed, the use of the second thread mask is terminated.

In an embodiment of the present invention, the optimization process further includes translating each call function instruction in the intermediary code to perform the following operation: direct all contents of the function called by the call function instruction to the function using the call instruction inline expansion in the caller of .

In an embodiment of the present invention, the optimization process further includes translating each loop instruction in the intermediate code to perform the following operations: analyzing the number of loops for the loop instruction; The number of loops is fully expanded.

In one embodiment of the invention, the front end module is a clang compiler configured to generate intermediate code defined by the underlying virtual machine.

In an embodiment of the present invention, the preprocessing includes macro processing, static analysis, and generating a syntax tree corresponding to the source code.

The present invention also provides a non-transitory computer-readable storage medium configured to store a plurality of instructions that, when executed by a processor in a computer system, cause the processor to execute a compilation method for the computer system An application program executed by a graphics processor in the graphics processor is compiled to generate a machine code corresponding to the application program for execution by a plurality of streaming multiprocessors in the graphics processor, and the compiling method includes: compiling the corresponding application program A source code of a source code is preprocessed to generate an intermediate code; an optimization process is performed on the intermediate code; and a translation process is performed on the optimized intermediate code to generate the machine code; wherein the optimization process includes the intermediate code Each branch instruction in the code is translated to perform the following operations: build a reverse dominator tree for the branch instruction to find a direct reverse dominator point of the branch instruction as an instruction of a first path of the branch instruction and a first A convergent node of the instruction of the two paths; and inserting a specific instruction at the front end of the convergent node, so that when the instruction of the first path of the branch instruction is executed, after the specific instruction on the first path is executed, jump to The instruction of the second path of the branch instruction is executed until the specific instruction on the second path is executed, and then the instruction started by the convergent node is continued to be executed.

In the present invention, the above-mentioned branch-related instructions, call instructions and loop instructions are correspondingly optimized in the compilation process, so that the software stack can better cooperate with the operation of the hardware, and the overall performance is greatly improved, thereby providing developers with a convenient open source execution environment. .

In order to make the above-mentioned and other objects, features and advantages of the present invention more clearly understood, the preferred embodiments of the present invention will be exemplified below and described in detail in conjunction with the accompanying drawings.

Please refer to FIG. 1, which is a block diagram of a graphics processor 100 according to a preferred embodiment of the present invention. The general-purpose graphics processor 100 is a single instruction multiple thread (Single Instruction Multiple Thread, SIMT) architecture, which includes an interconnection network module 110 , a plurality of Streaming Multiprocessors (SM) 120 , and a work scheduling module 130 , and memory 140 . The interconnecting network module 110 is electrically connected to each of the streaming multiprocessors 120, the work scheduling module 130, and the memory 140, and is configured to transmit data among these elements. Streaming multiprocessor 120 is configured to perform operations and execute instructions. Each streaming multiprocessor 120 includes a warp scheduling module 121 and a plurality of Streaming Processors (SPs) 122, the purpose of which will be described later. The workgroup scheduling module 130 is configured to communicate with an external central processing unit (not shown), receive work assigned from the central processing unit, and schedule the work to the streaming multiprocessor 120 for execution.

A thread is the smallest unit of a program executed by the general-purpose graphics processor 100 , and its schedule is dispatched through two different scheduling modules, namely the work group scheduling module 130 and the thread bundle scheduling module 130 . program module 121. When the central processing unit sends a new job, the work group scheduling module 130 receives the program to be executed in the unit of thread grid (grid), cuts and schedules it, and then uses the thread block ( block) is dispatched to each streaming multiprocessor 120 for execution. After receiving the thread block, a stream multiprocessor 120 divides it into multiple thread bundles according to the width of the single instruction multiple data stream (SIMD), and performs operations in units of thread bundles. A plurality of thread bundles are scheduled through the thread bundle scheduling module 121 and dispatched to each stream processor 122 for execution. Multiple threads in the same thread bundle are simultaneously operated by the stream processor 122 in the stream multiprocessor 120 . For example, if the stream multiprocessor 120 contains 32 stream processors 122 (ie, the SIMD width is 32), then each thread bundle will be arranged to have as many as 32 threads and the 32 The stream processors 122 are executed in parallel at the same time. If there are less than 32 threads in the thread bundle, some corresponding stream processors 122 will not work at the moment. It should be understood that the program executed on the graphics processor is generally called a kernel, and a kernel corresponds to a thread grid (grid), each thread grid contains multiple thread blocks (blocks), each A thread block contains multiple threads.

Please refer to FIG. 2. FIG. 2 is a schematic diagram of a software level of a general-purpose graphics processor 100 according to a preferred embodiment of the present invention. As shown in Figure 2, the top layer is the TensorFlow execution platform (runtime) 210, on which developers can use the supported application libraries in TensorFlow to support machine learning and deep learning model development. Then, the general-purpose graphics processor 100 is supported by the OpenCL execution platform 220 to achieve a large number of parallel operations to improve performance. In other words, both TensorFlow CNN applications and OpenCL applications can be accelerated on the general-purpose graphics processor 100. Finally, the Heterogeneous System Architecture (HSAHSA) execution platform 230 provides a common hardware interface, and a bridge between software and hardware is provided to communicate with the general-purpose graphics processor 100, so as to reduce the design complexity of the OpenCL execution platform 220 . The general-purpose graphics processor 100 starts to operate after receiving the information from the software side, and finally transmits the result back to the memory of the CPU side, so as to achieve the effect of program acceleration.

However, if the software level of the general-purpose graphics processor 100 is not supported by a compiler, the entire system platform of the general-purpose graphics processor 100 cannot be completely established, so the compiler occupies a very important position in the entire software and hardware system. In the present invention, the compiler 240 is an OpenCL LLVM compiler to support the general-purpose graphics processor 100, wherein the compiler 240 can optimize and customize its own instruction set, so as to achieve good cooperation between hardware and software, thereby improving execution s efficiency.

Specifically, for the TensorFlow execution platform 210, in order to enable TensorFlow applications to be executed under the OpenCL architecture, it is first necessary to understand the matching scheme of TensorFlow Stream Executor and TF-Coriander. TensorFlow Stream Executor is a common interface to the Kernel API defined by Google for TensorFlow. The architecture concept uses Stream Executor as the hardware abstraction layer of each target platform. The Kernel application above will perform resource management-related commands for virtual devices through a unified interface, such as memory allocation, command dispatch, and program flow monitoring (Kernel). Process Monitoring) and so on. Platform developers can also put platform-related optimization programs into Kernel implementation to optimize the execution efficiency of each Kernel on the platform.

The native TensorFlow GPU Support only supports GPU devices using CUDA Programming Language. For other platforms, developers need to design Stream Executor for the target platform. Since TensorFlow provides many types of Kernel Operation, it will require a lot of labor costs to provide more complete support for the platform, and if TensorFlow is updated, it will be difficult to synchronize and maintain. In order to reduce the complexity of the newly added hardware, a CUDA-on-CL architecture is proposed, which uses Coriander's Source-to-Source Compiler to translate native CUDA applications into Host Code and Device Code executable by OpenCL Device. This converts TensorFlow's native CUDA code into OpenCL Device Kernel, and designs a Stream Executor for OpenCL, which is an independent branch of TensorFlow, namely TF-Coriander.

TF-Coriander translates Tensorflow's built-in CUDA Code into OpenCL Device Kernel Code through Coriander Compiler, and replaces cuBlast and cuDNN in CUDA with OpenC libraries such as clBLAST[11], DNN[12], and builds Tensorflow for OpenCL devices is supported for OpenCL 1.2 devices.

In addition, for the HSA execution platform 230 , today's computing platforms are generally composed of heterogeneous hardware such as a central processing unit (CPU), a graphics processing unit (GPU), or an application-specific chip (ASIC). To this end, Apple proposes an open source language framework, the Open Computing Language (Open Computing Language). OpenCL provides a unified abstract software architecture and language for various hardware architectures, and uses the same application programming interface to connect to the target hardware, providing such as Device Memory Allocation, Device Kernel Compilation, Device Code Dispatching and other functions. In order to support the hardware of each platform, the OpenCL execution platform is implemented in the form of Shared Library (Linux)/Dynamic Loadable Library (NT) in the software architecture. Each hardware development The Chamber implements APIs for its hardware according to the OpenCL specification.

The OpenCL application architecture divides the code into Host Code and Device Code (kernel). Most of the content executed by Host Code is the Host Code composed of C++ Classes and Runtime API provided by the OpenCL execution platform. For target devices such as graphics processors/accelerators, it is necessary to write OpenCL Kernel Code separately and follow the OpenCL Programming mode. The design has been dispatched to the Kernel. OpenCL Kernel Code is a C99-based programming language, which, together with the Kernel API, provides parallel computing capabilities for task division/data division.

For the HSA execution platform 230, in order to integrate hardware platforms with different architectures such as CPU, GPU, and DSP, the HSA Foundation proposes a software architecture of Heterogeneous System Architecture (HSA). Similar to the software architecture provided by OpenCL A common parallel computing software development framework, HSA aims to provide a common hardware interface. Unlike OpenCL, which standardizes a unified application development interface, HSA standardizes a unified hardware operation interface to simplify the upper layer (such as OpenCL, etc.) and The development complexity of the underlying bridge interface.

In this embodiment, in order to provide the OpenCL Kernel application and the special operation instructions supported by the general-purpose graphics processor 100 , the device function library 250 needs to be additionally set up to cooperate with the compiler 240 . The device library 250 includes an OCKL module 251 , an OCML module 252 and an OpenCL module 253 . The OCL module 251 is configured to provide an API for the relevant parameters (eg, work item ID, thread block size, thread grid size, etc.) required by the Kernel at runtime. The OCML module 252 is configured to provide an application programming interface related to mathematical operations. The OpenCL module 253 is configured to provide an OpenCL Kernel API to correspond to the functions of the OCKL module 215 and the OCML module 252. Through the device library 250, the compiler 240 can provide OpenCL Kernel API-related resources for developers to use its internal special operation instruction set.

Please refer to FIG. 3, which is a block diagram of a compiler 240 according to a preferred embodiment of the present invention. The compiler 240 may be implemented as a computer program and stored in a storage device. The storage device includes a non-transitory computer-readable recording medium or other device with storage function. The computer program includes one or more computer-executable instructions. Computer-executable instructions may be executed by one or more processors to perform the compilation operations of compiler 240 . Specifically, the compiler 240 may be used in a general-purpose graphics processor in a computer system. The computer system includes a central processing unit, the general-purpose graphics processing unit, and a memory connected to the central processing unit. The compiler 240 can be stored in the memory, and is executed by the central processing unit to compile an application (eg, Kernel written in the OpenCL language) executed by the general-purpose graphics processor 100 to generate a corresponding code of the application. Machine code (binary code), the compiled machine code can be executed by the streaming multiprocessor 120 such as the general-purpose graphics processor 100 in FIG. Repeat. The compiler 240 can be divided into a front-end module 310 , an optimization module 320 and a back-end module 330 according to functions. The front end module 310 is configured to preprocess the source code (source code) corresponding to the application to generate an intermediate representation (IR). The optimization module 320 is configured to perform optimization processing on the mediation code. Backend module 330 is configured to translate the optimized intermediate code into assembly code, and to call an assembler to translate the assembly code into machine code.

In this embodiment, the compiler 240 adopts the LLVM architecture as a development platform. LLVM takes componentization as the design goal when designing the compiler architecture, and divides each compiler function into individual corresponding sub-modules, so that the core components of the compiler can be shared between different languages and different target architectures. The transmission mechanism of the intermediate data adopts the intermediate language (LLVM-IR) defined by LLVM, which is a platform-independent high-level abstract intermediate code that can be used by the front-end module 310 and the back-end module 330 .

Specifically, the front-end module 310 is responsible for language-related processing. For example, the front-end module 310 can translate the source code to generate an internal required abstract syntax tree (AST) data structure, pre-process the source code, and then translate the processed source code to The aforementioned LLVM-IR is generated for processing by the backend module 330 . Preprocessing may include macro processing, static analysis, and the like. Macros handle language-specific functions such as item expansion, constant term handling, etc. Static analysis is to analyze the characteristics of the code, such as program size, use of variables, program complexity, performance and so on.

In this embodiment, the front-end module 310 may be a Clang compiler to generate the corresponding LLVM-IR. In one embodiment, Clang can first perform the aforementioned preprocessing on the source code, and then translate the source code into the syntax tree Clang AST defined by Clang through the Token based Parser. After generating the Clang AST, Clang can perform language-related optimizations on it and convert the Clang AST to LLVM-IR.

The optimization module 320 can perform optimization processing on LLVM-IR, such as constant preprocessing, conditional optimization and other language-dependent optimization processing.

The back-end module 330 is used to unify the instructions of the LLVM-IR generated by the front-end module 310 and the optimization module 320, and generate the target executable instructions and file formats. In other words, the backend module 330 can translate the LLVM-IR to generate machine code/files executable by the streaming multiprocessor 120 in the general-purpose graphics processor 100 .

In the present invention, for some instructions contained in the intermediate code (ie, LLVM-IR), the optimization module 320 of the compiler 240 performs further optimization processing, which is described below.

In one embodiment, when the intermediate code includes a branch instruction, the optimization module 320 can perform optimization processing to translate it into corresponding machine code that performs the following operations: building a post dominator tree for the branch instruction ) to find an immediate post dominator (IPDOM) of the branch instruction as the reconverge point of the instruction of the first path and the instruction of the second path of the branch instruction; A specific instruction (eg, a jump instruction) such that when an instruction of the first path of the branch instruction is executed, when the specific instruction on the first path is executed, it jumps to the instruction of the second path of the branch instruction, rather than continuing to execute convergence The remaining instructions starting from the node will not continue to execute the remaining instructions starting from the convergent node until the specific instructions on the second path are executed.

Please refer to FIG. 4 , which is a schematic diagram illustrating the operation of the branch instruction 400 according to an embodiment of the present invention. As shown in Figure 4, the branch instruction means that the conditional execution of different operations. In the condition judgment block 410, if the condition A for executing the A block 420 is met, the execution proceeds to the first path where the A block 420 is located, and if the condition B for executing the B block 430 is met, the execution proceeds to the second path where the B block 430 is located. As mentioned above, the general-purpose graphics processor 100 adopts the SIMT architecture, that is, the same instruction will be executed by multiple stream processors at the same time, but the executed data addresses are different. For branch instructions, divergence will occur when encountering different data and the target address after branching is different, and finally, because the thread (lane) target in the stream processor is inconsistent, it cannot be executed in SIMT mode . In this embodiment, the general-purpose graphics processor 100 uses a masked execution mode to execute divergent instructions. Specifically, the general-purpose graphics processor 100 still uses the SIMT mode to execute different instructions, but uses a thread mask (lane mask) to determine which threads (ie, assign threads from the thread bundle scheduling module) channel to the stream processor) is valid, and according to the thread mask to decide whether the execution result should be written/stored to the cache/register/memory, wait until the end of the process and then switch to another thread mask Go ahead and do it.

Taking the branch instruction 400 in FIG. 4 as an example, in this example, it is assumed that there are 6 threads in the thread bundle, but 3 of them meet the condition A and pass through the stream processor that receives the data from the thread 441 to execute, and the other 3 threads meet condition B and execute through the stream processor that receives data from thread 442. Therefore, for the stream multiprocessor executing this thread bundle, the 6 threads will still be executed simultaneously by the 6 stream processors in the stream multiprocessor connected to threads 441 and 442 of the first path ( Contains instructions from A-block 410 and C-block 450), but using the first thread mask while executing. Therefore, after executing the instructions of the first path, only the operation result of the data transmitted through the thread 441 is written/stored in the cache/register/memory, while the operation result of the data transmitted through the thread 442 is will be discarded. Next, the 6 stream processors connected to threads 441 and 442 continue to execute the instructions of the second path (including B block 420 and C block 450 ) at the same time, but use the second thread mask while executing. Therefore, after executing the instructions of the second path, only the operation result of the data transmitted through the thread 442 is written/stored in the cache/register/memory, while the operation result of the data transmitted through the thread 441 is will be discarded. In one embodiment, the first thread mask and the second thread mask may have, for example, a data structure with a number of bits corresponding to the number of threads, each bit corresponds to a thread, and the corresponding bit is determined according to the content of the bit. Whether the thread's data is valid. For example, the three bits corresponding to the thread 441 in the first thread mask may all be high-level, and the three bits corresponding to the thread 442 may all be low-level. In the second thread mask, the three bits corresponding to the thread 441 may all be low-level, and the three bits corresponding to the thread 442 may all be high-level. In the thread mask, the operation result of the thread corresponding to the high-level bit is valid, while the operation result of the thread corresponding to the low-level bit is invalid and will not be written. .

In the example in Figure 4, it can be found that for the divergent instructions, the instructions of the C block 450 of the first path and the second path are executed twice. If the instruction of the C block 450 is a huge program, it will be Significantly affects the performance of the entire general-purpose graphics processor.

Please refer to FIG. 5 and FIG. 6 together. FIG. 5 is a schematic diagram of a reverse dominator tree 500 established according to the branch instruction 400 of FIG. 4 , and FIG. 6 is a diagram according to a preferred embodiment of the present invention. A schematic diagram of the corresponding operations after the branch instruction 400 is translated. In this embodiment, after the compiler of the present invention sees the branch instruction 400 in the intermediate code when performing optimization processing, it can perform Post Dominator Tree analysis to establish it as shown in FIG. 6 . Post Dominator Tree 500. From the reverse dominance tree 500, it can be found that all the reverse dominators (Post Dominator, PDOM) and direct reverse dominator (Immediate Post Dominator, IPDOM) owned by A block 420 and B block 430 are C block 450, so it can be Decision C block 450 is the reconverge point after branch instruction 400 diverges. Next, a specific instruction (eg, a jump instruction) can be inserted at the front end of the C block 450, so that when the instruction of the A block 420 of the branch instruction 400 (ie, the instruction of the first path) is executed to the specific instruction, the Instead of continuing to execute the instructions of the C-block, ie, the remaining instructions of the first path starting at the convergent node (including the convergent node's instructions), the instructions of the B-block 430 of the branch instruction 400 (ie, the instructions of the second path) are executed. The branch instruction divergence can be ended when the instruction executing the B block 430 reaches the specific instruction, and the thread mask can be cleared at this time, so that the instruction following the specific instruction (ie, the instruction of the C block 450 ) is simultaneously connected to the branch instruction. The stream processors of the threads 441 and 442 are executed at the same time, which avoids repeated execution, thereby improving the execution efficiency and performance of the general graphics processor 100 .

In one embodiment, when the intermediate code includes a call function (call) instruction, the optimization module 320 can perform optimization processing to translate it into corresponding machine code to perform the following operations: All contents of the callee are directly expanded inline in the caller of the function using the call instruction. Due to the complex divergence problem of the call instruction, the cost of the hardware is increased and the efficiency is not good. Therefore, when the compiler 240 of the present invention processes a call-related instruction, it directly inserts the specified function body and replaces each place where the function is called, that is, the content of the function to be called is directly in the caller (caller) Expand all internally to avoid divergence and thus save the extra time cost of each function call.

In one embodiment, when the intermediate code includes a loop instruction (eg, loop instruction, for instruction, etc.), the optimization module 320 may perform optimization processing on it to translate it into corresponding machine code to perform the following operations: The loop instruction analyzes the number of loops; and all the instructions executed in the loop instruction are expanded according to the number of loops. Because the branch instruction will cause divergence, the streaming multiprocessor will block the dispatch of all instructions after the branch instruction when facing the branch instruction, and wait until the instructions in the pipeline (pipeline) are completed before executing the branch instruction, and wait for the jump After reaching the specified target, subsequent instructions can be dispatched, resulting in a decrease in the efficiency of pipeline usage. In order to reduce the number of instructions required by the branch instruction, this embodiment uses the loop unrolling method to unroll all the instructions in the loop instruction according to the number of times when resources allow, thereby reducing the number of loop instructions during execution. Proportion occupied by inner branch instructions.

To sum up, the general-purpose graphics processor provided by the present invention designs the execution platform of the graphics processor and the corresponding OpenCL LLVM compiler according to the OpenCL specification, thereby providing an application program interface that conforms to and supports OpenCL/TensorFlow. In addition, through the corresponding optimization of the compilation process of the above-mentioned branch-related instructions, call instructions and loop instructions, the software stack can better cooperate with the operation of the hardware, and the overall performance can be greatly improved, thereby providing developers with convenient open source execution. surroundings.

Although the present invention has been disclosed with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the appended patent application.

100 General Purpose Graphics Processors 110 Internet Modules 120 Streaming Multiprocessors 121 Thread bundle scheduling module 122 Stream Processor 130 Job Scheduler Module 140 memory 210 TensorFlow Execution Platform 220 OpenCL Execution Platform 230 Heterogeneous system architecture execution platform 240 Compiler 250 Device Libraries 251 OCKL module 252 OCML modules 253 OpenCL modules 310 Front-end modules 320 Optimization Modules 330 Backend Modules 400 branch instructions 410 Conditional Judgment Block 420 A square 430 B square 441, 442 threads 450 C block 500 reverse dominance tree

FIG. 1 is a block diagram of a graphics processor according to a preferred embodiment of the present invention. FIG. 2 is a schematic diagram of a general-purpose graphics processor software hierarchy according to a preferred embodiment of the present invention. FIG. 3 is a block diagram of a compiler according to a preferred embodiment of the present invention. FIG. 4 is a schematic diagram illustrating the operation of a branch instruction according to an embodiment of the present invention. FIG. 5 is a schematic diagram of a reverse dominator tree established according to the branch instruction of FIG. 4 . FIG. 6 is a schematic diagram illustrating a corresponding operation after translation of a branch instruction according to a preferred embodiment of the present invention.

240 Compiler 310 Front-end modules 320 Optimization Modules 330 Backend Modules

Claims (12)

A compiler configured to compile an application program executed by a graphics processor to generate a machine code corresponding to the application program for execution by a plurality of streaming multiprocessors in the graphics processor , wherein the compiler includes: a front-end module configured to perform a pre-processing on a source code corresponding to the application to generate an intermediate code; an optimization module configured to perform a pre-processing on the intermediate code an optimization process; and a backend module configured to perform a translation process on the optimized intermediate code to generate the machine code; wherein the optimization process includes translating each branch instruction in the intermediate code into Performing the following operations: establishing a reverse dominator tree for the branch instruction to find a direct reverse dominator point of the branch instruction as a convergence node of an instruction of a first path and an instruction of a second path of the branch instruction; and inserting a specific instruction at the front end of the convergence node, so that when executing the instruction of the first path of the branch instruction, after executing the specific instruction on the first path, jump to the second path of executing the branch instruction until the specific instruction on the second path is executed, the instruction from the convergent node will continue to be executed; wherein the optimization process further includes translating each call function instruction in the intermediate code to perform the following operations: All contents of the function called by the call-function instruction are expanded inline directly in the caller of the function using the call-instruction. The compiler of claim 1, wherein the branch instruction is concurrently executed by a plurality of stream processors included in one of the assigned stream multiprocessors, wherein the instruction of the first path is executed by A plurality of first stream processors and a plurality of second stream processors of the stream processors execute concurrently using a first thread mask, and instructions of the second path are processed by the first streams The processor and the second stream processors execute concurrently using a second thread mask. The compiler of claim 2, wherein upon completion of executing the specific instruction on the first path, only the results of execution by the first stream processors are stored, and upon completion of execution on the second path When the specific instruction is executed, only the results executed by the second stream processors are stored. The compiler of claim 2, wherein when executing the instruction of the first path of the branch instruction, after the specific instruction is executed, the first thread mask is terminated; and when executing the instruction of the branch instruction When the instruction of the second path is executed, the use of the second thread mask is terminated after the specific instruction is executed. The compiler of claim 1, wherein the optimizing process further comprises translating each loop instruction in the intermediate code to perform the following operations: analyzing the loop instruction a number of times of a loop; and the loop instruction The instructions executed within the loop are all expanded according to the number of loops. The compiler of claim 1, wherein the front end module is a clang compiler configured to generate the intermediate code defined by the underlying virtual machine. The compiler of claim 6, wherein the preprocessing includes macro processing, static analysis, and generating a syntax tree corresponding to the source code. A non-transitory computer-readable storage medium configured to store a plurality of instructions that, when executed by a processor in a computer system, cause the processor to execute a compilation method for the computer system compiling an application program executed by a graphics processor to generate a machine code corresponding to the application program for execution by a plurality of streaming multiprocessors in the graphics processor, the compiling method includes: compiling the application program corresponding to the application program A source code of the program is preprocessed to generate an intermediate code; an optimization process is performed on the intermediate code; and a translation process is performed on the optimized intermediate code to generate the machine code; wherein the optimization process includes the Each branch instruction in the intermediate code is translated into an instruction that performs the following operations: builds an inverse domination tree for the branch instruction to find a direct inverse domination point of the branch instruction as an instruction of a first path of the branch instruction and an instruction A convergent node of the instruction of the second path; and inserting a specific instruction at the front end of the convergent node, so that when the instruction of the first path of the branch instruction is executed, after the specific instruction on the first path is executed, jump The instruction to execute the second path of the branch instruction does not continue to execute the instruction starting from the convergent node until the specific instruction on the second path is executed; wherein the optimization process also includes each call in the intermediate code Function instructions translate to perform the following operations: All contents of the function called by the call-function directive are expanded inline directly in the caller of the function using the call-directive. The non-transitory computer-readable storage medium of claim 8, wherein the branch instruction is concurrently executed by a plurality of stream processors included in one of the assigned stream multiprocessors, wherein Instructions of the first path are concurrently executed by a plurality of first stream processors and a plurality of second stream processors of the stream processors using a first thread mask, and instructions of the second path are executed by The first stream processors and the second stream processors execute concurrently using a second thread mask. The non-transitory computer-readable storage medium of claim 9, wherein when the specific instruction on the first path is executed, only the results executed by the first stream processors are stored, and in When the specific instruction on the second path is executed, only the results executed by the second stream processors are stored. The non-transitory computer-readable storage medium of claim 9, wherein when executing the instruction of the first path of the branch instruction, after the specific instruction is executed, the first thread mask is terminated; and When executing the instruction of the second path of the branch instruction, after the specific instruction is executed, the use of the second thread mask is terminated. The non-transitory computer-readable storage medium of claim 8, wherein the optimization process further comprises translating each loop instruction in the intermediate code to perform the following operations: Analyzing the number of loops for the loop instruction; and all the instructions executed in the loop instruction are expanded according to the number of loops.

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