TWI774986B - Key storage system and key storage method - Google Patents

Abstract

A key storage method includes: storing a first key by a first key storage in a key storage device; transmitting at least one specific instruction by a key encryption and decryption accelerator; and determining, by the key storage device, the first key storage corresponding to the at least one specific instruction. When the key encryption and decryption accelerator wants to read the first key to perform a specific operation for modifying the first key, the first accelerator transmits the at least one specific instruction to the key storage device, and the at least one specific instruction includes a blocking access signal of the first key and a first key number signal of the first key.

Description

Key storage system and key storage method

The present disclosure relates to a storage system and a storage method, and more particularly, to a key storage system and a key storage method.

Generally speaking, the automated key management mechanism of an Intelligent Key Storage Center (IKSC) allows users to easily store, use, and clear keys. However, when the encryption/decryption accelerator performs operations, if the key is modified, and the user can still read the key content at the same time, this method may lead the user to think that the key has been contaminated, attacked, or even misused the key. The modified key is regarded as the original key, which makes the subsequent operation error. The protection method when modifying the key is, for example, RSA side-channel attack protection. This algorithm will perform key/exponent blinding to prevent attacks.

However, in this algorithm, the private key is numerically obfuscated to avoid third-party attacks, and the user may mistakenly obtain the obfuscated key as the original key, causing errors in subsequent operations. Therefore, how to avoid misidentification or misuse of the key by the user while modifying the key has become one of the problems to be solved in the art.

In order to solve the above problems, one aspect of the present disclosure provides a key storage system. The key storage system includes a key encryption/decryption accelerator and a key storage device. A key encryption/decryption accelerator includes a first accelerator. The first accelerator is used for sending at least one specific instruction. A key storage device includes a first key storage, an arbiter and a core. The first key storage is used for storing a first key. The arbiter is used for receiving and judging a sender of the at least one specific command. The core is used for determining that the at least one specific command corresponds to the first key storage. Wherein, when the first accelerator wants to read the first key to perform a specific operation of modifying the first key, the first accelerator transmits at least one specific instruction to the arbiter, and the at least one specific instruction includes the corresponding first key a blocking access signal and a first key number signal.

Another aspect of the present invention is to provide a key storage method, comprising: storing a first key by a first key storage in a key storage device; sending a key by a key encryption/decryption accelerator at least one specific command; and determining the first key storage corresponding to the at least one specific command by the key storage device. Wherein, when the key encryption/decryption accelerator wants to read the first key to perform a specific operation of modifying the first key, the first accelerator transmits the at least one specific instruction to the key storage device, and the at least one specific instruction includes A blocking access signal and a first key number signal corresponding to the first key.

With the key storage system and key storage method described in this case, when the accelerator is about to modify the key, the accelerator transmits a specific instruction to the key storage device, and the specific instruction is used to instruct the key storage device to block the processor. Access to the key, thereby avoiding the possibility of the processor reading the modified key, resulting in erroneous operations.

The following descriptions are preferred implementations for completing the invention, and are intended to describe the basic spirit of the invention, but are not intended to limit the invention. Reference must be made to the scope of the following claims for the actual inventive content.

It must be understood that words such as "comprising" and "including" used in this specification are used to indicate the existence of specific technical features, values, method steps, operation processes, elements and/or components, but do not exclude possible Plus more technical features, values, method steps, job processes, elements, components, or any combination of the above.

The use of words such as "first", "second", "third", etc. in the claim is used to modify the elements in the claim, and is not used to indicate that there is a priority order, antecedent relationship, or an element Prior to another element, or chronological order in which method steps are performed, is only used to distinguish elements with the same name.

Please refer to FIGS. 1A-1B and 2. FIG. 1A is a block diagram illustrating a key storage system 100 according to an embodiment of the present invention. FIG. 1B is a block diagram illustrating a key storage system 150 according to an embodiment of the present invention. FIG. 2 is a flowchart illustrating a key storage method 200 according to an embodiment of the present invention.

In one embodiment, the key storage system 100 may be implemented by circuitry on a chip. In one embodiment, the key storage system 100 may be a module on a chip. In FIG. 1A , the key storage system 100 includes a key encryption/decryption accelerator 10 and a key storage device 20 .

In one embodiment, the key encryption/decryption accelerator 10 includes an Advanced Encryption Standard (AES) accelerator 12, a Hash Message Authentication Code (HMAC) accelerator 14, and an elliptic curve cryptography (Elliptic Curve Cryptography, ECC) accelerator 16 and/or an RSA (from the initials of inventors Rivest, Shmir and Adleman) accelerator 18.

Among them, the AES encryption algorithm is a segment encryption standard adopted by the federal government of the United States. The AES accelerator 12 implements this algorithm with a hardware circuit, so it can accelerate the operation.

Among them, the HMAC encryption algorithm is a hash function algorithm with a key, a message authentication code based on a hash function, which requires an encryption hash function (such as MD5 or SHA-1) and a key to calculate the message authentication code The HMAC accelerator 14 uses the hardware circuit to implement the algorithm, so it can speed up the operation.

Among them, the ECC encryption algorithm is a public key encryption algorithm based on elliptic curve mathematics. The ECC accelerator 16 implements this algorithm with a hardware circuit, so it can accelerate the operation.

Among them, the RSA encryption algorithm is an asymmetric encryption algorithm, which is widely used in public key encryption and electronic commerce. The RSA accelerator 18 implements this algorithm with a hardware circuit, so it can accelerate the operation.

In one embodiment, the key storage device 20 may be a module in a chip, implemented in a circuit. In one embodiment, the key storage device 20 includes one or more key storages S1 ˜Sn, an arbiter 22 and a core 24 .

In one embodiment, the key storage device 20 may be implemented by a circuit. In one embodiment, it can be implemented as read-only memory, flash memory, floppy disk, hard disk, optical disk, pen drive, tape, network accessible database, or can be easily conceived by those skilled in the art. A storage medium with the same function.

In one embodiment, the key storage S1 in the key storage device 20 is used to store the key K1.

In one embodiment, the key storage device 20 includes a plurality of key storages S1 ˜Sn for storing the keys K1 ˜Kn respectively. For example, the key storage device 20 includes a key storage S1 for storing the key K1, a key storage S2 for storing the key K2, the key storage S3 for storing the key K3 and/or the key storage Sn for storing Key Kn. In one embodiment, the keys K1 to Kn may be generated by the same or different symmetric encryption algorithms or asymmetric encryption algorithms. The symmetric encryption algorithm or the asymmetric encryption algorithm can adopt the existing algorithm, so it is not repeated here.

In one embodiment, the keys K1 to Kn can be pre-written into the key storage system 100 before the chips are shipped.

In one embodiment, the arbiter 22 is used to receive and determine a sender of at least one specific command.

In one embodiment, the arbiter 22 determines that the sender of the specific command is one of the AES accelerator 12 , the HMAC accelerator 14 , the ECC accelerator 16 and/or the RSA accelerator 18 . For example, the arbiter 22 determines that the sender of the specific command is the RSA accelerator 18 .

In one embodiment, the AES accelerator 12 , the HMAC accelerator 14 , the ECC accelerator 16 and the RSA accelerator 18 cannot read keys corresponding to each other. For example, if the RSA accelerator 18 corresponds to the key K1, the AES accelerator 12, the HMAC accelerator 14 and the ECC accelerator 16 cannot access the key K1.

In one embodiment, the core 24 is used to determine the key storage (eg, the key storage S1 ) corresponding to at least one specific instruction.

In one embodiment, the AES accelerator 12, the HMAC accelerator 14, the ECC accelerator 16, and the RSA accelerator 18 can access the corresponding keys for performing certain operations.

The specific operation is, for example, but not limited to, the RSA side-channel attack protection algorithm. The RSA side-channel attack protection algorithm performs key/exponent blinding to prevent attacks.

In one embodiment, when the RSA accelerator 18 substitutes the key K1 into the RSA side-channel attack protection algorithm, in this process, the RSA accelerator 18 will disguise the key K1 as the obfuscated key K1' after the operation to avoid subsequent operations. In other operations or transmission procedures, the third party can obtain the real key K1; however, if the processor 30 (as shown in FIG. 1B ) accesses the key storage S1 at this time, the obfuscated key will be read. K1', resulting in the subsequent operation error of the processor 30.

In order to avoid this problem, when the RSA accelerator 18 wants to perform a specific operation (an operation involving modifying the key K1 to the obfuscated key K1'), the RSA accelerator 18 transmits at least one specific instruction to the key storage device 20, and the at least one The specific command includes a blocking access signal (eg, the signal Block_cpu_read) and a key number signal (eg, the key number signal corresponding to the key K1 can be represented as Block_key_num==K1). The block access signal Block_cpu_read is used to instruct the key storage device 20 to block the processor 30 from accessing the key K1, thereby preventing the processor 30 from reading the possibility of confusing the key K1' (during a specific operation process). , the key K1 is modified into the obfuscated key K1'), resulting in an incorrect operation.

In one embodiment, a circuit can be established between the key encryption/decryption accelerator 10 and the key storage device 20 to transmit a sideband signal, and a specific command is transmitted through the sideband signal. The following are more specific description details.

In one embodiment, when the RSA accelerator 18 wants to read the key K1 to perform a specific operation that modifies the key K1, the RSA accelerator 18 sends at least one specific command to the arbiter 22, the at least one specific command includes a The block access signal (eg, the signal Block_cpu_read) of the key (eg, the key K1 ) and the key number signal (eg, the key number signal corresponding to the key K1 can be expressed as Block_key_num==K1 ).

In one embodiment, when the AES accelerator 12 wants to read the key K2 to perform a specific operation of modifying the key K2, the AES accelerator 12 transmits at least one specific command to the arbiter 22, and the at least one specific command includes an instruction corresponding to the key K2. The blocking access signal (eg, the signal Block_cpu_read) of the key K2 and the key number signal (eg, the key number signal corresponding to the key K2 can be expressed as Block_key_num==K2).

In one embodiment, when the HMAC accelerator 14 wants to read the key K3 to perform a specific operation of modifying the key K3, the HMAC accelerator 14 transmits at least one specific command to the arbiter 22, and the at least one specific command includes a specific command corresponding to the key K3. The blocking access signal (eg, the signal Block_cpu_read) of the key K3 and the key number signal (eg, the key number signal corresponding to the key K3 can be represented as Block_key_num==K3).

In one embodiment, when the ECC accelerator 16 wants to read the key Kn to perform a specific operation of modifying the key Kn, the ECC accelerator 16 transmits at least one specific command to the arbiter 22, and the at least one specific command includes an instruction corresponding to the key Kn. A blocking access signal (eg, the signal Block_cpu_read) of the key Kn and the key number signal (eg, the key number signal corresponding to the key Kn can be represented as Block_key_num==Kn).

Please refer to FIG. 1B, the processor 30 in FIG. 1B can be implemented as a microcontroller, a microprocessor, a digital signal processor, an application specific integrated circuit integrated circuit, ASIC) or a logic circuit.

In one embodiment, the processor 30 is configured to access at least one of the keys K1 ˜Kn in the key storage device 20 .

In one embodiment, the processor 30 can access any one of the keys K1 to Kn. For example, the processor 30 sends the access request signal Read_K1 of the key K1 to the arbiter 22, and the arbiter 22 learns that the access request is requested. After the signal Read_K1 comes from the processor 30 , the core 24 is notified to read the key K1 from the key storage S1 and transmit it to the processor 30 .

In one embodiment, when the RSA accelerator 18 wants to read the key K1 to perform a specific operation of modifying the key K1, the RSA accelerator 18 transmits the block access signal Block_cpu_read and the key number signal corresponding to the key K1 Block_key_num==K1 to the arbiter 22, representing the blocking key K1 being accessed by the processor 30.

In other words, when the processor 30 wants to access at least one of the keys K1 to Kn (eg, the key K1 ), a current key number signal (eg, Block_key_num==K1 ) and the key corresponding to the key When the key number signal (for example, Block_key_num==K1) is the same, and the key storage device 20 has previously received the block access signal Block_cpu_read and the key number signal Block_key_num==K1 corresponding to the key K1, the processor 30 receives a Access failure signal Read_Fail.

In one embodiment, when the accelerator (eg, the RSA accelerator 18 ) wants to read the key (eg, the key K1 ) to perform a specific operation of modifying the key K1 , the block access signal Block_cpu_read transmitted by the RSA accelerator 18 includes a The first flag (eg, 1), when the accelerator (eg, the RSA accelerator 18 ) completes a specific operation and restores the key K1, the blocking access signal Block_cpu_read sent by the RSA accelerator 18 includes a second flag (eg, 0).

More specifically, when the first identifier is 1, it means that when the key storage device 20 determines that the processor 30 wants to access the key (eg, the key K1 ), the core 24 of the key storage device 20 will block the access The signal Block_cpu_read is sent to the arbiter 22, and the arbiter 22 sends the blocking access signal Block_cpu_read to the processor 30. The blocking access signal Block_cpu_read including the first identifier is used to block the processor 30 from accessing the key (for example, the key K1); when the second identifier is 0, it means that when the key storage device 20 determines that the processor 30 wants to access the key (eg, the key K1), the core 24 of the key storage device 20 will block the access signal Block_cpu_read The arbiter 22 transmits the blocking access signal Block_cpu_read to the processor 30. The blocking access signal Block_cpu_read including the second identifier does not block the processor 30 from accessing the key (eg, the key K1).

In one embodiment, as shown in FIG. 1B , the RSA accelerator 18 can transmit a request access signal Read_K1 at any time. The request access signal Read_K1 indicates that the RSA accelerator 18 wants to access the read key K1 and the key storage The device 20 returns an access permission signal Read_Ok to the RSA accelerator 18 , and the access permission signal Read_Ok represents the subsequent transfer of the key K1 to the RSA accelerator 18 .

In one embodiment, as shown in FIG. 1B , the processor 30 is used to access at least one of the plurality of keys K1 ˜Kn in the key storage device 20 (for example, the key K1 ), when the corresponding A current key number signal (eg, Block_key_num==K1 ) of at least one of the keys K1 to Kn to be accessed by the processor 30 (eg, the key K1 ) and a signal corresponding to the key K1 When the first key number signal (for example, Block_key_num==K1) is the same, and the key storage device 20 has previously received the block access signal Block_cpu_read corresponding to the key K1 including a first identifier (for example, 1), it means The accelerator (for example, the RSA accelerator 18) has sent the modified obfuscated key K1', the core 24 of the key storage device 20 sends an access failure signal Read_Fail to the arbiter 22, and the arbiter 22 sends the access failure signal Read_Fail to the processor 30 , so that the processor 30 cannot access the key K1 , so as to prevent the processor 30 from fetching the confusing key K1 ′ by mistake, resulting in an operation error of the processor 30 .

In one embodiment, when a current key number signal (eg Block_key_num==K1 ) corresponding to at least one of the keys (eg, key K1 ) to be accessed by the processor 30 corresponds to The first key number signal (for example, Block_key_num==K1) of the key K1 is the same, and the key storage device 20 has previously received the block access signal Block_cpu_read corresponding to the key K1 including the second identifier (for example, 0). ), it means that the accelerator (for example, the RSA accelerator 18) has changed the modified obfuscated key K1' back to the original key K1 (for example, the RSA accelerator 18 has completed the operation that requires the obfuscated key K1'), which will not affect In the subsequent operations of the processor 30, the core 24 of the key storage device 20 transmits the access permission signal Read_Ok to the arbiter 22, and the arbiter 22 transmits the access permission signal Read_Ok to the processor 30. The access permission signal Read_Ok represents The processor 20 is allowed to access the key K1.

Referring to FIG. 2 , in step 210 , a first key is stored by a first key storage in a key storage device 20 . In step 220, the key storage device 20 determines the first key storage corresponding to at least one specific instruction, and a first accelerator determines whether to rewrite the first key in the first key storage, so as to perform the operation. Modifying a specific operation of the first key; if the first accelerator determines that the first key in the first key storage is to be rewritten, it transmits at least one specific instruction to the key storage device 20, and proceeds to step 230; When an accelerator determines that it is not necessary to rewrite the first key in the first key storage, the process proceeds to step 235 . In step 235, a read request is sent by the processor 30 or the first accelerator for requesting to read the first key. In step 240 , an access permission signal is returned by the key storage device 20 . In step 230, the key storage device 20 determines whether the read request comes from the first accelerator that allows access to the first key. In this step, the key storage device 20 can also determine that the read request comes from the processor 30. or any accelerator; if the key storage device 20 determines that the read request is from the processor 30, then go to step 250; if the key storage device 20 determines that the read request is from the first accelerator that allows access to the first key, then go to step 250 240. In step 250 , an access failure signal is returned by the key storage device 20 .

With the key storage system and key storage method described in this case, when the accelerator is about to modify the key, the accelerator transmits a specific instruction to the key storage device, and the specific instruction is used to instruct the key storage device to block the processor. Access to the key, thereby avoiding the possibility of the processor reading the modified key, resulting in erroneous operations.

Although this case has been disclosed above with examples, it is not intended to limit this case. Anyone who is familiar with this technique can make various changes and modifications without departing from the spirit and scope of this case. Therefore, the scope of protection in this case should be regarded as The scope of the attached patent application shall prevail.

100, 150: Key storage system 10:Key encryption and decryption accelerator 20:Key storage device 30: Processor S1~Sn: key storage K1~Kn: key 22: Arbiter 24: Core Block_cpu_read: block access signal Block_key_num: key number signal 200:Key storage method 210~250: Steps Read_Fail: access failure signal Read_K1: request access signal Read_Ok: allow access to the signal

FIG. 1A is a block diagram illustrating a key storage system according to an embodiment of the present invention. FIG. 1B is a block diagram illustrating a key storage system according to an embodiment of the present invention. FIG. 2 is a flowchart illustrating a method for storing a key according to an embodiment of the present invention.

200:Key storage method

210~250: Steps

Claims (9)

A key storage system, comprising: a key encryption and decryption accelerator, including: a first accelerator for sending at least one specific instruction; and a key storage device, including: a first key storage for storing a first key; an arbiter for receiving and determining a sender of the at least one specific command; a core for determining that the at least one specific command corresponds to the first key storage; and a processor ; wherein, when the first accelerator wants to read the first key to perform a specific operation of modifying the first key, the first accelerator transmits the at least one specific instruction to the arbiter, the at least one specific instruction including a blocking access signal and a first key number signal corresponding to the first key; wherein the processor is used to access at least one of a plurality of keys in the key storage device; wherein , when a current key number signal of at least one of the keys to be accessed by the processor is the same as the first key number signal corresponding to the first key, and the key storage device When the blocking access signal and the key number signal corresponding to the first key have been received in advance, the processor receives an access failure signal. The key storage system as described in claim 1, wherein the arbiter determines that the sender of the specific command is the first accelerator. The key storage system as described in item 1 of the scope of the application, wherein when When the first accelerator wants to read the first key to perform the specific operation of modifying the first key, the blocking access signal transmitted by the first accelerator includes a first identifier. When the first accelerator completes the The blocking access signal transmitted by the first accelerator includes a second identifier when the first key is specifically calculated and recovered. The key storage system as described in claim 3, wherein the first identifier is 1, indicating that when the key storage device determines that the processor wants to access the first key, the key storage device has The core transmits the blocking access signal to the arbiter, the arbiter transmits the blocking access signal to the processor, and the blocking access signal including the first identifier is used to block the processor from accessing the first a key; wherein the second identifier is 0, indicating that when the key storage device determines that the processor wants to access the first key, the core of the key storage device transmits the blocking access signal to the an arbiter that transmits the blocking access signal to the processor, and the blocking access signal including the second identification does not block the processor from accessing the first key. The key storage system according to item 3 of the scope of the application, further comprising: wherein, when the current key number signal corresponding to at least one of the keys to be accessed by the processor is associated with a signal corresponding to When the first key number signal of the first key is the same, and the key storage device has previously received that the blocking access signal corresponding to the first key includes a first identifier, the key storage device The core of the arbiter transmits the access failure signal to the arbiter, and the arbiter transmits the access failure signal to the processor so that the processor cannot access the first key. The key storage system according to item 3 of the scope of the application, further comprising: wherein the current key number signal corresponding to at least one of the keys to be accessed by the processor corresponds to The first key number signal of the first key is the same, and the key storage device has previously received the block storage corresponding to the first key When the fetch signal contains the second identifier, the core of the key storage sends an access-allowed signal to the arbiter, and the arbiter sends the access-allowed signal to the processor, the access-allowed signal representing the The processor is allowed to access the first key. The key storage system as described in claim 1, wherein the key encryption/decryption accelerator further comprises a second accelerator, and the second accelerator cannot access the first key stored in the first key storage key. The key storage system of claim 1, wherein the key storage device further comprises a second key storage for storing a second key. A key storage method, comprising: storing a first key by a first key storage in a key storage device; sending at least one specific instruction by a key encryption and decryption accelerator; using the key The storage device determines the first key storage corresponding to the at least one specific instruction; and is used by a processor to access at least one of a plurality of keys in the key storage device; wherein, when the When the key encryption/decryption accelerator wants to read the first key to perform a specific operation of modifying the first key, the first accelerator sends the at least one specific instruction to the key storage device, the at least one specific instruction including a blocking access signal and a first key number signal corresponding to the first key; wherein, when the processor wants to access at least one of the keys a current key number signal When the first key number signal corresponding to the first key is the same, and the key storage device has previously received the blocking access signal and the key number signal corresponding to the first key, the The processor receives an access failure signal.

Images