TWI774434B - Transmission control system of multi-media signal, transmission control circuit and receiving control circuit - Google Patents

Abstract

A transmission control system of multi-media signal including a transmission control circuit and a receiving circuit is provided. The transmission control circuit is configured to pack a control signal with one or more of multiple multi-media signals to form multiple first mixing-data packets in an active video period of an image frame, and configured to pack the control signal with other one or more of the multiple multi-media signals to form multiple second mixing-data packets in a vertical front porch and a vertical back porch of the image frame. The receiving circuit is coupled with the transmission circuit. The receiving circuit is configured to receive the multiple first mixing-data packets in the active video period, and configured to receive the multiple second mixing-data packets in the vertical front porch and the vertical back porch. The receiving circuit is configured to unpack the multiple first mixing-data packets and the multiple second mixing-data packets, so as to provide the control signal and the multiple multi-media signals to a display module.

Description

Multimedia signal transmission control system, transmission control circuit and reception control circuit

The present disclosure relates to a multimedia signal transmission control system and a transmission control circuit and a reception control circuit thereof, in particular to a multimedia signal transmission control system for simplifying a signal transmission interface, and a transmission control circuit and a reception control circuit thereof.

The display includes a control module and a display module. The control module is used for decoding image data and adjusting its resolution, and is also used for transmitting various control signals to the display module to control the display module to provide corresponding images. Generally speaking, the components of the control module are arranged on the printed circuit board, and the components of the display module are mostly realized on the glass substrate. If the control module and the display module are packaged into the same device, a thicker casing is required to accommodate the two different substrates. Therefore, it has become a current design trend to separate the control module and the display module from each other, so that the display module, which occupies most of the volume of the display, can be thin and light like a wallpaper. Traditionally, the control module and the display module transmit data through various transmission interfaces, such as serial peripheral interface (SPI) and built-in integrated circuit (I2C) bus, etc. These complicated transmission interfaces are only suitable for short-distance transmission. In addition, different transmission lines are required, so it is not suitable for the design in which the control module and the display module are separated from each other.

The present disclosure provides a multimedia signal transmission control system, which includes a transmission control circuit and a reception control circuit. The transmission control circuit is used for encapsulating one or more of the control signal and the plurality of multimedia signals into a plurality of first mixed data packets during the active video period of the image frame, and is used for the vertical leading edge of the image frame ( The vertical front porch and the vertical back porch encapsulate the control signal and one or more of the plurality of multimedia signals into a plurality of second mixed data packets. The receiving control circuit is coupled to the transmitting control circuit, and is used for receiving a plurality of first mixed data packets during the active video period, and for receiving a plurality of second mixed data packets at the vertical leading edge and the vertical trailing edge. The receiving control circuit is used for unpacking a plurality of first mixed data packets and a plurality of second mixed data packets to provide control signals and a plurality of multimedia signals to the display module.

The present disclosure provides a transmission control circuit, which is suitable for a multimedia signal transmission control system. The transmission control circuit is used for encapsulating one or more of the control signal and the plurality of multimedia signals into a plurality of first mixed data packets during the active video period of the image frame, and for sending the control signal at the vertical leading edge and the vertical trailing edge of the image frame. The signal and one or more of the plurality of multimedia signals are packaged into a plurality of second mixed data packets. When the transmit control circuit is coupled to the receive control circuit, the receive control circuit receives a plurality of first mixed data packets during the active video period, and receives a plurality of second mixed data packets at the vertical leading edge and the vertical trailing edge, and the receive control circuit deciphers the Packing a plurality of first mixed data packets and a plurality of second mixed data packets, so that the transmitting control circuit provides control signals and a plurality of multimedia signals to the display module through the receiving control circuit.

The present disclosure provides a receiving control circuit, which is suitable for a multimedia signal transmission control system. The receiving control circuit is used for being coupled to the transmitting control circuit, and the transmitting control circuit is used to encapsulate a control signal and one or more of the plurality of multimedia signals into a plurality of first mixed data packets during the active video period of the image frame, and use the One or more of the control signal and the plurality of multimedia signals are packaged into a plurality of second mixed data packets at the vertical leading edge and the vertical trailing edge of the image frame. The receiving control circuit is used for receiving a plurality of first mixed data packets during the active video period, and is used for receiving a plurality of second mixed data packets at the vertical leading edge and the vertical trailing edge, wherein the receiving control circuit is used for unpacking the plurality of first mixed data packets The data packets and a plurality of second mixed data packets are used to provide control signals and a plurality of multimedia signals to a display module.

The embodiments of the present disclosure will be described below in conjunction with the relevant drawings. In the drawings, the same reference numbers refer to the same or similar elements or method flows.

FIG. 1 is a simplified functional block diagram of a multimedia playback system 100 according to an embodiment of the present disclosure. The multimedia playback system 100 includes a control module 110 , a multimedia signal transmission control system 120 and a display module 130 , wherein the multimedia signal transmission control system 120 is coupled between the control module 110 and the display module 130 . The control module 110 is used for receiving multimedia signals through video streaming or from a graphics processing unit (GPU), converting the multimedia signals into a data format suitable for the display module 130 to play, and then transmitting the converted multimedia signals through the multimedia signals The control system 120 is provided to the display module 130 . The control module 110 is also used for transmitting additional control signals to the display module 130 through the multimedia signal transmission control system 120 . For example, in some embodiments, the display module 130 includes the pixel matrix 710 and the backlight module 730 in FIG. 7 , and the control module 110 transmits the backlight control signal and the PWM signal through the multimedia signal transmission control system 120 to the display module 130 to control its backlight brightness.

In this embodiment, the multimedia signal transmission control system 120 transmits the multimedia signal and the control signal from the control module 110 to the display module 130 through a single transmission interface (for example, a high-definition multimedia interface, HDMI for short), so there are Helps reduce the number of transmission lines, but this disclosure is not limited thereto. In this embodiment, a part of the multimedia signal transmission control system 120 and the control module 110 are integrated into a single device, and another part of the multimedia signal transmission control system 120 and the display module are integrated into a single device, but the present disclosure The file is not limited to this. In some embodiments, the multimedia signal transmission control system 120 and the transmission line are integrated into a single device, which is coupled to the control module 110 and the display module 130 through pluggable connectors.

In some embodiments, the control module 110 may be implemented by a combination of one or more of a scaler IC, an image decoder, an analog-to-digital converter, a microprocessor, and a memory circuit. In some embodiments, the control module 110 may be the video stream source or the graphics processor itself, or a module integrated with the video stream source or the graphics processor, but not limited thereto.

FIG. 2 is a simplified functional block diagram of the multimedia signal transmission control system 120 according to an embodiment of the present disclosure. The multimedia signal transmission control system 120 may include a transmission control circuit 20 and a reception control circuit 30 coupled to each other. The transmit control circuit 20 is coupled to the control module 110 or, in some embodiments, integrated with the control module 110 into a single device. The receiving control circuit 30 is coupled to the display module 130 or integrated with the display module 130 into a single device in some embodiments. In some embodiments, the transmit control circuit 20 and the receive control circuit 30 are coupled to each other through a transmission line.

The transmit control circuit 20 receives the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DEN and the pixel clock signal CLK. In addition, the transmission control circuit 20 includes a signal distribution circuit 210 and a transmission interface circuit 220 . The signal distribution circuit 210 is used for receiving the control signal CT from the control module 110 . In some embodiments, the control signal CT includes, but is not limited to, a backlight control signal, a pulse width modulation signal, a panel calibration signal, and the like, wherein the panel calibration signal can be used to correct uneven brightness of the panel. In other embodiments, the control signal CT is different from the video signal VS, the audio signal AS and the auxiliary data signal AUX. The transmitting interface circuit 220 is used for receiving multimedia signals from the control module 110, such as but not limited to the video signal VS, the audio signal AS and the auxiliary data signal AUX. In some embodiments, the auxiliary data signal AUX is used to convey the specification of the multimedia signal or the information needed to reconstruct the audio clock. In other embodiments, the video signal VS is used to specify the gray scale of the pixels in the pixel matrix 710 of FIG. 7 .

FIG. 3 is a schematic diagram of simplified waveforms of a plurality of signals processed by the multimedia signal transmission control system 120 . The vertical synchronization signal Vsync is used to control the time length of each image frame of the display module 130 . For example, the interval between two adjacent pulses of the vertical synchronization signal Vsync is the time length of one image frame. The horizontal synchronization signal Hsync and the data enable signal DEN are used to control the display module 130 to update a corresponding row of pixels. The pixel clock signal CLK is used to further control the display module 130 to update a corresponding pixel in a row.

In an image frame, the period between the pulse wave of the vertical synchronization signal Vsync and the first pulse wave of the data enable signal DEN is called "vertical back porch" (vertical back porch). In addition, the period between the last pulse of the data enable signal DEN in one image frame and the pulse of the vertical synchronization signal Vsync of the next image frame is called "vertical front porch" (vertical front porch). The multimedia signal transmission control system 120 transmits the information carried by the audio signal AS or the auxiliary data signal AUX in the vertical back edge VBP and the vertical front edge VFP. The period between the vertical trailing edge VBP and the vertical leading edge VFP is called "active video period AVP" (active video period). The multimedia signal transmission control system 120 transmits the information carried by the video signal VS through the AVP during the active video period. It is worth mentioning that, in order to obtain sufficient continuous bandwidth under a single communication protocol, the multimedia signal transmission control system 120 disperses the information carried by the control signal CT in the vertical trailing edge VBP, the vertical leading edge VFP and the active video period AVP transmission. .

Please refer to FIG. 2 and FIG. 3 at the same time, in the vertical trailing edge VBP and the vertical leading edge VFP, the signal distribution circuit 210 provides the control signal CT to the first data packetizer 222 of the transmitting interface circuit 220 through its first output terminal . The first data packer 222 is coupled to the first output end of the signal distribution circuit 210 for receiving the video signal VS and for packaging the video signal VS and the control signal CT into a plurality of first mixed data packets MPa.

On the other hand, during the active video period AVP, the signal distribution circuit 210 provides the control signal CT to the second data packetizer 224 of the transmit interface circuit 220 through its second output terminal. The second data packer 224 is coupled to the second output end of the signal distribution circuit 210, and is used for receiving the audio signal AS and the auxiliary data signal AUX, and for packing the audio signal AS or the auxiliary data signal AUX and the control signal CT into multiple A second mixed data packet MPb.

The first data packetizer 222 and the second data packetizer 224 respectively provide the first mixed data packet MPa and the second mixed data packet MPb to the transmitting circuit 226 of the transmitting interface circuit 220 . The transmitting circuit 226 has an encoding function for encoding the first mixed data packet MPa, the second mixed data packet MPb, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DEN and the pixel clock signal CLK. The transmitting circuit 226 transmits the encoded information to the receiving control circuit 30 through an appropriate data transmission technology. In some embodiments, in order to increase the transmission distance of the multimedia signal transmission control system 120 , the transmitter circuit 226 uses a transition-minimized differential signaling (TMDS) technique for data communication with the receiver control circuit 30 .

FIG. 4 is a signal transmission timing diagram of the multimedia signal transmission control system 120 . As shown in FIG. 4, the vertical trailing edge VBP and the vertical leading edge VFP include a plurality of control periods (marked as blank blocks) 410 and a plurality of data island periods (marked as cross-mesh blocks) ) 420. The transmitting circuit 226 transmits the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync and the preamble to the receiving control circuit 30 in the control period 410 . The transmitting circuit 226 also transmits the second mixed data packet MPb to the receiving control circuit 30 in the data island period 420, ie, transmits the mixed information of the control signal CT, the audio signal AS and/or the auxiliary data signal AUX. The active video period AVP includes multiple periods of video data (labeled as dot blocks) 430 . The transmitting circuit 226 transmits the first mixed data packet MPa to the receiving control circuit 30 in the video data period 430, ie, transmits the mixed information of the control signal CT and the video signal VS.

In a word, the transmit control circuit 20 is used for encapsulating the control signal CT and one or more of the plurality of multimedia signals (eg, the video signal VS) from the control module 110 as the first mixed data during the active video period AVP of the image frame. Pack the MPa and deliver it. Further, as shown in FIG. 3 , the transmit control circuit 20 transmits the first mixed data packet MPa when the data enable signal DEN provides a pulse wave. The transmission control circuit 20 is also used for connecting the control signal CT and another or more of the plurality of multimedia signals (such as the audio signal AS or auxiliary data) from the control module 110 at the vertical trailing edge VBP and the vertical leading edge VFP of the image frame. The signal AUX) is packaged as a second mixed data packet MPb and transmitted.

In some embodiments, the transmit control circuit 20 may encapsulate the first mixed data packet MPa and the second mixed data packet MPb according to a user-defined packet format. The aforementioned custom packet format refers to a user-defined header for the first mixed data packet MPa and the second mixed data packet MPb. The user-defined header is different from the headers of the pre-formatted packets (eg, video packets, audio packets and auxiliary data packets) defined in the specifications of the multimedia signal transmission control system 120 .

Please refer to FIG. 2 again, the receiving control circuit 30 includes a receiving interface circuit 310 and a signal combining circuit 320 . The receiving interface circuit 310 includes a receiving circuit 312 , a first data depacketizer 314 and a second data depacketizer 316 . The receiving circuit 312 is used for data communication with the transmitting circuit 226, and the receiving circuit 312 has a decoding function (for example: a decoding function corresponding to the encoding format of the transmitting circuit 226), which is used for decoding and encapsulating the received first mixed data MPa and The second mixed data packet MPb is provided to the first data depacketizer 314 and the second data depacketizer 316, respectively. The first data depacketizer 314 is used for depacketizing the first mixed data packet MPa, so as to regenerate the video signal VS at the receiving end, and generate the first input signal INa including part of the information of the control signal CT. The second data depacketizer 316 is used for depacketizing the second mixed data packet MPb to regenerate the audio signal AS and/or the auxiliary data signal AUX at the receiving end, and to generate a second input signal including another part of the control signal CT INb. In addition, the receiving circuit 312 is also used to restore the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DEN and the pixel clock signal CLK through decoding at the receiving end, and provide these signals to the display module 130 .

Please refer to FIGS. 2 , 3 and 4 at the same time, the signal combining circuit 320 is used for receiving the first input signal INa and the second input signal INb through its first input terminal and the second input terminal, respectively. During the active video period AVP, the signal combining circuit 320 provides the first input signal INa as the regenerated control signal CT to the display module 130 . Further, the receiving control circuit 30 generates the control signal CT according to the information in the first mixed data packet MPa when the data enable signal DEN provides the pulse wave. At the vertical back edge VBP and the vertical front edge VFP, the signal combining circuit 320 provides the second input signal INb to the display module 130 as the regenerated control signal CT.

FIG. 5 is a simplified functional block diagram of the signal distribution circuit 210 according to an embodiment of the present disclosure. The signal distribution circuit 210 includes a demultiplexer 510 and a transmit count circuit 520 . The demultiplexer 510 is used for receiving the control signal CT, and is coupled to the first output terminal and the second output terminal of the signal distribution circuit 210 . The transmit counting circuit 520 is used to receive one or more of the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DEN and the pixel clock signal CLK, for example, to receive the vertical synchronization signal Vsync and the data enable signal DEN, so as to It is determined whether the emission control circuit 20 is operating in the vertical trailing edge VBP, the vertical leading edge VFP or the active video period AVP. The transmit counting circuit 520 is used to control the demultiplexer 510 to distribute the control signal CT to one of the first output terminal and the second output terminal of the signal distribution circuit 210 . That is, during the active video period AVP, the transmit count circuit 520 controls the demultiplexer 510 to distribute the control signal CT to the first output terminal, and during the vertical back edge VBP and the vertical front edge VFP, the transmit count circuit 520 controls the demultiplexer. The processor 510 distributes the control signal CT to the second output terminal.

FIG. 6 is a simplified functional block diagram of the signal combining circuit 320 according to an embodiment of the present disclosure. The signal combining circuit 320 includes a multiplexer 610 and a receiving counting circuit 620 . The multiplexer 610 is coupled to the first input terminal and the second input terminal of the signal combining circuit 320, and is used for receiving the first input signal INa and the second input signal INb. The receiving counting circuit 620 is used for receiving one or more of the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DEN and the pixel clock signal CLK, for example, the vertical synchronization signal Vsync and the data enable signal DEN are received, so as to It is determined whether the receiving control circuit 30 is operating in the vertical back edge VBP, the vertical front edge VFP or the active video period AVP. The receiving counting circuit 620 is used to control the multiplexer 610 to use one of the first input signal INa and the second input signal INb as the control signal CT provided to the display module 130 . That is, during the active video period AVP, the receiving counting circuit 620 will control the multiplexer 610 to use the first input signal INa as the control signal CT, and during the vertical trailing edge VBP and the vertical leading edge VFP, the receiving counting circuit 620 will control the multiplexing The controller 610 uses the second input signal INb as the control signal CT.

FIG. 7 is a simplified functional block diagram of the display module 130 according to an embodiment of the present disclosure. The display module 130 includes a pixel matrix 710 , a backlight controller 720 , a backlight module 730 , a timing controller 740 , a scan driver 750 , a data driver 760 , a plurality of gate lines GL and a plurality of source lines SL. The backlight controller 720 is used for receiving the control signal CT and operating the backlight module 730 according to the control signal CT. The gate line GL and the source line SL are respectively coupled to the scan driver 750 and the data driver 760, and the pixels in the pixel matrix 710 correspond to the intersections of the gate line GL and the source line SL, respectively. The timing controller 740 is used for receiving the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DEN, the pixel clock signal CLK and the video signal VS. The timing controller 740 is used for generating a plurality of operating clocks according to the received signals to drive the scan driver 750 and the data driver 760, and to generate display data to the data driver 760 to determine the gray scale of the pixels. The operations of the scan driver 750 and the data driver 760 are well known to those skilled in the art, and will not be repeated here.

In some embodiments, the display module 130 includes a speaker circuit (not shown). The speaker circuit is used to receive the audio signal AS and auxiliary data signal AUX as shown in Figure 2. The speaker circuit can reconstruct the sound clock according to the auxiliary data signal AUX to play the sound information in the audio signal AS. In other embodiments, the display module 130 does not include a speaker circuit, so the display module 130 may not receive the audio signal AS and the auxiliary data signal AUX.

Please refer to FIGS. 3 , 4 and 7 at the same time. In some embodiments, the pixel matrix 710 shown in FIG. 7 has a resolution of M×N, that is, each gate line GL is coupled to M pixels, and each source line SL is coupled to N pixels, where M and N are positive integers. For the convenience of description, the number of pixels coupled to the gate line GL is hereinafter referred to as the lateral resolution of the display module 130 . In some embodiments, the width of one pulse of the data enable signal DEN corresponds to the lateral resolution of the display module 130 , that is, it is approximately equal to the width of M pulses of the pixel clock signal CLK.

In the embodiments shown in FIGS. 3 and 4 , the width of one pulse of the data enable signal DEN is greater than the lateral resolution of the display module 130 shown in FIG. 7 . The width of one pulse of the data enable signal DEN is approximately equal to the width of K pulses of the pixel clock signal CLK, where K is a positive number and K is greater than M. The user can define the value of K so as to extend the time for transmitting row data by a predetermined time length PP as shown in FIG. 4 , thereby increasing the continuous bandwidth of AVP during active video.

To sum up, the multimedia signal transmission control system 120 can transmit a variety of different signals through a single transmission interface, which helps to simplify the types of connectors of the multimedia playback system 100 and reduce the number of transmission lines, so that the multimedia playback system 100 can easily achieve a thin and light design .

In addition, the multimedia signal transmission control system 120 mixes the information of the control signal CT with the information of other signals, so that the information of the control signal CT can be transmitted in the whole image frame. In this way, the multimedia signal transmission control system 120 can provide sufficient continuous bandwidth even if only a single transmission interface is used for data communication.

Certain terms are used in the specification and claims to refer to particular elements. However, those of ordinary skill in the art should understand that the same elements may be referred to by different nouns. The description and the scope of the patent application do not use the difference in name as a way of distinguishing elements, but use the difference in function of the elements as a basis for distinguishing. The "comprising" mentioned in the description and the scope of the patent application is an open-ended term, so it should be interpreted as "including but not limited to". In addition, "coupled" herein includes any direct and indirect means of connection. Therefore, if it is described in the text that the first element is coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection or signal connection such as wireless transmission or optical transmission, or through other elements or connections. The means are indirectly electrically or signally connected to the second element.

As used herein, the description "and/or" includes any combination of one or more of the listed items. In addition, unless otherwise specified in the specification, any term in the singular also includes the meaning in the plural.

The above are only preferred embodiments of the present disclosure, and all equivalent changes and modifications made according to the claims of the present disclosure shall fall within the scope of the present disclosure.

100: Multimedia playback system 110: Control Module 120: Multimedia Signal Transmission Control System 130: Display Module 20: launch control circuit 30: Receive control circuit 210: Signal distribution circuit 220: launch interface circuit 222: First Data Packer 224: Second Data Packer 226: transmitter circuit 310: receiving interface circuit 312: Receiver circuit 314: First Data Unpacker 316: Second Data Unpacker 320: Signal Combination Circuit Vsync: vertical sync signal Hsync: horizontal sync signal DEN: data enable signal CLK: pixel clock signal VS: Video signal AS: audio signal AUX: auxiliary data signal CT: control signal MPa: first mixed data packet MPb: Second Mixed Data Packet INa: The first input signal INb: The second input signal VBP: Vertical Back Edge VFP: Vertical Frontier AVP: During Active Video PP: Predetermined length of time 410: Control cycle 420: Data Island Cycle 430: Video data cycle 510: Demultiplexer 520: launch counting circuit 610: Multiplexer 620: Receive counting circuit 710: pixel matrix 720: Backlight Controller 730: Backlight Module 740: Timing Controller 750: Scan Drive 760: Data Drive GL: gate line SL: source line

FIG. 1 is a simplified functional block diagram of a multimedia playback system according to an embodiment of the present disclosure. FIG. 2 is a simplified functional block diagram of a multimedia signal transmission control system according to an embodiment of the present disclosure. FIG. 3 is a schematic diagram of simplified waveforms of multiple signals processed by the multimedia signal transmission control system. FIG. 4 is a signal transmission timing diagram of the multimedia signal transmission control system. FIG. 5 is a simplified functional block diagram of a signal distribution circuit according to an embodiment of the present disclosure. FIG. 6 is a simplified functional block diagram of a signal combining circuit according to an embodiment of the present disclosure. FIG. 7 is a simplified functional block diagram of a display module according to an embodiment of the present disclosure.

20: launch control circuit

30: Receive control circuit

120: Multimedia Signal Transmission Control System

210: Signal distribution circuit

220: launch interface circuit

222: First Data Packer

224: Second Data Packer

226: transmitter circuit

310: receiving interface circuit

312: Receiver circuit

314: First Data Unpacker

316: Second Data Unpacker

320: Signal Combination Circuit

Vsync: vertical sync signal

Hsync: horizontal sync signal

DEN: data enable signal

CLK: pixel clock signal

VS: Video signal

AS: audio signal

AUX: auxiliary data signal

CT: control signal

MPa: first mixed data packet

MPb: Second Mixed Data Packet

INa: The first input signal

INb: The second input signal

Claims (7)

A multimedia signal transmission control system, comprising: a transmission control circuit for encapsulating a control signal and one or more of a plurality of multimedia signals into a plurality of first video during an active video period of an image frame a mixed data packet for encapsulating the control signal and the other or more of the plurality of multimedia signals into a plurality of multi-media signals at a vertical front porch and a vertical back porch of the image frame a second mixed data packet, and includes: a signal distribution circuit including a first output terminal and a second output terminal for receiving the control signal, wherein during the active video period, the signal distribution circuit the control signal Distributed to the first output terminal to output the control signal through the first output terminal, at the vertical leading edge and the vertical trailing edge, the signal distribution circuit distributes the control signal to the second output terminal to pass through the second output terminal a terminal to output the control signal; and a transmitting interface circuit coupled to the first output terminal, the second output terminal and the receiving control circuit, wherein the transmitting interface circuit is used for receiving the signal from the first output terminal generating the plurality of first mixed data packets with the one or more of the plurality of multimedia signals for use in accordance with the signal received from the second output and the other or more of the plurality of multimedia signals generating the plurality of second mixed data packets; and a receiving control circuit, coupled to the transmitting control circuit, and used for The active video period receives the plurality of first mixed data packets and is used for receiving the plurality of second mixed data packets at the vertical leading edge and the vertical trailing edge, wherein the receiving control circuit is used for unpacking the plurality of first mixed data packets The mixed data packets and the plurality of second mixed data packets are used to provide the control signal and the plurality of multimedia signals to a display module. The multimedia signal transmission control system as claimed in claim 1, wherein the transmission control circuit is configured to provide a pixel clock signal to the display module through the reception control circuit, and each pulse wave of the pixel clock signal used to control the display module to update a corresponding pixel of the display module; wherein, the transmission control circuit is used for receiving a data enable signal, when the data enable signal provides a pulse, the transmission control circuit transmits The plurality of first mixed data packets, and the pulse wave of the data enable signal is used to control the display module to update a corresponding row of pixels of the display module; wherein, the width of the pulse wave of the data enable signal Corresponding to the width of K pulses of the pixel clock signal, K is a positive number and K is greater than a horizontal resolution of a pixel matrix of the display module. The multimedia signal transmission control system of claim 1, wherein the receiving control circuit comprises: a signal combining circuit including a first input terminal and a second input terminal; and a receiving interface circuit coupled to the transmitting a control circuit, the first input terminal and the second input terminal for unpacking the plurality of first mixed data packets and the plurality of second mixed data packets to generate a first input signal and a second input signal respectively, and for providing the first input signal and the second input signal to the first input terminal and the second input terminal respectively an input terminal; wherein during the active video period, the signal combining circuit uses the first input signal as the control signal provided to the display module, and during the vertical leading edge and the vertical trailing edge, the signal combining circuit provides the first input signal to the first input terminal. Two input signals are used as the control signal provided to the display module. A transmission control circuit is suitable for a multimedia signal transmission control system, wherein the transmission control circuit is used to package a control signal and one or more of a plurality of multimedia signals into a plurality of a first mixed data packet for encapsulating the control signal and one or more of the plurality of multimedia signals into a plurality of second mixed data packets at a vertical leading edge and a vertical trailing edge of the image frame, wherein the The transmission control circuit includes: a signal distribution circuit including a first output terminal and a second output terminal for receiving the control signal, wherein during the active video period, the signal distribution circuit distributes the control signal to the first output terminal The output terminal is used to output the control signal through the first output terminal, and at the vertical leading edge and the vertical trailing edge, the signal distribution circuit distributes the control signal to the second output terminal to output the control signal through the second output terminal ; and a transmitting interface circuit coupled to the first output end, the second output end and the receiving control circuit, wherein the transmitting interface circuit is used to communicate with the plurality of multimedia based on the signal received from the first output end the one in the signal or generating the plurality of first mixed data packets and generating the plurality of second mixed data packets according to the signal received from the second output terminal and the other one or more of the plurality of multimedia signals, Wherein, when the transmit control circuit is coupled to a receive control circuit, the receive control circuit receives the plurality of first mixed data packets during the active video period, and receives the plurality of first mixed data packets at the vertical leading edge and the vertical trailing edge Two mixed data packets, and the receiving control circuit unpacks the plurality of first mixed data packets and the plurality of second mixed data packets, so that the transmission control circuit provides the control signal and the plurality of multimedia through the receiving control circuit signal to a display module. The transmit control circuit of claim 4, wherein the transmit control circuit is configured to provide a pixel clock signal to the display module through the receive control circuit, and each pulse of the pixel clock signal is used for Controlling the display module to update a corresponding pixel of the display module; wherein, the transmission control circuit is used for receiving a data enabling signal, and when the data enabling signal provides a pulse, the transmission control circuit transmits the multiple a first mixed data packet, and the pulse wave of the data enable signal is used to control the display module to update a corresponding row of pixels of the display module; wherein, the width of the pulse wave of the data enable signal corresponds to The widths of K pulses of the pixel clock signal, K is a positive number and K is greater than a horizontal resolution of a pixel matrix of the display module. A receiving control circuit suitable for a multimedia signal transmission A transmission control system, wherein the reception control circuit is used for coupling to a transmission control circuit, and the transmission control circuit is used for connecting a control signal and one or more of a plurality of multimedia signals during an active video of an image frame encapsulated into a plurality of first mixed data packets for encapsulating the control signal and one or more of the plurality of multimedia signals into a plurality of second mixed data at a vertical leading edge and a vertical trailing edge of the image frame packets; wherein the receiving control circuit is used for receiving the plurality of first mixed data packets during the active video period, and for receiving the plurality of second mixed data packets at the vertical leading edge and the vertical trailing edge, wherein the receiving The control circuit is used for unpacking the plurality of first mixed data packets and the plurality of second mixed data packets to provide the control signal and the plurality of multimedia signals to a display module, wherein the receiving control circuit includes: a signal combination circuit, comprising a first input terminal and a second input terminal; and a receiving interface circuit, coupled to the transmission control circuit, the first input terminal and the second input terminal, for unpacking the plurality of first input terminals Mixing the data packets and the plurality of second mixing data packets to generate a first input signal and a second input signal respectively, and for providing the first input signal and the second input signal to the first input terminal and the second input signal respectively the second input terminal, wherein during the active video period, the signal combining circuit takes the first input signal as the control signal provided to the display module, and during the vertical leading edge and the vertical trailing edge, the signal combining circuit The second input signal is used as the control signal provided to the display module. The reception control circuit of claim 6, wherein the reception control circuit receives a pixel clock signal from the transmission control circuit, and provides the pixel clock signal to the display module, the pixel clock signal Each pulse of the signal is used to control the display module to update a corresponding pixel of the display module; wherein, the receiving control circuit is used to receive a data enabling signal, when the data enabling signal provides a pulse , the receiving control circuit generates the control signal according to the information in the plurality of first mixed data packets, and each pulse of the data enabling signal is used to control the display module to update a corresponding row of pixels of the display module ; wherein, the width of the pulse wave of the data enable signal corresponds to the width of K pulse waves of the pixel clock signal, K is a positive number and K is greater than a horizontal resolution of a pixel matrix of the display module .

Images