TWI774233B - Signal transmission system and transmission-end encoding apparatus - Google Patents

Abstract

A transmission-end encoding apparatus including a multiplexer and a transmission-end encoder is provided. The multiplexer is configured to receive a first digital signal and a second digital signal and to generate an output. The output of the multiplexer includes multiple M-bit code words of the first digital signal, and also includes multiple M-bit code words of the second digital signal interleaved with the multiple M-bit code words of the first digital signal. The transmission-end encoder is configured to receive the output of the multiplexer, and configured to generate multiple N-bit code words, in which M and N are positive integers but M is different from N. The transmission-end encoder is configured to determine a current N-bit word of the multiple N-bit words according to the output of the multiplexer and a disparity of a previous N-bit word of the multiple N-bit words. The transmission-end encoder is further configured to transmit the multiple N-bit words to a receiving-end decoding apparatus including a receiving-end decoder and a demultiplexer.

Description

Signal transmission system and transmitter encoding device

The present disclosure relates to a signal transmission system and a transmitter encoding device thereof, especially a DC-balanced high-speed signal transmission system and a transmitter encoding device thereof.

Differential signals have excellent resistance to external interference, and have steep rising and falling edges, so they are often used in high-speed data transmission technology. When using a differential signal to continuously transmit a sequence of multiple "1" or multiple "0", because the frequency of the signal decreases, the impedance of the transmission line will increase correspondingly, which may cause signal attenuation and distortion. In order to make the differential signal transmit the sequence of "1" and "0" evenly, that is, to achieve DC balance, many encoding methods have been applied to high-speed data transmission systems, such as 8-bit to 10-bit (8B). /10B) coding method. In this encoding, each 8-bit code word is converted into a 10-bit code word with positive disparity, negative disparity, or no disparity, where positive disparity , Negative Inequality and No Inequality respectively represent the number of "1" in the sequence is more than the number of "0", the number of "1" in the sequence is less than the number of "0" and the number of "1" in the sequence Equal to the number of "0"s. By arranging the order of appearance of the 10-bit codewords with these three inequalities, DC balance can be achieved.

The present disclosure provides a signal transmission system, which includes a transmitting-end encoding device and a receiving-end decoding device. The transmitter encoding apparatus includes a multiplexer and a first transmitter encoder. The multiplexer is used for receiving the first digital signal and the second digital signal and generating an output. The output of the multiplexer includes a plurality of M-bit codewords of the first digital signal, and includes a plurality of M-bit codewords of the second digital signal alternately arranged with the plurality of M-bit codewords of the first digital signal, And M is a positive integer. The first transmitter-side encoder is used for receiving the output of the multiplexer and generating a plurality of N-bit codewords, where N is a positive integer and M is not equal to N. The first transmitter encoder is configured to determine the current N in the plurality of N-bit codewords according to the disparity between the output of the multiplexer and the previous N-bit codeword in the plurality of N-bit codewords Bit code word. The receiving end decoding device is coupled to the transmitting end encoding device, and includes a first receiving end decoder and a demultiplexer. The first receiver decoder is used for decoding a plurality of N-bit codewords to generate a plurality of I-bit codewords. I is a positive integer and I is not equal to N. The demultiplexer is used to alternately distribute multiple 1-bit codewords to the multiple outputs of the demultiplexer.

The present disclosure provides a transmitter encoding apparatus, which includes a multiplexer and a first transmitter encoder. The multiplexer is used for receiving the first digital signal and the second digital signal and generating an output. The output of the multiplexer includes a plurality of M-bit codewords of the first digital signal, and includes a plurality of M-bit codewords of the second digital signal alternately arranged with the plurality of M-bit codewords of the first digital signal, And M is a positive integer. The first transmitter-side encoder is used for receiving the output of the multiplexer and generating a plurality of N-bit codewords, where N is a positive integer and M is not equal to N. The first transmitter encoder is configured to determine the current N-bit code in the plurality of N-bit code words according to the inequality between the output of the multiplexer and the previous N-bit code word in the plurality of N-bit code words Character. The first transmitter-side encoder is used for transmitting a plurality of N-bit codewords to the receiver-side decoding device. The receiver decoding apparatus includes a demultiplexer and a first receiver decoder for decoding the plurality of N-bit codewords.

The present disclosure provides a receiver decoding apparatus, which includes a first receiver decoder and a demultiplexer. The first receiver-side decoder is used for receiving a plurality of N-bit codewords from the transmitter-side encoding device. The transmitter encoding apparatus includes a multiplexer and a first transmitter encoder for generating a plurality of N-bit codewords. The first receiver decoder is used for decoding a plurality of N-bit codewords to generate a plurality of 1-bit codewords. A plurality of N-bit codewords have substantially equal numbers of 0s and 1s, N and 1 being positive integers and N not equal to 1. The demultiplexer is used to alternately distribute multiple 1-bit codewords to the multiple outputs of the demultiplexer.

The advantages of the above-mentioned embodiments are that the requirement for the number of transmission lines is reduced without reducing the data transmission rate.

The embodiments of the present disclosure will be described below in conjunction with the relevant drawings. In the drawings, the same reference numbers refer to the same or similar elements or method flows.

FIG. 1 is a simplified functional block diagram of a signal transmission system 100 according to an embodiment of the present disclosure. The signal transmission system 100 includes a transmitter encoding device 110 , a transmitter physical layer driver 120 , a receiver physical layer driver 130 , a receiver decoding device 140 and a cable 150 . The transmitting-end encoding device 110 is used for receiving the digital signals DAa-DAd transmitted from an external device (not shown, such as a graphics processor or other suitable logic circuits). In some embodiments, the digital signals DAa-DAd include video data, audio data or other control signals (such as but not limited to vertical synchronization signals and backlight control signals). The transmitting-end encoding device 110 is used for encoding the digital signals DAa-DAd into the digital signals DBa-DBb, and providing the digital signals DBa-DBb to the transmitting-end physical layer driver 120 . In some embodiments, the digital signals DBa˜DBb are DC balance signals.

The transmitter physical layer driver 120 , the cable 150 and the receiver physical layer driver 130 are sequentially coupled in series. The transmitter physical layer driver 120 is used for converting the digital signals DBa to DBb into serialized differential signals, and provides the differential signals to the receiver physical layer driver 130 through the cable 150 . That is, although FIG. 1 shows the cable 150 as a dual channel, in some embodiments the cable 150 includes four differential signal lines. The physical layer driver 130 at the receiving end is used to restore the differential signals to the digital signals DBa-DBb, and provide the restored digital signals DBa-DBb to the decoding device 140 at the receiving end. The receiver decoding device 140 is coupled to a video control chip or an audio control chip (not shown). The receiver decoding device 140 is also used for converting the digital signals DBa-DBb into a data format compatible with the video control chip or the audio control chip, so as to generate the digital signals DCa-DCd. In some embodiments, the transmitter PHY driver 120, the cable 150, and the receiver PHY driver 130 comply with or are compatible with one or more communication specifications, such as, but not limited to, Peripheral Component Interconnect Express (PCIe), Serial Advanced Technology Attachment (SATA) or High-Definition Multimedia Interface (HDMI).

The transmitter encoding apparatus 110 includes a multiplexer 112 and a transmitter encoder 114 coupled to each other. The multiplexer 112 is used for receiving the digital signals DAa~DAd. For the convenience of description, in the following embodiments of the present disclosure, the digital signals DAa˜DAd are assumed to each include a plurality of 8-bit code words, but the present disclosure is not limited to this. In some embodiments, the digital signals DAa˜DAd each include a plurality of M-bit codewords, and M is a positive integer. The first output terminal of the multiplexer 112 is used for outputting the 8-bit codewords of the digital signals DAa and DAb, and the multiplexer 112 combines the 8-bit codewords of the digital signal DAa with the 8-bit codewords of the digital signal DAb Alternate arrangement. Similarly, the second output terminal of the multiplexer 112 is used for outputting the 8-bit codewords of the digital signals DAc and DAd, and the multiplexer 112 combines the 8-bit codewords of the digital signal DAc with the 8-bit codewords of the digital signal DAd. The metacode words are arranged alternately.

FIG. 2 is a schematic diagram of the multiplexer 112 alternately arranging codewords of different digital signals. As shown in Fig. 2, in an arbitrary period of time, the digital signal DAa provides the code words "f0", "f2", "f4" and "f6" in sequence, and the digital signal DAb provides the code words "f1", "f1", "f2" and "f6" in sequence. "f3", "f5" and "f7". In the output of the first output terminal of the multiplexer 112, the codeword "f1" is arranged between the codewords "f0" and "f2", and the codeword "f3" is arranged between the codewords "f2" and "f4" ”, and so on. In this disclosure, the value of the codeword is expressed in hexadecimal to simplify the description. For example, the codeword "f0" expressed in hexadecimal is the same as the 8-bit codeword "11110000" expressed in binary. The multiplexer 112 alternately arranges the codewords of the digital signals DAc and DAd in a similar manner, which is not repeated here for brevity.

The transmitter encoder 114 is used for encoding the 8-bit codewords received from the first output terminal and the second output terminal of the multiplexer 112 into 10-bit codewords to obtain the digital signals DBa and DBb, respectively, that is, The transmitter encoder 114 is an 8-bit to 10-bit (8B/10B) encoder, but this disclosure is not limited thereto. In some embodiments, the transmitter encoder 114 is configured to encode the M-bit codeword output by the multiplexer 112 into digital signals DBa and DBb having N-bit codewords, where N is a positive integer and N is not equal to the aforementioned The M.

FIG. 3 is a schematic diagram of the encoding result of the encoder 114 at the transmitting end. As shown in FIG. 3, the transmitter encoder 114 encodes the 8-bit codewords "f0" to "f7" into 10-bit codewords "236", "3b1", "232", "1d3", " 234", "1d5", "216" and "217" to generate the digital signal DBa. The coding table of 8B/10B is well known to those with ordinary knowledge in the relevant technical field, and for the sake of brevity, it will not be repeated here.

It should be noted that, in the codewords of the digital signal DBa output by the encoder 114 at the transmitting end, if any codeword has positive disparity, the codeword will be adjacent to another codeword with negative equality numbers. For example, the "1" in the codeword "3b1" is more than "0" (6 1s and 4 0s in total) and has positive inequality, so the "1" in the next codeword "232" is less than "0" (4 1s and 6 0s in total) has negative equality. Similarly, if any codeword has negative inequality, that codeword will be adjacent to another codeword with positive inequality. For example, the codeword "234" has negative equality, so its next codeword "1d5" has positive equality.

From the above, it can be seen that the encoder 114 at the transmitting end will be based on the inequality between the output of the multiplexer 112 (eg, the codeword "f2") and the previous codeword of the digital signal DBa (eg, the positive inequality of the codeword "3b1"). ) to determine the current codeword (eg, codeword "232") of the digital signal DBa. Thereby, the digital signal DBa is realized to be a DC-balanced signal, that is, a plurality of codewords of the digital signal DBa have substantially equal numbers of "0" and "1". The transmitter encoder 114 encodes the output of the second output end of the multiplexer 112 into a DC-balanced digital signal DBb according to a method similar to that described above, which is not repeated here for brevity.

Please refer to FIG. 1 again, the receiving-end decoding apparatus 140 includes a receiving-end decoder 142 and a demultiplexer 144 which are coupled to each other. The receiver decoder 142 is used for receiving the digital signals DBa and DBb from the receiver physical layer driver 130 . The receiver decoder 142 decodes the 10-bit codewords of the digital signals DBa and DBb into 8-bit codewords, and provides the 8-bit codewords corresponding to the digital signals DBa and DBb to the demultiplexer 144 respectively. A first input terminal and a second input terminal. The demultiplexer 144 also includes first to fourth output terminals. The demultiplexer 144 is used for alternately distributing the codewords received at the first input end of the demultiplexer 144 to the first output end and the second output end of the demultiplexer 144 to form the digital signals DCa and DCb, respectively. Similarly, the demultiplexer 144 alternately distributes the codewords received at the second input terminal of the demultiplexer 144 to the third output terminal and the fourth output terminal of the demultiplexer 144 to form the digital signals DCc and DCd, respectively.

FIG. 4 is a schematic diagram of a decoding result of the decoder 142 at the receiving end. As shown in FIG. 4, the receiver decoder 142 converts the 10-bit code words “236”, “3b1”, “232”, “1d3”, “234”, “1d5”, and “216” contained in the digital signal DBa " and "217" are decoded into 8-bit codewords "f0" to "f7", respectively. Therefore, the receiver decoder 142 is a 10-bit to 8-bit (10B/8B) decoder, but this disclosure is not limited thereto. In some embodiments, the receiver decoder 142 decodes the digital signals DBa and DBb with N-bit codewords into 1-bit codewords, where I is a positive integer and I is not equal to the aforementioned N.

FIG. 5 is a schematic diagram illustrating that the multiplexer 144 alternately distributes the codewords received at the same input end to its different output ends. As shown in FIG. 5, in an arbitrary period, the demultiplexer 144 sequentially receives the codewords "f0" to "f7" from its first input. The demultiplexer 144 sequentially provides the code words "f0", "f2", "f4" and "f6" through its first output terminal to form the digital signal DCa. Similarly, the demultiplexer 144 sequentially provides the code words "f1", "f3", "f5" and "f7" through its second output terminal to form the digital signal DCb. That is, adjacent codewords are assigned to different outputs of the demultiplexer 144 . The demultiplexer 144 generates the digital signals DCc and DCd in a similar manner, which is not repeated here for brevity.

Referring to FIG. 1 again, in one embodiment, the respective data transmission rates of the digital signals DAa˜DAd may be 4 Gbps (4 gigabytes per second), and the respective data transmission rates of the digital signals DBa˜DBb may be 10 Gbps. That is, the total data transfer rate of the digital signals DAa~DAd is 16Gbps, and the total data transfer rate of the digital signals DBa~DBb is 20Gbps. As can be seen from the above, the signal transmission system 100 can reduce the requirement for the number of transmission lines without reducing the data transmission rate, thereby helping to reduce the width of cables (eg, the cables 150 ) between electronic devices. However, this is only an example, and is not intended to limit the signal data transmission rate, the number of channels and the number of transmission lines in this disclosure.

FIG. 6 is a simplified functional block diagram of a signal transmission system 600 according to an embodiment of the present disclosure. The signal transmission system 600 is similar to the signal transmission system 100 in FIG. 1 , except that the signal transmission system 600 further includes a transmitter encoder 610 and a receiver decoder 620 . The transmitter encoder 610 is used for encoding the digital signals DDa~DDd to generate the digital signals DAa~DAd, respectively. In some embodiments, the digital signals DDa˜DDd may be video signals, audio signals or other control signals from a multimedia signal source (not shown). On the other hand, the receiver decoder 620 is used for decoding the digital signals DCa-DCd to generate the digital signals DEa-DEd respectively. In some embodiments, the receiver decoder 620 is used to provide the digital signals DEa-DEd to a video control chip or an audio control chip (not shown).

In some embodiments, the transmitter encoder 610 is an 8B/10B encoder, and the receiver decoder 620 is a 10B/8B decoder, but this embodiment is not limited thereto. In other embodiments, the digital signals DAa-DAd output by the transmitter encoder 610 are DC-balanced signals, that is, the respective codewords of the digital signals DAa-DAd have substantially equal numbers of 0s and 1s.

Generally speaking, a hierarchical design method is adopted for chip design, that is, the chip is divided into a plurality of functional blocks designed by a plurality of teams respectively. In some embodiments, the multimedia signal source and signal transmission system 600 are designed by different teams, and the multimedia signal source is designed on the assumption that the signals it generates will be provided to the encoder. Therefore, the transmitter encoder 610 helps the signal transmission system 600 to be compatible with multimedia signal sources. Similarly, the design team of the video control chip or the audio control chip and the signal transmission system 600 may be different, and the video control chip or the audio control chip may be designed based on the assumption of receiving the input signal from the decoder. Therefore, the receiver decoder 620 helps the signal transmission system 600 to be compatible with the video control chip or the audio control chip.

FIG. 7 is a simplified functional block diagram of a signal transmission system 700 according to an embodiment of the present disclosure. The signal transmission system 700 is similar to the signal transmission system 100 in FIG. 1 , except that the signal transmission system 700 further includes a transmitter encoder 710 , a transmitter decoder 720 , a receiver encoder 730 and a receiver decoder 740 . The transmitter encoder 710 is used for encoding the digital signals DDa-DDd to generate the digital signals DFa-DFd, respectively. The transmitter decoder 720 is used for decoding the digital signals DFa-DFd to generate the digital signals DAa-DAd, respectively. In some embodiments, the transmitter encoder 710 is an 8B/10B encoder, and the transmitter decoder 720 is a 10B/8B decoder, that is, the encoding/decoding algorithms of the transmitter encoder 710 and the transmitter decoder 720 They correspond to each other, but this disclosure is not limited thereto. In some embodiments, the transmitter encoder 710 is used for encoding the digital signals DDa~DDd with M-bit codewords into digital signals DFa~DFd with K-bit codewords, and the transmitter decoder 720 is used for encoding The digital signals DFa~DFd with K-bit codewords are decoded into digital signals DAa~DAd with M-bit codewords, where K and M are positive integers and K is not equal to M.

In other embodiments, the digital signals DFa-DFd output by the transmitter encoder 710 are DC-balanced signals, that is, the respective codewords of the digital signals DFa-DFd have substantially equal numbers of 0s and 1s.

The receiver encoder 730 is used for encoding the digital signals DCa-DCd to generate the digital signals DGa-DGd respectively. The receiver decoder 740 is used for decoding the digital signals DGa~DGd to generate the digital signals DEa~DEd respectively. In some embodiments, the receiver encoder 730 is an 8B/10B encoder, and the receiver decoder 740 is a 10B/8B decoder, that is, the encoding/decoding algorithms of the receiver encoder 730 and the receiver decoder 740 They correspond to each other, but this disclosure is not limited thereto. In some embodiments, the receiver encoder 730 encodes the digital signals DCa~DCd with a 1-bit codeword into the digital signals DGa~DGd with a J-bit codeword, where I and J are positive integers and I is not equal to J . In other embodiments, the receiver decoder 740 is configured to decode the digital signals DGa˜DGd having J-bit codewords into digital signals DEa˜DEd having 1-bit codewords.

In other embodiments, the digital signals DGa˜DGd output by the receiver encoder 730 are DC-balanced signals, that is, the respective codewords of the digital signals DGa˜DGd have substantially equal numbers of 0s and 1s.

Similar to the foregoing embodiment, the transmitter encoder 710 helps the signal transmission system 700 to be compatible with the multimedia signal source, and the receiver decoder 740 helps the signal transmission system 700 to be compatible with the video control chip or the audio control chip. This will not be repeated here. On the other hand, the transmitter decoder 720 and the receiver encoder 730 can reduce the minimum bandwidth requirement for the cable 150 by design.

For example, in one embodiment, the transmitter encoder 114 and the transmitter encoder 710 are both 8B/10B encoders, the transmitter decoder 720 is a 10B/8B decoder, and the respective data transmission rates of the digital signals DDa~DDd 4Gbps. At this time, the respective data transmission rates of the digital signals DBa and DBb are only 10 Gbps.

In another embodiment where the transmitter decoder 720 is omitted, the transmitter encoder 114 and the transmitter encoder 710 are both 8B/10B encoders, and the respective data transmission rates of the digital signals DDa~DDd are 4 Gbps. At this time, the data transmission rates of the digital signals DBa and DBb are increased to 12.5 Gbps.

The present disclosure provides various embodiments of converting 4 digital signals into two digital signals to reduce the number of signal lines, but the present disclosure is not limited thereto. In practice, the circuit structures of these embodiments can also be applied to convert 8 digital signals into 4 digital signals, or convert 16 digital signals into 8 digital signals, etc., and so on.

Certain terms are used in the specification and claims to refer to particular elements. However, those of ordinary skill in the art should understand that the same elements may be referred to by different nouns. The description and the scope of the patent application do not use the difference in name as a way of distinguishing elements, but use the difference in function of the elements as a basis for distinguishing. The "comprising" mentioned in the description and the scope of the patent application is an open-ended term, so it should be interpreted as "including but not limited to". In addition, "coupled" herein includes any direct and indirect means of connection. Therefore, if it is described in the text that the first element is coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection or signal connection such as wireless transmission or optical transmission, or through other elements or connections. The means are indirectly electrically or signally connected to the second element.

As used herein, the description "and/or" includes any combination of one or more of the listed items. In addition, unless otherwise specified in the specification, any term in the singular also includes the meaning in the plural.

The above are only preferred embodiments of the present disclosure, and all equivalent changes and modifications made according to the claims of the present disclosure shall fall within the scope of the present disclosure.

100,600,700: Signal Transmission System 110: Transmitter encoding device 112: Multiplexer 114, 610, 710: Transmitter encoder 120: transmitter physical layer driver 130: Receiver Entity Layer Driver 140: Receiver decoding device 142, 620, 740: Receiver decoder 144: Demultiplexer 150: Cable 720: Transmitter decoder 730: Receiver encoder DAa~DAd: digital signal DBa~DBb: digital signal DCa~DCd: digital signal DDa~DDd: digital signal DEa~DEd: digital signal DFa~DFd: digital signal DGa~DGd: digital signal

FIG. 1 is a simplified functional block diagram of a signal transmission system according to an embodiment of the present disclosure. FIG. 2 is a schematic diagram of the multiplexer alternately arranging codewords of different digital signals. FIG. 3 is a schematic diagram of the encoding result of the encoder at the transmitting end. FIG. 4 is a schematic diagram of the decoding result of the decoder at the receiving end. FIG. 5 is a schematic diagram of understanding that the multiplexer distributes the codewords received at the same input terminal alternately to its different output terminals. FIG. 6 is a simplified functional block diagram of a signal transmission system according to another embodiment of the present disclosure. FIG. 7 is a simplified functional block diagram of a signal transmission system according to another embodiment of the present disclosure.

100: Signal transmission system

110: Transmitter encoding device

112: Multiplexer

114: Transmitter encoder

120: transmitter physical layer driver

130: Receiver Entity Layer Driver

140: Receiver decoding device

142: Receiver decoder

144: Demultiplexer

150: Cable

DAa~DAd: digital signal

DBa~DBb: digital signal

DCa~DCd: digital signal

Claims (10)

A signal transmission system, comprising: A transmitter encoding device, comprising: a multiplexer for receiving a first digital signal and a second digital signal and generating an output, wherein the output includes a plurality of M-bit codewords of the first digital signal and includes and the first digital signal a plurality of M-bit codewords of the second digital signal alternately arranged with the plurality of M-bit codewords, and M is a positive integer; and a first transmit-end encoder for receiving the output of the multiplexer and generating a plurality of N-bit codewords, where N is a positive integer and M is not equal to N, wherein the first transmit-end encoder is used for according to the The inequality of the output of the multiplexer with a previous N-bit codeword in the plurality of N-bit codewords determines a current N-bit codeword in the plurality of N-bit codewords; and A receiving-end decoding device, coupled to the transmitting-end encoding device, includes: a first receiver decoder for decoding the plurality of N-bit codewords to generate a plurality of 1-bit codewords, where I is a positive integer and I is not equal to N; and a demultiplexer for alternately distributing the plurality of 1-bit codewords to a plurality of outputs of the demultiplexer. The signal transmission system of claim 1, wherein, if an arbitrary N-bit codeword among the plurality of N-bit codewords has positive inequality, then the arbitrary N-bit codeword is adjacent to the plurality of N-bit codewords One of the N-bit codewords with negative disparities. The signal transmission system as described in claim 1, further comprising: a second transmitter encoder for outputting the first digital signal and the second digital signal; The M-bit codewords of the first digital signal have substantially equal numbers of 1s and 0s, and the M-bit codewords of the second digital signal have substantially equal numbers of 1s and 0s. The signal transmission system of claim 3, further comprising a second receiver decoder, wherein the second receiver decoder is used for decoding the outputs of the plurality of output ends of the demultiplexer. The signal transmission system as described in claim 1, further comprising: a second transmitter encoder for outputting a third digital signal and a fourth digital signal, wherein a plurality of K-bit codewords of the third digital signal have substantially equal numbers of 1s and 0s, the fourth digital signal a plurality of K-bit codewords of the digital signal having a substantially equal number of ones and zeros, where K is a positive integer and K is not equal to M; and a first transmitter decoder for decoding the third digital signal and the fourth digital signal to generate the first digital signal and the second digital signal respectively. The signal transmission system as described in claim 5, further comprising: a first receiving end encoder for encoding the outputs of the plurality of output ends of the demultiplexer to output a fifth digital signal and a sixth digital signal, wherein a plurality of J bits of the fifth digital signal the codewords have a substantially equal number of ones and zeros, the plurality of J-bit codewords of the sixth digital signal have a substantially equal number of ones and zeros, wherein J is a positive integer and J is not equal to one; and a second receiver decoder for decoding the fifth digital signal and the sixth digital signal. A transmitter encoding device, comprising: a multiplexer for receiving a first digital signal and a second digital signal and generating an output, wherein the output includes a plurality of M-bit codewords of the first digital signal and includes and the first digital signal a plurality of M-bit codewords of the second digital signal alternately arranged with the plurality of M-bit codewords, and M is a positive integer; and a first transmit-end encoder for receiving the output of the multiplexer and generating a plurality of N-bit codewords, where N is a positive integer and M is not equal to N, wherein the first transmit-end encoder is used for according to the The inequality between the output of the multiplexer and a previous N-bit codeword in the plurality of N-bit codewords determines a current N-bit codeword in the plurality of N-bit codewords; The first transmitter encoder is used for transmitting the plurality of N-bit codewords to a receiver decoding device, and the receiver decoding device includes a demultiplexer and a decoding device for decoding the plurality of N-bit codewords. a first receiver decoder. The transmitting-end encoding apparatus as claimed in claim 7, wherein, if an arbitrary N-bit codeword among the plurality of N-bit codewords has positive inequality, the arbitrary N-bit codeword is adjacent to the One of a plurality of N-bit codewords with negative inequalities. The transmitter encoding device as claimed in claim 7, further comprising: a second transmitter encoder for outputting the first digital signal and the second digital signal; The M-bit codewords of the first digital signal have substantially equal numbers of 1s and 0s, and the M-bit codewords of the second digital signal have substantially equal numbers of 1s and 0s. The transmitter encoding device as described in claim 7, further comprising: a second transmitter encoder for outputting a third digital signal and a fourth digital signal, wherein a plurality of K-bit codewords of the third digital signal have substantially equal numbers of 1s and 0s, the fourth digital signal a plurality of K-bit codewords of the digital signal having substantially equal numbers of ones and zeros, where K is a positive integer and K is not equal to M; and a first transmitter decoder for decoding the third digital signal and the fourth digital signal to generate the first digital signal and the second digital signal respectively.

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