TWI768939B - Memory device - Google Patents

Abstract

A memory device is provided. The memory device includes a setting memory array and a controller. The setting memory array includes a plurality of flash memory strings coupled to each other in parallel. The flash memory strings respectively include a plurality of dummy memory cells and a one-bit trimmed memory cell. Trimmed memory cells store operating data for the memory device. In the same flash memory string, the trimmed memory cell is coupled in series between two of the dummy memory cells. The controller performs an approximate zero-voltage value reading operation on the trimmed memory cells to read operating data.

Description

memory device

The present invention relates to the field of memory, and more particularly, to a memory device capable of storing at least operating data for the memory device.

Generally, a memory device will require operational data to perform a boot operation. Operational data is also stored in other memory elements. However, taking the ETOX flash memory as an example, after the current memory device is powered on, the read voltage value must reach 5 volts to read the operation data. Therefore, the time length of the above-mentioned read operation is prolonged. In addition, the memory device for storing the operation data must have high reliability, so that the memory device can perform the expected start-up operation according to the correct operation data. Therefore, how to shorten the time length of the read operation and ensure that the memory device performs the correct start-up operation is one of the research focuses of those skilled in the art.

The present invention provides a memory device capable of shortening the time length of a read operation and ensuring that the memory device performs a correct start-up operation.

The memory device of the present invention includes a setting memory array and a controller. The configuration memory array includes a plurality of flash memory strings coupled in parallel with each other. The plurality of flash memory strings respectively include a plurality of dummy memory cells and trimmed memory cells of a single cell. Trim memory cells store operational data for the memory device. In the same flash memory string, trim memory cells are coupled in series between two of the plurality of dummy memory cells. The controller is coupled to the setting memory array. The controller performs an approximately zero-voltage reading operation on the plurality of trim cells of the setting memory array to read operation data.

Based on the above, the setting memory array of the present invention includes a plurality of flash memory strings coupled in parallel with each other. The plurality of flash memory strings respectively include a plurality of dummy memory cells and trimmed memory cells of a single cell. The controller performs an approximately zero-voltage reading operation on the plurality of trim cells of the setting memory array to read the operation data. In this way, the time length of the read operation for setting the memory array can be shortened. In addition, in the same flash memory string, trim memory cells are coupled in series between the plurality of dummy memory cells. In this way, the plurality of trimmed memory cells have high reliability.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

Some embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Element symbols quoted in the following description will be regarded as the same or similar elements when the same element symbols appear in different drawings. These examples are only a part of the invention and do not disclose all possible embodiments of the invention. Rather, these embodiments are only examples within the scope of the patent application of the present invention.

Please refer to FIG. 1 , which is a schematic diagram of a memory device according to an embodiment of the present invention. In this embodiment, the memory device 100 includes a main memory array 110 , a setting memory array 120 and a controller 130 . The main memory array 110 is a flash memory array. The main memory array 110 stores user data DTA. For example, the main memory array 110 may store the user data DTA in response to the operation of the controller 130 . The memory array 120 is set to include mutual flash memory strings ST1 ˜STm. The flash memory strings ST1 to STm respectively include a plurality of dummy memory cells and trimmed memory cells of a single cell. For example, the flash memory string ST1 includes dummy memory cells D11 to D1n and a trim memory cell T1. The flash memory string ST2 includes dummy memory cells D21 to D2n and a trim memory cell T2. Similarly, it can be inferred that the flash memory string STm includes dummy memory cells Dm1 to Dmn and trim memory cells Tm. In this embodiment, the trimmed memory cells T1 ˜Tm store the operation data OD for the memory device 100 . Therefore, the memory array 120 is set to be capable of storing m-bit operation data OD. Taking m=3 as an example, the operation data OD may be, for example, the selection code of the operation program. For example, the setting memory array 120 can store 8 different option codes associated with different operation programs. Therefore, the controller 130 can perform the operation procedure corresponding to the selection code (eg, the procedure of starting the main memory array 110 ) according to the selection code stored in the setting memory array 120 . Since the trimming memory cells T1-Tm are flash memory cells, the trimming memory cells T1-Tm can be at least multi-time programmable.

In this embodiment, in the same flash memory string, the trim memory cells are coupled in series between two of the dummy memory cells. Taking the flash memory string ST1 as an example, the trim memory cell T1 is coupled in series with the dummy memory cells D11 to D1n, and is coupled between the dummy memory cells D11 and D12. That is, the trim cell T1 is not the first or last bit memory cell of the flash memory string ST1. It should be noted that the first bit memory cell or the last bit memory cell of the flash memory strings ST1 ˜ STm are both boundary memory cells located at the boundary of the set memory array 120 . Boundary memory cells are less reliable. Because trimmed memory cells T1~Tm are not border memory cells. Trimming the memory cells T1 ˜Tm is not affected by setting the boundary conditions of the memory array 120 itself. In this way, trimming memory cells T1~Tm has high reliability.

In this embodiment, the controller 130 is coupled to the main memory array 110 and the setting memory array 120 . The controller 130 is operated to perform access operations to the main memory array 110 and the setting memory array 120 . The controller 130 performs an approximately zero-voltage reading operation on the trimmed memory cells T1 ˜Tm of the setting memory array 120 to read the operation data OD. Therefore, the controller 130 does not need to raise the voltage value of the judgment voltage for reading to a high voltage level (eg, 5 volts) during startup. The controller 130 may perform a read operation on the setting memory array 120 at the time of startup. In this way, the time length of the read operation for setting the memory array 120 can be shortened.

In this embodiment, the trimmed memory cells T1-Tm are flash memory cells. By changing the process parameters, the intrinsic threshold voltage of the trimmed memory cells T1~Tm can be lowered. The above-mentioned process parameters are, for example, the design of the well (eg, common well) and/or the doping concentration of the well. In this embodiment, the negative threshold voltage values of the trimmed memory cells T1 ˜Tm correspond to the first logic value. The positive threshold voltage values of the trimmed memory cells T1 ˜Tm correspond to the second logic value. The first logical value is different from the second logical value. Therefore, the controller 130 can perform a read operation on the trimmed memory cells T1 ˜Tm using the determination voltage having a low voltage value (eg, 0˜1.2 volts).

In this embodiment, the layouts of the dummy memory cells and the trimmed memory cells in the setting memory array 120 are substantially equal to the layouts of the memory cells in the main memory array 110 , respectively. Therefore, setting the boundary layout rule of the memory array 120 also conforms to the boundary layout rule of the main memory array 110 . As such, setting the memory array 120 does not require an additional mask. Therefore, the design cost of the photomask can be reduced.

In this embodiment, it is assumed that the memory array 120 can be located in the peripheral area of the memory device 100 and is independent of the main memory array 110 . That is to say, the setting memory array 120 and the main memory array 110 are respectively disposed in different regions. Therefore, the setting memory array 120 does not occupy the storage space of the main memory array 110 .

The implementation details of setting the memory array are further described. Please refer to FIG. 1 and FIG. 2 at the same time. FIG. 2 is a schematic diagram of a configuration memory array according to an embodiment of the present invention. The configuration memory array 220 is applicable to the memory device 100 . In this embodiment, the memory array 220 is set to be exemplified by three flash memory strings ST1 - ST3 . The number of the flash memory strings in the present invention may be multiple, and is not limited to the number of the flash memory strings ST1 to ST3 in this embodiment.

In the setting memory array 220, the flash memory string ST1 is located in the first row. The flash memory string ST1 includes dummy memory cells D11 to D13 and a trim memory cell T1. The flash memory string ST2 is located in the second row. The flash memory string ST2 includes dummy memory cells D21 to D23 and a trim memory cell T2. The flash memory string ST3 is located in the third row. The flash memory string ST3 includes dummy memory cells D31 to D33 and a trim memory cell T3. In this embodiment, the dummy memory cells D11 to D13 and the trim memory cell T1 are coupled in series with each other. The trimming memory cell T1 is coupled between the dummy memory cells D12 and D13. The dummy memory cells D21˜D23 and the trimming memory cell T2 are coupled in series with each other. The trimming memory cell T2 is coupled between the dummy memory cells D22 and D23. The dummy memory cells D31˜D33 and the trimming memory cell T3 are coupled in series with each other. The trimming memory cell T3 is coupled between the dummy memory cells D32 and D33.

In this embodiment, the control terminals of the trimming memory cells T1 ˜ T3 are commonly connected to the same word line WL. Therefore, trimmed memory cells T1~T3 are arranged in the same column. As such, the configuration memory array 220 may only have a single word line WL.

In this embodiment, the first end of the trimming memory cell T1 is electrically connected to the bit line BL1 without passing through at least one of the dummy memory cells D11 ˜ D13 . The first end of the trim memory cell T2 is electrically connected to the bit line BL2 without passing through at least one of the dummy memory cells D21-D23. The first end of the trimming memory cell T3 is electrically connected to the bit line BL3 without passing through at least one of the dummy memory cells D31 ˜ D33 . For example, the first end of the trimmed memory cell T1 is directly electrically connected to the bit line BL1. The first end of the trimmed memory cell T2 is directly electrically connected to the bit line BL2. The first end of the trimmed memory cell T3 is directly electrically connected to the bit line BL3.

In this embodiment, the second end of the trimmed memory cell T1, the second end of the trimmed memory cell T2, and the second end of the trimmed memory cell T3 are electrically connected to the source line CSL (or the common source line) without It will pass through at least one of the dummy memory cells D11~D13, D21~D23, and D31~D33. For example, the second end of the trimmed memory cell T1, the second end of the trimmed memory cell T2, and the second end of the trimmed memory cell T3 are directly electrically connected to the source line CSL. In this way, the memory array 220 can be set to have only a single source line CSL. Based on the above configuration, the controller 130 can perform a one-time erase operation on the trimmed memory cells T1 to T3, and then perform a programming operation on the selected trimmed memory cells to be programmed.

It is worth mentioning here that, based on the above configuration, the controller 130 uses the word line WL, the source line CSL and the bit lines BL1 ˜ BL3 to perform at least the erase operation and the programming operation on the trimmed memory cells T1 ˜ T3 at least one of them. In addition, the controller 130 uses the word line WL, the source line CSL and the bit lines BL1 ˜ BL3 to perform a read operation only on the trimmed memory cells T1 ˜ T3 . In this way, the present embodiment can avoid the read interference caused by the over-erase phenomenon of the dummy memory cells D11-D13, D21-D23, and D31-D33.

In some embodiments, the second end of the trimmed memory cell T1, the second end of the trimmed memory cell T2, and the second end of the trimmed memory cell T3 are electrically connected to different source lines, respectively.

Please refer to FIG. 1 and FIG. 3 at the same time. FIG. 3 is a schematic diagram of a data state of a trimmed memory cell according to an embodiment of the present invention. In this embodiment, the controller 130 may perform at least one of an erase operation and a programming operation on the trimmed memory cells T1 ˜Tm to store the operation data OD on the trimmed memory cells T1 ˜Tm. The controller 130 provides a larger erase voltage for 0.1 second to 1 second to perform the erase operation on at least one of the trimmed memory cells T1 ˜Tm. Therefore, the threshold voltage value Vt of the trimmed memory cell to be erased will be less than or equal to -1 volt. The voltage value Vt less than or equal to -1 volt may correspond to the first logic value LG1, such as logic "1". In this embodiment, the erase operation may be a one-shot strong erase operation. Therefore, the controller 130 may not perform the erase verification operation after the erase operation.

In addition, the controller 130 can also trim at least one of the memory cells T1 ˜Tm so that the threshold voltage value Vt of the trimmed memory cell to be programmed is greater than or equal to 2 volts. The voltage value Vt greater than or equal to 2 volts may correspond to the second logic value LG2, such as logic "0".

In this embodiment, the controller 130 may use a judgment voltage with a low voltage value (eg, 0 volts to a predetermined voltage value VDD) to perform a read operation on the trimmed memory cells. Taking the trimmed memory cell to be erased as an example, since the threshold voltage Vt of the trimmed memory cell to be erased is less than or equal to -1 volt, it is judged that the voltage is sufficient to make the trimmed memory cell conduct, thereby generating a current greater than a threshold value. The reading current value (about 10-15 microamps, the present invention is not limited to this). Therefore, the trimmed memory cell can be known to store the data of the first logic value LG1 (eg, logic "1").

Taking the trimmed memory cell to be programmed as an example, since the threshold voltage Vt of the trimmed memory cell to be programmed is greater than or equal to 2 volts, it is judged that the voltage cannot make the trimmed memory cell to be programmed to conduct. During the read operation being performed, the trim cell to which the programming operation is performed is disconnected. The read current value approaches 0. Reading the current value will be lower than the current threshold. Therefore, the trimmed memory cell can be known to store the data of the second logic value LG2 (eg, logic "0").

In this embodiment, the preset voltage value VDD may be 1.2 volts. That is, the voltage value of the current judgment voltage may have a margin M of 1.2 volts. By changing the process parameters, the threshold voltage value Vt of the trimmed memory cell in different logic states can be changed. Therefore, the margin M of the voltage value of the judgment voltage can be wider.

Please refer to FIG. 4 , which is a schematic diagram of a memory device according to another embodiment of the present invention. In this embodiment, the memory device 300 includes a main memory array 310 , a setting memory array 320 and a controller 330 . Different from the memory device 100 shown in FIG. 1 , it is assumed that the memory array 320 is a sub-array divided from the main memory array 310 . The implementation details of setting the memory array 320 and the controller 330 can be sufficiently taught from the various embodiments of FIGS. 1 to 3 , and thus will not be repeated here.

To sum up, the setting memory array of the present invention includes a plurality of flash memory strings coupled in parallel with each other. The plurality of flash memory strings respectively include a plurality of dummy memory cells and trimmed memory cells of a single cell. Trim memory cells store operational data for the memory device. The controller performs an approximately zero-voltage reading operation on the plurality of trim cells of the setting memory array to read the operation data. In this way, the time length of the read operation for setting the memory array can be shortened. In the same flash memory string, trim memory cells are coupled in series between the plurality of dummy memory cells. Therefore, trimming the memory cells is not affected by setting the boundary conditions of the memory array itself. In this way, the plurality of trimmed memory cells have high reliability. In addition, the memory device operates on trimmed memory cells. In this way, the present invention can avoid the read disturbance caused by the over-erase phenomenon of the dummy memory cells.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the appended patent application.

100, 300: memory device 110, 310: Main memory array 120, 220, 320: set memory array 130, 330: Controller BL1, BL2, BL3: bit lines CSL: source line D11, D12, D13, D1n, D21, D22, D23, D2n, D31, D32, D33, Dm1, Dm2, Dmn: Dummy memory cells DTA: User Profile LG1: first logic value LG2: second logic value M: Margin OD: Operational Data ST1, ST2, ST3, STm: Flash memory string T1, T2, T3, Tm: trimmed memory cells VDD: preset voltage value Vt: threshold voltage value WL: word line

FIG. 1 is a schematic diagram of a memory device according to an embodiment of the present invention. FIG. 2 is a schematic diagram illustrating a configuration memory array according to an embodiment of the present invention. 3 is a schematic diagram of a data state of a trimmed memory cell according to an embodiment of the present invention. FIG. 4 is a schematic diagram of a memory device according to another embodiment of the present invention.

100: Memory device

110: Main memory array

120: Set the memory array

130: Controller

D11, D12, D1n, D21, D22, D2n, Dm1, Dm2, Dmn: dummy memory cells

DTA: User Profile

OD: Operational Data

ST1, ST2, STm: Flash memory string

T1, T2, Tm: trimmed memory cells

Claims (11)

A memory device comprising: A memory array is configured to include a plurality of flash memory strings coupled in parallel with each other, wherein the plurality of flash memory strings respectively include: a plurality of dummy memory cells; and a single-bit trim cell configured to store operating data for the memory device, wherein the trim cell is coupled in series to the plurality of dummy memories in the same flash memory string between two of the cells; and A controller, coupled to the setting memory array, is configured to perform an approximately zero-voltage reading operation on a plurality of trim cells of the setting memory array to read the operation data. The memory device of claim 1, wherein: The negative threshold voltage values of the plurality of trimmed memory cells correspond to the first logic value, and The positive threshold voltage values of the plurality of trimmed memory cells correspond to the second logic value. The memory device of claim 1, wherein the control terminals of the plurality of trim cells of the setting memory array are commonly connected to the same word line. The memory device of claim 1, wherein: The first terminal of the first trim cell of the first flash memory string is electrically connected to the first bit line without passing through the plurality of dummy cells of the first flash memory string at least one of them, and The first end of the second trimmed memory cell of the first flash memory string is electrically connected to the second bit line without passing through a plurality of dummy memory cells of the second flash memory string at least one of them. The memory device of claim 4, wherein the second end of the first trimmed memory cell and the second end of the second trimmed memory cell are electrically connected to source lines without passing through the plurality of At least one of the dummy memory cells. The memory device of claim 1, wherein the controller is further configured to perform at least one of an erase operation and a program operation on the plurality of trim cells to store the plurality of trim cells the operating data. The memory device of claim 6, wherein the erase operation is a single-click strong erase operation, and The threshold voltage value of the trimmed memory cell on which the erase operation is performed is less than or equal to -1 volt. The memory device of claim 6, wherein a threshold voltage value of a trimmed memory cell on which the programming operation is performed is greater than or equal to 2 volts. The memory device of claim 1, further comprising: a main memory array configured to store user data, The layouts of the plurality of dummy memory cells and the plurality of trim memory cells in the setting memory array are respectively substantially equal to the layouts of the memory cells of the main memory array. The memory device of claim 9, wherein the setting memory array is located in a peripheral area of the memory device and is independent of the main memory array. The memory device of claim 9, wherein the setting memory array is a sub-array divided from the main memory array.

Images