TWI768543B - Integrated circuit and in-system programming circuit thereof - Google Patents

Integrated circuit and in-system programming circuit thereof Download PDF

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TWI768543B
TWI768543B TW109139747A TW109139747A TWI768543B TW I768543 B TWI768543 B TW I768543B TW 109139747 A TW109139747 A TW 109139747A TW 109139747 A TW109139747 A TW 109139747A TW I768543 B TWI768543 B TW I768543B
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signal
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clock signal
clock
circuit
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TW202219756A (en
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劉則言
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新唐科技股份有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality

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Abstract

An integrated circuit and an in-system programming (ISP) circuit thereof are provided. The ISP circuit includes an action launcher and a command generator. The action launcher receives an input signal according to a first clock to obtain first input data, and enables an activating signal by comparing the first input data and target data. The command generator receives the input signal top obtain second input data according to a second clock signal when the activating signal is enabled, and obtain a in-system programming command by decoding the second input data. The command generator provides the in-system programming command to a memory apparatus to set the memory apparatus to perform an accessing action. A frequency of the first clock signal is lower than a frequency of the second clock signal.

Description

積體電路及其系統內程式化電路Integrated circuits and their in-system programmed circuits

本發明是有關於一種積體電路及其系統內程式化電路，且特別是有關於一種可降低功率消耗的積體電路及其系統內程式化電路。The present invention relates to an integrated circuit and its in-system programming circuit, and more particularly, to an integrated circuit and its in-system programming circuit capable of reducing power consumption.

在物聯網的時代，為了增加產品的續航力，產品內部除了增加電池的蓄電量外，低功耗設計也是晶片的發展趨勢。系統內程式化電路（In-system programming, ISP）是一種可以藉由輸入控制信號，不須透過處理器便可以對晶片內的記憶體進行讀、寫的控制電路。然而，作為隨時要接收數個來自外部控制訊號的系統內程式化電路，運作時的功率消耗的高低會確實反映在電路的上電過程與晶片運作期間。倘若在設計上降低了執行程式化動作的時脈頻率，雖然能降低電路的功率耗損，但卻會使系統內程式化動作的運作效率大幅下降，導致原先的操作行為就要花費更長的時間才能完成。因此，如何維持電路的效能又能降低未執行系統內程式化動作時所耗去的功率消耗，為本領域設計者的重要課題。In the era of the Internet of Things, in order to increase the endurance of the product, in addition to increasing the storage capacity of the battery inside the product, the low-power design is also the development trend of the chip. In-system programming (ISP) is a control circuit that can read and write the memory in the chip without going through a processor by inputting control signals. However, as a programmed circuit in the system that needs to receive several external control signals at any time, the level of power consumption during operation will indeed be reflected in the power-on process of the circuit and the operation of the chip. If the clock frequency for executing programmed actions is reduced in design, although the power consumption of the circuit can be reduced, the operational efficiency of programmed actions in the system will be greatly reduced, resulting in the original operation taking longer time. to complete. Therefore, how to maintain the performance of the circuit and reduce the power consumption when the programmed operation in the system is not performed is an important issue for designers in the art.

本發明提供一種積體電路及其系統內程式化電路，可有效節省功率消耗。The present invention provides an integrated circuit and its in-system programmed circuit, which can effectively save power consumption.

本發明的系統內程式化電路包括動作啟動器以及命令產生器。動作啟動器依據第一時脈信號以接收輸入信號來獲得第一輸入資料，依據比較第一輸入資料以及目標資料來致能啟動信號。命令產生器在啟動信號被致能時，依據第二時脈信號以接收輸入信號來獲得第二輸入資料，依據解碼第二輸入資料以獲得系統內程式化命令。其中，命令產生器提供系統內程式化命令至記憶體裝置以使記憶體裝置執行存取動作，第一時脈信號的頻率低於第二時脈信號的頻率。The in-system programming circuit of the present invention includes an action initiator and a command generator. The action initiator receives the input signal according to the first clock signal to obtain the first input data, and enables the activation signal according to the comparison between the first input data and the target data. When the enable signal is enabled, the command generator receives the input signal according to the second clock signal to obtain the second input data, and decodes the second input data to obtain the in-system programmed command. The command generator provides an in-system programmed command to the memory device to enable the memory device to perform an access operation, and the frequency of the first clock signal is lower than the frequency of the second clock signal.

本發明的積體電路包括第一時脈產生器、第二時脈產生器、記憶體裝置以及系統內程式化電路。第一時脈產生器產生第一時脈信號。第二時脈產生器依據啟動信號來產生第二時脈信號，其中第二時脈信號的頻率高於第一時脈信號的頻率。系統內程式化電路包括動作啟動器以及命令產生器。動作啟動器依據第一時脈信號以接收輸入信號來獲得第一輸入資料，依據比較第一輸入資料以及目標資料來致能啟動信號。命令產生器在啟動信號被致能時，依據第二時脈信號以接收輸入信號來獲得第二輸入資料，依據解碼第二輸入資料以獲得系統內程式化命令。其中，命令產生器提供系統內程式化命令至記憶體裝置以使記憶體裝置執行存取動作。The integrated circuit of the present invention includes a first clock generator, a second clock generator, a memory device, and an in-system programming circuit. The first clock generator generates a first clock signal. The second clock generator generates a second clock signal according to the enable signal, wherein the frequency of the second clock signal is higher than the frequency of the first clock signal. The programmed circuits in the system include action initiators and command generators. The action initiator receives the input signal according to the first clock signal to obtain the first input data, and enables the activation signal according to the comparison between the first input data and the target data. When the enable signal is enabled, the command generator receives the input signal according to the second clock signal to obtain the second input data, and decodes the second input data to obtain the in-system programmed command. The command generator provides in-system programmed commands to the memory device to enable the memory device to perform an access operation.

基於上述，本發明透過使系統內程式化電路分別在不同的狀態下，依據不同頻率的第一時脈信號以及第二時脈信號來分別執行動作。如此一來，在系統內程式化動作未被啟動時，系統內程式化電路可工作可依據具有相對低頻率的第一時脈信號，以偵測是否有執行系統內程式化動作的需求。並在需執行系統內程式化動作時，依據具有相對高頻率的第二時脈信號來工作。如此一來，在不減低系統內程式化動作的工作效能的前提下，可有效降低功率消耗。Based on the above, the present invention enables the programming circuits in the system to perform operations respectively according to the first clock signal and the second clock signal of different frequencies in different states. In this way, when the programming action in the system is not activated, the programming circuit in the system can work according to the relatively low frequency first clock signal to detect whether there is a need to execute the programming action in the system. And when the programmed action in the system needs to be performed, it works according to the second clock signal with a relatively high frequency. In this way, the power consumption can be effectively reduced without reducing the work performance of the programmed actions in the system.

請參照圖1，圖1繪示本發明一實施例的系統內程式化電路的示意圖。系統內程式化（in-system programming, ISP）電路100包括動作啟動器110以及命令產生器120。動作啟動器110接收第一時脈信號CK1以及輸入信號IS，並依據第一時脈信號CK1以接收輸入信號IS來獲得第一輸入資料。動作啟動器110並針對第一輸入資料以及目標資料進行比較，並依據比較結果來產生啟動信號EN。Please refer to FIG. 1 , which is a schematic diagram of an in-system programming circuit according to an embodiment of the present invention. The in-system programming (ISP) circuit 100 includes an action initiator 110 and a command generator 120 . The motion initiator 110 receives the first clock signal CK1 and the input signal IS, and obtains the first input data by receiving the input signal IS according to the first clock signal CK1. The action initiator 110 compares the first input data and the target data, and generates an enabling signal EN according to the comparison result.

其中，在動作細節上，在初始狀態下，啟動信號EN可以為禁能的狀態。在此時，動作啟動器110可依據第一時脈信號CK1以接收輸入信號IS來獲得第一輸入資料，並針對第一輸入資料來與預設的目標資料進行比對。在當第一輸入資料來與目標資料相同時，動作啟動器110可變更啟動信號EN為致能的狀態。In terms of action details, in an initial state, the enable signal EN may be in a disabled state. At this time, the action initiator 110 can receive the input signal IS according to the first clock signal CK1 to obtain the first input data, and compare the first input data with the preset target data. When the first input data is the same as the target data, the action initiator 110 can change the enable signal EN to the enabled state.

在本實施例中，啟動信號EN在致能狀態下可以為第一邏輯準位（邏輯0或邏輯1），啟動信號EN在禁能狀態下則可以為第二邏輯準位（邏輯1或邏輯0），第一邏輯準位與第二邏輯準位互補。In this embodiment, the enable signal EN may be at the first logic level (logic 0 or logic 1) in the enabled state, and the enable signal EN may be at the second logic level (logic 1 or logic 1) in the disabled state 0), the first logic level and the second logic level are complementary.

此外，命令產生器120耦接至動作啟動器110。在啟動信號EN被致能時，命令產生器120依據第二時脈信號CK2以接收輸入信號IS來獲得第二輸入資料。命令產生器120可針對第二輸入資料進行解碼，並獲得系統內程式化命令CMD。命令產生器120並傳送系統內程式化命令CMD至積體電路內的記憶體裝置中，以使記憶體裝置依據系統內程式化命令CMD執行程式化的相關動作，例如程式化（program）動作、抹除（erase）動作或是讀取（read）（驗證（verify））動作。記憶體裝置則可以為一非揮發式記憶體。其中，在本實施例中，第一時脈信號CK1的頻率低於第二時脈信號CK2的頻率。In addition, the command generator 120 is coupled to the action initiator 110 . When the enable signal EN is enabled, the command generator 120 receives the input signal IS according to the second clock signal CK2 to obtain the second input data. The command generator 120 can decode the second input data and obtain the in-system programmed command CMD. The command generator 120 transmits the in-system programming command CMD to the memory device in the integrated circuit, so that the memory device executes programming-related actions according to the in-system programming command CMD, such as program action, Erase (erase) action or read (read) (verify (verify)) action. The memory device may be a non-volatile memory. Wherein, in this embodiment, the frequency of the first clock signal CK1 is lower than the frequency of the second clock signal CK2.

進一步來說明，在啟動信號EN被致能之前，具有相對高頻率的第二時脈信號CK2並不會被產生，並藉以達到省電的效果。在啟動信號EN被致能之後，第二時脈信號CK2才會被產生，並作為命令產生器120接收輸入信號IS的依據。而在另一方面，在啟動信號EN被致能之後，動作啟動器110接收輸入信號IS的路徑會被切斷，並停止輸入信號IS的接收動作，也可以達到省電的效果。To further illustrate, before the enable signal EN is enabled, the second clock signal CK2 with a relatively high frequency will not be generated, so as to achieve the effect of power saving. After the enable signal EN is enabled, the second clock signal CK2 is generated and used as the basis for the command generator 120 to receive the input signal IS. On the other hand, after the enable signal EN is enabled, the path through which the motion enabler 110 receives the input signal IS is cut off, and the receiving operation of the input signal IS is stopped, which can also achieve the effect of power saving.

此外，在本發明實施例中，命令產生器120並可依據第二輸入資料來產生終止信號EXIT。命令產生器120傳送終止信號EXIT至動作啟動器110。當動作啟動器110接收到被致能的終止信號EXIT時，動作啟動器110依據終止信號EXIT以使啟動信號EN變更為禁能的狀態。In addition, in the embodiment of the present invention, the command generator 120 may generate the termination signal EXIT according to the second input data. The command generator 120 transmits the termination signal EXIT to the action initiator 110 . When the action initiator 110 receives the enabled termination signal EXIT, the action initiator 110 changes the enable signal EN to a disabled state according to the termination signal EXIT.

附帶一提的，在本發明實施例中，動作啟動器110以及命令產生器120可通過相同的匯流排來接收輸入信號IS。為使輸入信號IS的接收可以正確無誤，動作啟動器110以及命令產生器120可以設置同步電路，先針對輸入信號IS分別依據第一時脈信號CK1以及第二時脈信號CK2進行同步動作後，再針對同步後的輸入信號IS進行讀取動作。Incidentally, in the embodiment of the present invention, the action initiator 110 and the command generator 120 may receive the input signal IS through the same bus. In order to ensure that the input signal IS can be received correctly, the action starter 110 and the command generator 120 can be provided with a synchronization circuit. Then, the read operation is performed for the synchronized input signal IS.

由上述說明不難得知，本發明實施例的系統內程式化電路100分別依據兩個頻率不相同的時脈信號（第一時脈信號CK1以及第二時脈信號CK2）來分別執行動作啟動的判斷以及程式化命令的解碼。並使動作啟動器110工作在相對低的頻率下，可有效降低所需的功率消耗。It is not difficult to know from the above description that the in-system programming circuit 100 according to the embodiment of the present invention respectively executes the action activation according to two clock signals (the first clock signal CK1 and the second clock signal CK2 ) with different frequencies. Determination and decoding of stylized commands. Making the motion initiator 110 work at a relatively low frequency can effectively reduce the required power consumption.

以下請參照圖2，圖2繪示本發明另一實施例的系統內程式化電路的示意圖。系統內程式化電路200包括動作啟動器210、命令產生器220以及邏輯電路230。動作啟動器210接收第一時脈信號CK1，透過邏輯電路230以接收輸入信號IS，並接收終止信號EXIT。在本實施例中，邏輯電路230包括反向器INV1以及及閘AN1。在當致能信號EN為禁能的狀態（例如為邏輯0），反向器INV1可傳送為邏輯1的輸出至及閘AN1的一輸入端。在此狀況下，及閘AN1的輸出端可輸出另一輸入端所接收的輸入信號IS，並使輸入信號IS被傳送至動作啟動器210中。在此同時，動作啟動器210可依據第一時脈信號CK1來接收輸入信號IS，並獲得第一輸入資料。動作啟動器210並可依據使第一輸入資料與預設的目標資料進行比較，並在當第一輸入資料與目標資料相同時，使啟動信號EN變更為致能的狀態（邏輯1）。Please refer to FIG. 2 below. FIG. 2 is a schematic diagram of an in-system programming circuit according to another embodiment of the present invention. The in-system programming circuit 200 includes an action initiator 210 , a command generator 220 and a logic circuit 230 . The action initiator 210 receives the first clock signal CK1, receives the input signal IS through the logic circuit 230, and receives the termination signal EXIT. In this embodiment, the logic circuit 230 includes an inverter INV1 and a gate AN1. When the enable signal EN is in a disabled state (eg, logic 0), the inverter INV1 can transmit a logic 1 output to an input terminal of the AND gate AN1. In this case, the output terminal of the AND gate AN1 can output the input signal IS received by the other input terminal, and the input signal IS is transmitted to the action starter 210 . At the same time, the action initiator 210 can receive the input signal IS according to the first clock signal CK1 and obtain the first input data. The action initiator 210 can compare the first input data with the preset target data, and change the enable signal EN to an enabled state (logic 1) when the first input data is the same as the target data.

在本實施例中，目標資料可以視為啟動系統內程式化電路200以執行系統內程式化動作的鎖鑰資訊。In this embodiment, the target data can be regarded as lock-key information for enabling the in-system programming circuit 200 to execute in-system programming actions.

值得一提的，邏輯電路230中所設置的邏輯閘，可以依據啟動信號EN禁能時的邏輯準位，以及設計者的喜好來進行變更。重點在於，當啟動信號EN禁能時，邏輯電路230可使輸入信號IS被傳送至動作啟動器210，而在當啟動信號EN致能時，邏輯電路230可使輸入信號IS被遮蔽，而避免被傳送至動作啟動器210。圖2中的反向器INV1以及及閘AN1的實施方式只是說明用的範例，不用以限縮本發明的範疇。It is worth mentioning that the logic gate set in the logic circuit 230 can be changed according to the logic level when the enable signal EN is disabled and the designer's preference. The point is that when the enable signal EN is disabled, the logic circuit 230 enables the input signal IS to be transmitted to the motion enabler 210, and when the enable signal EN is enabled, the logic circuit 230 enables the input signal IS to be masked to avoid is passed to the action initiator 210 . The implementations of the inverter INV1 and the gate AN1 in FIG. 2 are only examples for illustration, and are not intended to limit the scope of the present invention.

在當啟動信號EN為致能的狀態時，第二時脈信號CK2可被提供至命令產生器220。在此同時，命令產生器220可依據第二時脈信號CK2以接收輸入信號IS來獲得第二輸入資料。命令產生器220可針對第二輸入資料進行解碼動作，並藉以產生系統內程式化命令CMD。其中，系統內程式化命令CMD用以提供至記憶體裝置，並使記憶體裝置執行程式化、抹除或讀取（驗證）動作。When the enable signal EN is in an enabled state, the second clock signal CK2 may be provided to the command generator 220 . At the same time, the command generator 220 can receive the input signal IS according to the second clock signal CK2 to obtain the second input data. The command generator 220 can perform a decoding operation on the second input data, thereby generating an in-system programmed command CMD. The in-system programming command CMD is provided to the memory device, and the memory device executes programming, erasing or reading (verification) actions.

在本實施例中，命令產生器220可以為一命令解碼器（command decoder）。命令產生器220例如可先預存對應程式化、抹除或讀取（驗證）動作的資訊，並使第二輸入資料與對應程式化、抹除或讀取（驗證）動作的資訊比對。當第二輸入資料與對應程式化動作的資訊相符時，則產生可驅使記憶體裝置執行程式化動作的系統內程式化命令CMD；當第二輸入資料與對應抹除動作的資訊相符時，則產生可驅使記憶體裝置執行抹除動作的系統內程式化命令CMD；當第二輸入資料與對應讀取（驗證）動作的資訊相符時，則產生可驅使記憶體裝置執行讀取（驗證）動作的系統內程式化命令CMD。In this embodiment, the command generator 220 may be a command decoder. For example, the command generator 220 may pre-store the information corresponding to the programming, erasing or reading (verification) actions, and compare the second input data with the information corresponding to the programming, erasing or reading (verification) actions. When the second input data matches the information corresponding to the programmed action, an in-system programmed command CMD that can drive the memory device to execute the programmed action is generated; when the second input data matches the information corresponding to the erase action, then Generate an in-system programmed command CMD that can drive the memory device to execute the erase action; when the second input data matches the information corresponding to the read (verify) action, generate the memory device to execute the read (verify) action The in-system stylized command CMD.

附帶一提的，命令產生器220另可依據第二輸入資料來致能所產生的終止信號EXIT。在本實施例中，當終止信號EXIT被致能為邏輯1時，動作啟動器210可依據終止信號EXIT以使啟動信號EN被變更為禁能的狀態（例如邏輯0），並藉此結束系統內程式化動作。Incidentally, the command generator 220 can further enable the generated termination signal EXIT according to the second input data. In this embodiment, when the termination signal EXIT is enabled to be a logic 1, the action initiator 210 can change the enable signal EN to a disabled state (eg, a logic 0) according to the termination signal EXIT, thereby ending the system Internally programmed actions.

以下請參照圖3，圖3繪示本發明實施例的動作啟動器的實施方式的示意圖。在圖3中，動作啟動器300包括同步電路310、資料緩衝器320以及比較器330。同步電路310接收輸入信號IS以及第一時脈信號CK1。同步電路310依據第一時脈信號CK1以針對輸入信號IS進行同步動作，並產生同步後輸入信號SYNIS。資料緩衝器320則接收同步後輸入信號SYNIS以及第一時脈信號CK1，並依據第一時脈信號CK1來接收同步後輸入信號SYNIS以獲得第一輸入資料SD1，並將第一輸入資料SD1儲存在資料緩衝器320中。Please refer to FIG. 3 below. FIG. 3 is a schematic diagram illustrating an implementation of an action starter according to an embodiment of the present invention. In FIG. 3 , the action initiator 300 includes a synchronization circuit 310 , a data buffer 320 and a comparator 330 . The synchronization circuit 310 receives the input signal IS and the first clock signal CK1. The synchronization circuit 310 performs a synchronization operation with respect to the input signal IS according to the first clock signal CK1, and generates a synchronized input signal SYNIS. The data buffer 320 receives the synchronized input signal SYNIS and the first clock signal CK1, receives the synchronized input signal SYNIS according to the first clock signal CK1 to obtain the first input data SD1, and stores the first input data SD1 in data buffer 320.

在另一方面，比較器330耦接至資料緩衝器320。比較器330使第一輸入資料SD1與目標資料KEY進行比較，並依據比較結果來決定啟動信號EN的邏輯準位。其中，當第一輸入資料SD1與目標資料KEY相同時，啟動信號EN可以為致能的邏輯準位（例如邏輯1）；而當第一輸入資料SD1與目標資料KEY不相同時，啟動信號EN可以為禁能的邏輯準位（例如邏輯0）。On the other hand, the comparator 330 is coupled to the data buffer 320 . The comparator 330 compares the first input data SD1 with the target data KEY, and determines the logic level of the enable signal EN according to the comparison result. Wherein, when the first input data SD1 is the same as the target data KEY, the enable signal EN can be an enabled logic level (eg, logic 1); and when the first input data SD1 is different from the target data KEY, the enable signal EN Can be a disabled logic level (eg logic 0).

此外，比較器330另接收終止信號EXIT。當終止信號EXIT為致能時，比較器330可以使啟動信號EN由致能轉換為禁能的狀態。其中，比較器330可以依據致能的終止信號EXIT來重置啟動信號EN為禁能的狀態，或者，比較器330也可以透過邏輯運算的方式，來依據致能的終止信號EXIT使啟動信號EN為禁能的狀態。In addition, the comparator 330 further receives the termination signal EXIT. When the termination signal EXIT is enabled, the comparator 330 can make the enable signal EN change from the enabled state to the disabled state. The comparator 330 can reset the enable signal EN to a disabled state according to the enabled termination signal EXIT, or the comparator 330 can also enable the enable signal EN according to the enabled termination signal EXIT by means of logic operation. for the disabled state.

在硬體架構方面，同步電路310、資料緩衝器320以及比較器330可應用邏輯電路來建構。例如，同步電路310可應用D型正反器來實施，資料緩衝器320可通過多個暫存器來實施，而比較器330例如可應用互斥或閘來實施。當然，本領域具通常知識者也可應用其他類型的邏輯電路來實施，沒有特定的限制。In terms of hardware structure, the synchronization circuit 310, the data buffer 320 and the comparator 330 can be constructed by applying logic circuits. For example, the synchronization circuit 310 can be implemented by a D-type flip-flop, the data buffer 320 can be implemented by a plurality of registers, and the comparator 330 can be implemented by, for example, a mutex or gate. Of course, those skilled in the art can also apply other types of logic circuits to implement, without specific limitations.

以下請參照圖4，圖4繪示本發明一實施例的積體電路的示意圖。積體電路400可設置在單一晶片上，包括系統內程式化電路410、時脈產生器420、430以及記憶體裝置440。時脈產生器420、430分別用以產生第一時脈信號CK1以及第二時脈信號CK2，其中第一時脈信號CK1的頻率低於第二時脈信號CK2的頻率。其中的時脈產生器430可依據啟動信號EN以決定是否產生第二時脈信號CK2，當啟動信號EN為禁能狀態時，時脈產生器430產生第二時脈信號CK2，相對的，當啟動信號EN為致能狀態時，時脈產生器430停止產生第二時脈信號CK2。Please refer to FIG. 4 below. FIG. 4 is a schematic diagram of an integrated circuit according to an embodiment of the present invention. The integrated circuit 400 may be provided on a single chip and includes the in-system programming circuit 410 , the clock generators 420 , 430 and the memory device 440 . The clock generators 420 and 430 are respectively used for generating the first clock signal CK1 and the second clock signal CK2, wherein the frequency of the first clock signal CK1 is lower than the frequency of the second clock signal CK2. The clock generator 430 can determine whether to generate the second clock signal CK2 according to the enable signal EN. When the enable signal EN is in the disabled state, the clock generator 430 generates the second clock signal CK2. When the enable signal EN is in the enabled state, the clock generator 430 stops generating the second clock signal CK2.

另外，系統內程式化電路410依據第一時脈信號CK1、第二時脈信號CK2以及輸入信號IS來產生啟動信號EN以及系統內程式化命令CMD，相關的動作細節在前述的實施例以及實施方式中已有詳細的說明，在此不多贅述。In addition, the in-system programming circuit 410 generates the enable signal EN and the in-system programming command CMD according to the first clock signal CK1, the second clock signal CK2 and the input signal IS. The details of the operations are described in the foregoing embodiments and implementations The method has been described in detail, and will not be repeated here.

在另一方面，啟動信號EN、系統內程式化命令CMD以及第二時脈信號CK2被提供至記憶體裝置440。記憶體裝置440包括記憶體控制器441以及記憶體442。記憶體控制器441可依據啟動信號EN、系統內程式化命令CMD以及第二時脈信號CK2來針對記憶體442執行程式化動作、抹除動作或是讀取（驗證）動作。On the other hand, the enable signal EN, the in-system programming command CMD and the second clock signal CK2 are provided to the memory device 440 . The memory device 440 includes a memory controller 441 and a memory 442 . The memory controller 441 can perform programming, erasing or reading (verification) operations for the memory 442 according to the enable signal EN, the in-system programming command CMD and the second clock signal CK2.

在本實施例中，記憶體442可以為非揮發性記憶體，例如快閃記憶體。In this embodiment, the memory 442 may be a non-volatile memory, such as a flash memory.

綜上所述，本發明提供兩個不同頻率的時脈信號，以作為系統內程式化電路的工作依據。其中，在檢測是否要啟動系統內程式化動作的過程中，可利用具有較低頻率的第一時脈信號來做為工作的依據。在執行系統內程式化動作的過程中，則利用具有相對高頻率的第二時脈信號來做為工作的依據。如此一來，在不減低系統內程式化動作效率的前提下，可有效降低系統內程式化電路所需的功率消耗，達到節能減碳的功效。To sum up, the present invention provides two clock signals of different frequencies as the working basis of the programming circuit in the system. Wherein, in the process of detecting whether to start the programmed action in the system, the first clock signal with a lower frequency can be used as the basis for the operation. In the process of executing the programmed action in the system, the second clock signal with a relatively high frequency is used as the basis for the work. In this way, on the premise of not reducing the efficiency of the programmed operation in the system, the power consumption required by the programmed circuit in the system can be effectively reduced, and the effect of energy saving and carbon reduction can be achieved.

100、200、410：系統內程式化電路 110、210：動作啟動器 120、220：命令產生器 230：邏輯電路 300：動作啟動器 310：同步電路 320：資料緩衝器 330：比較器 400：積體電路 420、430：時脈產生器 440：記憶體裝置 441：記憶體控制器 442：記憶體 AN1：及閘 CK1：第一時脈信號 CK2：第二時脈信號 CMD：系統內程式化命令 EN：啟動信號 EXIT：終止信號 INV1：反向器 IS：輸入信號 KEY：目標資料 SD1：第一輸入資料 SYNIS：同步後輸入信號 100, 200, 410: Programmable circuits within the system 110, 210: Action Launcher 120, 220: command generator 230: Logic Circuits 300: Action Launcher 310: Synchronization Circuit 320: data buffer 330: Comparator 400: Integrated Circuits 420, 430: clock generator 440: Memory device 441: Memory Controller 442: memory AN1: and gate CK1: the first clock signal CK2: the second clock signal CMD: Programmatic commands in the system EN: start signal EXIT: Terminate signal INV1: Inverter IS: Input signal KEY: target data SD1: first input data SYNIS: Input signal after synchronization

圖1繪示本發明一實施例的系統內程式化電路的示意圖。 圖2繪示本發明另一實施例的系統內程式化電路的示意圖。 圖3繪示本發明實施例的動作啟動器的實施方式的示意圖。 圖4繪示本發明一實施例的積體電路的示意圖。 FIG. 1 is a schematic diagram of an in-system programming circuit according to an embodiment of the present invention. FIG. 2 is a schematic diagram of an in-system programming circuit according to another embodiment of the present invention. FIG. 3 is a schematic diagram illustrating an implementation of an action initiator according to an embodiment of the present invention. FIG. 4 is a schematic diagram of an integrated circuit according to an embodiment of the present invention.

100：系統內程式化電路 110：動作啟動器 120：命令產生器 CK1：第一時脈信號 CK2：第二時脈信號 CMD：系統內程式化命令 EN：啟動信號 EXIT：終止信號 IS：輸入信號 100: Programmable circuits in the system 110: Action Launcher 120: Command Generator CK1: the first clock signal CK2: the second clock signal CMD: Programmatic commands in the system EN: start signal EXIT: Terminate signal IS: Input signal

Claims (10)

一種系統內程式化電路，包括： 一動作啟動器，依據一第一時脈信號以接收一輸入信號來獲得一第一輸入資料，依據比較該第一輸入資料以及一目標資料來致能一啟動信號；以及 一命令產生器，在該啟動信號被致能時，依據一第二時脈信號以接收該輸入信號來獲得一第二輸入資料，依據解碼該第二輸入資料以獲得一系統內程式化命令， 其中該命令產生器提供該系統內程式化命令至一記憶體裝置以使該記憶體裝置執行一存取動作，該第一時脈信號的頻率低於該第二時脈信號的頻率。 An in-system programmed circuit comprising: an action initiator, receiving an input signal according to a first clock signal to obtain a first input data, and enabling an activation signal according to comparing the first input data and a target data; and a command generator, when the enable signal is enabled, receives the input signal according to a second clock signal to obtain a second input data, and obtains an in-system programmed command according to decoding the second input data, Wherein the command generator provides the in-system programming command to a memory device to make the memory device perform an access operation, and the frequency of the first clock signal is lower than the frequency of the second clock signal. 如請求項1所述的系統內程式化電路，更包括： 一邏輯電路，耦接在該動作啟動器接收該第一時脈信號的路徑間，在該啟動信號被致能時，該邏輯電路遮斷該輸入信號，並使該動作啟動器停止接收該輸入信號。 The in-system programmed circuit of claim 1, further comprising: a logic circuit, coupled between the paths of the motion starter receiving the first clock signal, when the start signal is enabled, the logic circuit blocks the input signal and makes the motion starter stop receiving the input Signal. 如請求項1所述的系統內程式化電路，其中該命令產生器並依據該第二輸入資料以產生一終止信號，該動作啟動器並接收該終止信號並依據該終止信號以使該啟動信號為禁能的狀態。The in-system programming circuit of claim 1, wherein the command generator generates a termination signal according to the second input data, and the action initiator receives the termination signal and activates the activation signal according to the termination signal for the disabled state. 如請求項3所述的系統內程式化電路，其中該動作啟動器包括： 一資料緩衝器，依據該第一時脈信號以接收一同步輸入信號來獲得該第一輸入資料； 一比較器，比較該第一資料以及預設的該目標資料以產生該啟動信號；以及 一同步電路，依據該第一時脈信號以調整該輸入信號的相位來產生該同步輸入信號。 The in-system programmed circuitry of claim 3, wherein the action initiator comprises: a data buffer for receiving a synchronous input signal according to the first clock signal to obtain the first input data; a comparator that compares the first data with the preset target data to generate the enable signal; and A synchronizing circuit generates the synchronizing input signal by adjusting the phase of the input signal according to the first clock signal. 如請求項4所述的系統內程式化電路，其中該比較器更依據該終止信號以使該啟動信號為禁能的狀態。The in-system programming circuit as claimed in claim 4, wherein the comparator further makes the enable signal a disabled state according to the stop signal. 一種積體電路，包括： 一第一時脈產生器，產生第一時脈信號； 一第二時脈產生器，依據一啟動信號來產生一第二時脈信號，其中該第二時脈信號的頻率高於該第一時脈信號的頻率； 一記憶體裝置；以及 一系統內程式化電路，包括： 一動作啟動器，依據該第一時脈信號以接收一輸入信號來獲得一第一輸入資料，依據比較該第一輸入資料以及一目標資料來致能該啟動信號；以及 一命令產生器，在該啟動信號被致能時，依據該第二時脈信號以接收該輸入信號來獲得一第二輸入資料，依據解碼該第二輸入資料以獲得一系統內程式化命令， 其中該命令產生器提供該系統內程式化命令至該記憶體裝置以使該記憶體裝置執行一存取動作。 An integrated circuit comprising: a first clock generator to generate a first clock signal; a second clock generator for generating a second clock signal according to a start signal, wherein the frequency of the second clock signal is higher than the frequency of the first clock signal; a memory device; and An in-system programmed circuit comprising: an action initiator, receiving an input signal according to the first clock signal to obtain a first input data, and enabling the activation signal according to comparing the first input data and a target data; and a command generator, when the enable signal is enabled, receives the input signal according to the second clock signal to obtain a second input data, and obtains an in-system programmed command according to decoding the second input data, Wherein the command generator provides the in-system programmed command to the memory device to make the memory device perform an access operation. 如請求項6所述的積體電路，其中在該啟動信號被禁能時，該第二時脈產生器停止產生該第二時脈信號，在該啟動信號被致能時，該第二時脈產生器產生該第二時脈信號。The integrated circuit of claim 6, wherein when the enable signal is disabled, the second clock generator stops generating the second clock signal, and when the enable signal is enabled, the second clock The pulse generator generates the second clock signal. 如請求項6所述的積體電路，其中該系統內程式化電路更包括： 一邏輯電路，耦接至該動作啟動器，該邏輯電路在該啟動信號被致能時，使該動作啟動器停止接收該輸入信號。 The integrated circuit of claim 6, wherein the in-system programmed circuit further comprises: A logic circuit is coupled to the action initiator, and when the activation signal is enabled, the logic circuit makes the action initiator stop receiving the input signal. 如請求項6所述的積體電路，其中該命令產生器並依據該第二輸入資料以產生一終止信號，該動作啟動器並接收該終止信號並依據該終止信號以使該啟動信號為禁能的狀態。The integrated circuit of claim 6, wherein the command generator generates a termination signal according to the second input data, and the action initiator receives the termination signal and disables the activation signal according to the termination signal able state. 如請求項9所述的積體電路，其中該動作啟動器包括： 一資料緩衝器，依據該第一時脈信號以接收一同步輸入信號來獲得該第一輸入資料；以及 一比較器，比較該第一資料以及預設的該目標資料以產生該啟動信號，該比較器更依據該終止信號以使該啟動信號為禁能的狀態； 一同步電路，依據該第一時脈信號以調整該輸入信號的相位來產生該同步輸入信號。 The integrated circuit of claim 9, wherein the action initiator comprises: a data buffer for receiving a synchronous input signal according to the first clock signal to obtain the first input data; and a comparator that compares the first data with the preset target data to generate the enable signal, and the comparator further makes the enable signal a disabled state according to the stop signal; A synchronizing circuit generates the synchronizing input signal by adjusting the phase of the input signal according to the first clock signal.
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