TWI768391B - Hemt layout - Google Patents

Abstract

An HEMT layout includes a substrate. A mesa is disposed on the substrate. The mesa includes a first III-V compound layer and a second III-V compound layer. The second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different. A third III-V compound layer is disposed on the meas. The third III-V compound layer forms a first hollow rectangle. A first source/drain pad is disposed on the mesa and is surrounded by the first hollow rectangle. A second source/drain pad is disposed on the mesa and is outside of the first hollow rectangle.

Description

Layout of High Electron Mobility Transistors

The present invention relates to a layout diagram of a high electron mobility transistor, especially a layout diagram that can avoid source/drain leakage.

III-V semiconductor compounds can be applied to form many kinds of integrated circuit devices due to their semiconducting properties, such as high power field effect transistors, high frequency transistors or high electron mobility transistors (HEMTs) . In high electron mobility transistors, two semiconductor materials with different band-gap are combined to form a heterojunction at a junction to provide a channel for carriers. In recent years, GaN series materials are suitable for high power and high frequency products due to their wide energy gap and high saturation rate. The high electron mobility transistor of the gallium nitride series generates a two-dimensional electron gas (2DEG) by the piezoelectric effect of the material itself. Compared with the traditional transistor, the electron speed of the high electron mobility transistor and the The density is high, so it can be used to increase the switching speed.

High electron mobility transistors are generally divided into normally-on and normally-off types. However, normally-off high electron mobility transistors often have source/drain leakage problems. That is to say, when the high electron mobility transistor is required to be turned off, a current will flow to the source or drain instead.

In view of this, the present invention provides a layout diagram of a high electron mobility transistor to solve the leakage problem.

According to a preferred embodiment of the present invention, a layout diagram of a high electron mobility transistor includes a substrate, and a platform is disposed on the substrate, wherein the platform includes a first III-V group compound layer and a second III-V compound layer. group compound layer, the second group III-V compound is disposed on the first group III-V compound layer, the composition of the second group III-V compound layer is different from that of the first group III-V compound layer, a third group III-V compound layer is The group compound layer is disposed on the platform, wherein the third III-V group compound layer forms a first hollow rectangle, a first source/drain contact pad is disposed on the platform and is surrounded by the first hollow rectangle and a second source The /drain contact pads are disposed on the platform and outside the first hollow rectangle.

According to a preferred embodiment of the present invention, a layout diagram of a high electron mobility transistor includes: a substrate, a platform disposed on the substrate, wherein the platform includes a first III-V group compound layer and a second III- Group V compound layer, the second group III-V compound layer is disposed on the first group III-V compound layer, the composition of the second group III-V compound layer is different from that of the first group III-V compound layer, a third group III compound layer - The group V compound layer is disposed on the platform, wherein the cross section of the platform not covered by the third group III-V compound layer includes a stepped profile.

In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the preferred embodiments are exemplified below, and are described in detail as follows in conjunction with the accompanying drawings. However, the following preferred embodiments and drawings are only for reference and description, and are not intended to limit the present invention.

10: Base

12: Platform

14: The first III-V compound layer

16: Second III-V compound layer

18: The third III-V compound layer

20: First hollow rectangle

20': Second hollow rectangle

20a: wide side

20b: Narrow side

22: First source/drain contact pad

22a: Long side

24: Second source/drain contact pad

26: Protective layer

28: First trapezoid

30: First hypotenuse

32: First upper surface

34: First lower surface

36: Second trapezoid

38: Second hypotenuse

40: Second upper surface

42: Second lower surface

44: Step Profile

100: Layout of a high electron mobility transistor

200: Layout of a high electron mobility transistor

300: Layout of a high electron mobility transistor

K: frame line

L1: Line

L2: Line

L3: Line

L4: Line

U: direction

V: direction

W1: width

W2: width

X: direction

Y: direction

FIG. 1 is a layout diagram of a high electron mobility transistor according to a first preferred embodiment of the present invention.

Figure 2 is a side view taken along the AA' tangent in Figure 1.

Figure 3 is a side view taken along the BB' tangent in Figure 1.

Figure 4 is a side view taken along the tangent line CC' in Figure 1.

Figure 5 is a side view taken along the DD' tangent in Figure 1.

Figure 6 is a side view taken along the tangent line EE' in Figure 1.

FIG. 7 is a layout diagram of a high electron mobility transistor according to another preferred embodiment of the present invention.

FIG. 8 is a layout diagram of a high electron mobility transistor according to a second preferred embodiment of the present invention.

Fig. 9 is a side view taken along the tangent line FF' in Fig. 8.

Figure 10 is a side view taken along the GG' tangent in Figure 8.

Figure 11 is a side view taken along the tangent line HH' in Figure 8.

Figure 12 is a side view taken along the tangent line II' in Figure 8.

Figure 13 is a side view taken along the tangent line JJ' in Figure 8.

FIG. 1 is a layout diagram of a high electron mobility transistor according to a first preferred embodiment of the present invention. Figure 2 is a side view taken along the AA' tangent in Figure 1. Figure 3 is a side view taken along the BB' tangent in Figure 1. Figure 4 is a side view taken along the tangent line CC' in Figure 1. Figure 5 is a side view taken along the DD' tangent in Figure 1. Figure 6 is a side view taken along the tangent line EE' in Figure 1.

As shown in FIGS. 1 to 6, a layout diagram 100 of a high electron mobility transistor includes a substrate 10, and the substrate 10 may include a silicon substrate and an epitaxial buffer layer. A platform 12 is disposed on the substrate 10. The platform 12 includes a first III-V group compound layer 14 and a second III-V group compound layer 16. The second III-V group compound layer 16 is disposed on the first III-V group compound layer. On the group compound layer 14, the composition of the second group III-V compound layer 16 is different from that of the first group III-V compound layer 14, and a third group III-V compound layer 18 is disposed on the platform 12, wherein the third group III-V compound layer 18 The group compound layer 18 forms a first hollow rectangle 20, a first source/drain contact pad 22 is disposed on the platform 12 and is surrounded by the first hollow rectangle 20, and a second source/drain contact pad 24 is disposed on the platform 12. flat On mesa 12 and outside of first hollow rectangle 20, a protective layer 26 covers third III-V compound layer 18, mesa 12 and substrate 10, but the first source/drain contact pads 22 and the second source The pole/drain contact pads 24 are exposed from the protective layer 26 , and the protective layer 26 in the first figure is omitted for clarity of illustration. As shown in FIG. 1, the first hollow rectangle 20 includes two broad sides 20a and two narrow sides 20b. The wide side 20a of the first hollow rectangle 20 is used as a gate, and a gate electrode (not shown in the figure) can be set later. ) on the broadside 20a.

According to a preferred embodiment of the present invention, the first source/drain contact pad 22 is a source contact pad, and the second source/drain contact pad 24 is a drain contact pad. As shown in FIG. 1 , since the second source/drain contact pad 24 is outside the first hollow rectangle 20 , it can extend beyond the platform 12 in the Y direction, wherein the Y direction is parallel to the upper surface of the substrate 10 The surface and the direction perpendicular to the two narrow sides 20b, the X direction is the direction perpendicular to the upper surface of the substrate 10 .

A two-dimensional electron gas is naturally formed between the first III-V compound layer 14 and the second III-V compound layer 16 , but where the third III-V compound layer 18 covers, the two-dimensional electron gas cannot be formed, so a normally-off high electron mobility transistor can be formed by stacking the third III-V compound layer 18 on the platform 12, that is, the transistor presented in the present invention . Please refer to FIG. 5, the cross section of the platform 12 along the X direction is a first trapezoid 28, the first trapezoid 28 includes a first hypotenuse 30, a first upper surface 32 and a first lower surface 34, the first upper The width of the surface 32 is smaller than the width of the first lower surface 34, the first hypotenuse 30 is inclined toward the outside of the platform 12 in the direction from the first upper surface 32 to the second lower surface 34, and the third III-V compound 18 layer is along the The cross section along the X direction is a second trapezoid 36, the second trapezoid 36 includes a second hypotenuse 38, a second upper surface 40 and a second lower surface 42, the width of the second upper surface 40 is smaller than that of the second lower surface 42, the second hypotenuse 38 is inclined toward the outside of the third III-V group compound layer 18 from the second upper surface 40 to the second lower surface 42, and the width of the second upper surface 40 is smaller than that of the first upper surface 32 width, the first hypotenuse 30 is connected to the second hypotenuse 38 . It is worth noting that there is almost no third III-V compound layer 18 at the end point where the first hypotenuse 30 connects to the second hypotenuse 38. For details, please refer to Fig. 4 and Fig. 5 at the same time, Fig. 4 It is a side view cut along the line L2 perpendicular to the direction of the base in Fig. 5, and Fig. 4 is also At the same time, it is a side view taken along the tangent line CC' in FIG. 1. It can be seen from FIG. 4 that there is no third III-V group compound layer 18 on the platform 12 at all, so the first oblique edge 30 is connected to the second oblique side. At the end of the edge 38, a two-dimensional electron gas will continue to be formed. Since the present invention is a normally-off high electron mobility transistor, there is a normally-on two-dimensional electron gas at the gate edge. The two-dimensional electron gas here is Electron gas can cause source leakage when normally-off high electron mobility transistors should be turned off.

Please refer to Fig. 3 and Fig. 5 at the same time, Fig. 3 is a side view cut along the line L1 perpendicular to the direction of the substrate 10 in Fig. 5, and Fig. 3 is also the side drawn along the tangent line BB' in Fig. 1 3, there is no two-dimensional electron gas on the platform 12 covered by the third III-V group compound layer 18, so it is a normally-off high electron mobility transistor with normal function.

As shown in FIG. 6, there is no two-dimensional electron gas under the third group III-V compound layer 18. Since the third group III-V compound layer 18 surrounds the first source/drain contact pad 22, the third group III-V compound layer 18 surrounds the first source/drain contact pad 22. Even if two-dimensional electron gas is formed at the end point where a hypotenuse 30 connects to the second hypotenuse 38, it will be blocked by the third III-V compound layer 18 surrounding the first source/drain contact pad 22 and will not reach the first source/drain contact pad 22. A source/drain contact pad 22 . Generally speaking, when the first source/drain contact pad 22 is a source contact pad and the second source/drain contact pad 24 is a drain contact pad, in the design of the transistor, the gate and the first The distance between a source/drain contact pad 22 is short, and leakage is more likely to occur, so a hollow rectangle is arranged around the first source/drain contact pad 22 .

The first III-V group compound layer 14 may be formed of gallium nitride (gallium nitride, GaN) or/and indium gallium nitride (In _x Ga _1-x N) and other materials, and the second III- The group V compound layer 16 can utilize aluminum gallium nitride (Al _x Ga _1-x N), aluminum indium nitride (Al _x In _1-x N), aluminum indium gallium nitride (Al Indium gallium nitride, Al _1-xy In _x Ga _y N) or/and aluminum nitride (aluminum nitride, AlN) and other materials, but not limited thereto. According to a preferred embodiment of the present invention, the first III-V compound layer 14 is gallium nitride, and the second III-V compound layer 16 is aluminum gallium nitride. The third III-V compound layer 18 includes P-type gallium nitride or P-type aluminum indium gallium nitride. The substrate 10 may include an epitaxial layer and a silicon substrate. The protective layer 26 includes silicon nitride or aluminum nitride. According to a preferred embodiment of the present invention, the thickness of the first III-V compound layer 14 is about 300 nanometers, the thickness of the second III-V compound layer 16 is about 10 nanometers, and the thickness of the third III-V compound layer 18 is about 10 nanometers. The thickness of the protective layer 26 is about 100 nm, and the thickness of the protective layer 26 is about 200 nm.

FIG. 7 is a layout diagram of a high electron mobility transistor according to another preferred embodiment of the present invention, wherein the components with the same function will use the component symbols in the first preferred embodiment, here No longer. As shown in FIG. 7 , depending on different requirements, the second source/drain contact pad 24 can also be surrounded by a second hollow rectangle 20 ′ formed by the third III-V group compound layer 18 . The length of the pole/drain contact pads 24 in the Y direction will be smaller than the length of the second source/drain contact pads 24 in the Y direction in FIG. 1, and the second hollow rectangle 20' can avoid two-dimensional The electron gas leakage current goes to the drain contact pad 24 .

FIG. 8 is a layout diagram of a high electron mobility transistor according to a second preferred embodiment of the present invention. Components with the same functions in FIGS. 8 to 13 will use the first preferred embodiment. The component symbols in the example, the types and sizes of their material layers will not be repeated here. Fig. 9 is a side view taken along the tangent line FF' in Fig. 8. Figure 10 is a side view taken along the GG' tangent in Figure 8. Figure 11 is a side view taken along the tangent line HH' in Figure 8. Figure 12 is a side view taken along the tangent line II' in Figure 8. Figure 13 is a side view taken along the tangent line JJ' in Figure 8. The main difference between the first preferred embodiment and the second preferred embodiment is that the cross section (side view) of the platform not covered by the third III-V compound layer in the second preferred embodiment includes a step outline, and the third III-V compound layer of the second preferred embodiment does not form a hollow rectangle.

As shown in FIGS. 8 to 13, a layout diagram 300 of a high electron mobility transistor includes a substrate 10 and a platform 12 disposed on the substrate 10, wherein the platform 12 includes a first III-V group compound layer 14 and a second III-V group compound layer 16, the second III-V group compound layer 16 is disposed on the first III-V group compound layer 14, and the composition of the second III-V group compound layer 16 is the same as that of the first III-V group compound layer 16. Different from the group V compound layer 14, a third group III-V compound layer 18 is disposed on the platform 12, the third group III-V compound layer 18 is used as a gate electrode, and a gate electrode (not shown in the figure) can be disposed on the on the third III-V compound layer 18 .

As shown in FIG. 13 , the mesa 12 not covered by the third III-V compound layer 18 includes a stepped profile 44 . As shown in FIG. 8 , the first source/drain contact pad 22 and the second source/drain contact pad 24 are disposed on the mesa 12 and located on both sides of the third III-V group compound layer 18 , respectively. The first source/drain contact pad 22 is preferably a source contact pad, the first source/drain contact pad 22 includes a long side 22a, and the second source/drain contact pad 24 is preferably a drain contact pad pad, a protective layer 26 covers the third III-V compound layer 18, the platform 12 and the substrate 10, the first source/drain contact pad 22 and the second source/drain contact pad 24 are exposed from the protective layer 26 In addition, for the sake of clarity of illustration, the protective layer 26 in the first figure is omitted. The V direction is defined as a direction parallel to the upper surface of the substrate 10 and parallel to the first source/drain contact pads 22 , and the U direction is defined as a direction perpendicular to the upper surface of the substrate 10 .

For the reason explained in Fig. 5 of the first preferred embodiment, the edge of the second III-V compound layer 16 under the gate electrode is not covered by the third III-V compound layer 18, so there is a The two-dimensional electron gas, however, in the second preferred embodiment, the portion of the second III-V compound layer 16 not covered by the third III-V compound layer 18 is removed, in detail, near the edge of the mesa 12 And the second III-V group compound layer 16 that is not covered by the third III-V group compound layer 18 is removed. For the position of removal, please refer to the position of the frame line K in FIG. 8, so that in the absence of the second III-V group compound layer 16 In the case of the group compound layer 16, two-dimensional electron gas cannot be generated.

Please refer to Fig. 8, Fig. 11 and Fig. 12 at the same time, Fig. 11 is a side view of Fig. 12 cut along the line L4 perpendicular to the direction of the substrate 10, Fig. 11 is also a tangent line HH' in Fig. 8 In the side view shown, it can be seen from FIG. 11 that since the third III-V compound layer 18 is not covered, the second III-V compound layer 16 here is completely removed, so there will be no two Electron gas is produced. Please refer to Figure 8, Figure 10 and Figure 12 at the same time, Figure 10 is a side view of Figure 12 taken along the line L3 perpendicular to the direction of the substrate 10, Figure 10 is also the tangent line GG' in Figure 8 In the side view shown, it can be seen from FIG. 10 that since the second III-V compound layer 16 is covered by the third III-V compound layer 18, the second III-V compound layer 16 will not be moved. In addition, the third III-V group compound layer 18 can prevent the generation of two-dimensional electron gas.

Please refer to Fig. 8 and Fig. 13 at the same time, since the position of tangent JJ' is not by the third group III-V The compound layer 18 is covered, so the second III-V group compound layer 16 within the range of the frame line K is completely removed, and in this case, no two-dimensional electron gas is generated within the range of the frame line K. In this way, leakage of the two-dimensional electron gas to the first source/drain contact pad or the second source/drain contact pad can be avoided.

In addition, as shown in FIG. 13, the step profile 44 is composed of the first III-V group compound layer 14 and the second III-V group compound layer 16. In the V direction, the first III-V group compound layer 14 is The width W1 is 1.010 times or more the width W2 of the second group III-V compound layer 16 . For example, when the width W1 of the first group III-V compound layer 14 is 10 micrometers, the width W2 of the second group III-V compound layer 16 is about 9.9 micrometers, that is to say, the second group III-V compound layer has a width W2 of about 9.9 micrometers. Both ends of 16 were removed by 50 nm each.

As shown in FIG. 1 to FIG. 6 , the method of fabricating the layout diagram 100 of the high electron mobility transistor in the first preferred embodiment of the present invention includes providing a substrate 10 and then forming a first III-V in sequence A group compound layer 14, a second group III-V compound layer 16 and a third group III-V compound layer 18 cover the substrate 10, and then the first group III-V compound layer 14 and the second group III-V compound layer 14 are patterned layer 16 and third III-V compound layer 18, wherein the patterned first III-V compound layer 14 and the patterned second III-V compound layer 16 constitute a platform 12, after the platform is formed , patterning the third III-V compound layer 18 to form a first hollow rectangle 20, then forming a protective layer 26 to cover the platform 12, the substrate 10 and the first hollow rectangle 20, and finally forming a first source/drain at the same time The contact pads 2 and the second source/drain contact pads 24 are on the platform 12 and penetrate the protective layer 26 , wherein the first source/drain contact pads 22 are located within the first hollow rectangle 20 .

The manufacturing method of the layout diagram 300 of the high electron mobility transistor in the second preferred embodiment of the present invention includes providing a substrate 10' and then forming a first III-V group compound layer 14 and a second III-V compound layer in sequence A group compound layer 16 and a third group III-V compound layer 18 cover the substrate 10, followed by patterning the first group III-V compound layer 14, the second group III-V compound layer 16 and the third group III-V compound layer 18, wherein the patterned first III-V group compound layer 14 and the patterned second III-V group compound layer 16 constitute a platform 12, and after the platform 12 is formed, the third III-V group compound is patterned layer 18 to form a gate, then perform a removal process to remove part of the second II-V compound layer 16 not covered by the gate, and then form a protection The layer 26 covers the platform 12 , the substrate 10 and the gate, and finally the first source/drain contact pad 22 and the second source/drain contact pad 14 are simultaneously formed on the platform 12 and penetrate the protective layer 26 .

The first preferred embodiment of the present invention utilizes the hollow rectangle formed by the third III-V compound layer to surround the first source/drain contact pads to avoid the leakage of the two-dimensional electron gas toward the source; the second preferred embodiment Then, the second II-V group compound layer not covered by the third III-V group compound layer is removed, so that the two-dimensional electron gas cannot be formed near the edge of the platform, so as to prevent the two-dimensional electron gas from leaking toward the source electrode.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

10: Base

12: Platform

20: First hollow rectangle

20a: wide side

20b: Narrow side

22: First source/drain contact pad

24: Second source/drain contact pad

100: Layout of a high electron mobility transistor

X: direction

Y: direction

Claims (11)

A layout diagram of a high electron mobility transistor, the layout diagram of the high electron mobility transistor comprising: a substrate; a platform disposed on the substrate, wherein the platform includes a first III-V group compound layer and a first Two III-V compound layers, the second III-V compound is disposed on the first III-V compound layer, and the composition of the second III-V compound layer is the same as that of the first III-V compound layer different; a third III-V compound layer is disposed on the platform, wherein the third III-V compound layer forms a first hollow rectangle; a first source/drain contact pad is disposed on the platform and is The first hollow rectangle surrounds; and a second source/drain contact pad is disposed on the platform and outside the first hollow rectangle. The layout diagram of the high electron mobility transistor according to claim 1, wherein the cross section of the platform is a first trapezoid, and the first trapezoid includes a first hypotenuse, a first upper surface and a first trapezoid. A lower surface, the width of the first upper surface is smaller than the width of the first lower surface, and the first oblique edge is inclined toward the outside of the platform from the first upper surface to the second lower surface. The layout diagram of the high electron mobility transistor as described in item 2 of the claimed scope, wherein the cross-section of the third III-V group compound layer is a second trapezoid, and the second trapezoid includes a second hypotenuse, a A second upper surface and a second lower surface, the width of the second upper surface is smaller than the width of the second lower surface, and the second oblique edge from the second upper surface to the second lower surface faces the third The outside of the III-V compound layer is inclined. The layout diagram of the high electron mobility transistor as described in claim 3, wherein The first hypotenuse is connected to the second hypotenuse. The layout diagram of the high electron mobility transistor as described in claim 1, wherein the first III-V group compound layer is gallium nitride, the second III-V group compound layer comprises aluminum gallium nitride, Aluminum Indium Nitride, Aluminum Indium Gallium Nitride, or Aluminum Nitride. The layout diagram of the high electron mobility transistor described in claim 1, wherein the third III-V group compound layer is P-type gallium nitride or p-type aluminum indium gallium nitride. The layout diagram of the high electron mobility transistor as described in claim 1, further comprising a second hollow rectangle formed by the third III-V compound layer surrounding the second source/drain contact pad. A layout diagram of a high electron mobility transistor, the layout diagram of the high electron mobility transistor comprising: a substrate; a platform disposed on the substrate, wherein the platform includes a first III-V group compound layer and a first Two III-V group compound layers, the second III-V group compound layer is disposed on the first III-V group compound layer, the composition of the second III-V group compound layer is the same as that of the first III-V group compound layer different layers; a third III-V compound layer disposed on the platform; wherein the cross section of the platform not covered by the third III-V compound layer includes a stepped profile; a first source/drain contact pad disposed on the platform and located on one side of the platform; and a second source/drain contact pad disposed on the platform and located on the other side of the platform, wherein the second III-V compound layer The width is smaller than the width of the first III-V compound layer, and a V direction is parallel to the The upper surface of the substrate, a long side of the first source/drain contact pad is parallel to the upper surface of the substrate, the V direction, the long side of the first source/drain contact pad, the first III The width of the -V group compound layer and the width of the second III-V group compound layer are parallel to each other. The layout diagram of the high electron mobility transistor as described in claim 8, wherein the step profile consists of the first III-V compound layer and the second III-V compound layer parallel to the In the direction of the upper surface of the platform, the width of the first III-V group compound layer is more than 1.010 times the width of the second III-V group compound layer. The layout diagram of the high electron mobility transistor as described in claim 8, wherein the first III-V group compound layer is gallium nitride, the second III-V group compound layer comprises aluminum gallium nitride, Aluminum Indium Nitride, Aluminum Indium Gallium Nitride, or Aluminum Nitride. The layout diagram of the high electron mobility transistor as described in claim 8, wherein the third III-V group compound layer is P-type gallium nitride or p-type aluminum indium gallium nitride.

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