TWI761846B - Data auto-transmitting method, apparatus, and storage medium thereof - Google Patents

Abstract

The present disclosure relates to a data auto-transmitting method, an apparatus, and a storage medium thereof. The method includes: a storage with storage modules receives data from a processor and acquires identification information of the data; the data corresponds to one of the storage modules the storage; the storage searches a starting address based on the identification information; the storage sets the storage module corresponding to the data as a target storage module, and sets a target control module corresponding to the data; a pointer of the target control module transmits the data from the starting address; the storage tums off an outputting function of the storage when an interrupt command is received and the current pointer points to an end address, thus a transmitting speed of the data is improved based on the auto-acquiring operation of starting address and the determining operation of the interrupt command.

Description

Automatic data transmission method, device and storage medium

The present invention relates to an automatic data transmission method, device and storage medium.

With the development of communication technology, the amount of data generated in terminal equipment becomes increasingly huge. A terminal device usually includes a central processing unit (CPU), a dynamic random access memory (DRAM), a static random access memory (SRAM), and other functional modules. The data generated in the terminal device usually needs to be temporarily stored in the memory and sent to the corresponding functional module after some processing, so that the corresponding functional module can receive the required data. In the prior art, the CPU needs to first read out the target data from the DRAM and analyze the data to determine the transmission sequence. The above process takes a long time, and takes up the time of the CPU to process other instructions, so that the rapid response of the data during the transmission process cannot be achieved.

The main purpose of the present invention is to provide an automatic data transmission method, device and storage medium, aiming at solving the problem that the prior art cannot realize the quick response in the transmission process.

An automatic data transmission method is applied to a memory that communicates with a processor; the memory includes a first storage module and a second storage module; the automatic data transmission method includes: When the receiving instruction is detected, the memory receives the data transmitted by the processor and obtains the identification information of the data; wherein, the data is one of the first storage module and the second storage module. as a default storage module; the identification information is used to identify whether the data has a specified starting address in the target memory; when a query command is detected, the memory queries the The starting address corresponding to the data; when the setting instruction is detected, the preset storage module corresponding to the data is set as the target storage module, and the target control module is set according to the predetermined operation corresponding to the data; in When detecting the transmission command, control the pointer of the target control module to start from the starting address to transmit the multi-segment data segments corresponding to the data; when detecting the detection command, determine whether an interrupt command is received When receiving the interrupt instruction, judge whether the address corresponding to the current pointer is the last address; when the address corresponding to the current pointer is the last address, close the output function of the memory .

Preferably, the identification information includes a preset identification ID and a designated identification ID; the step of querying the starting address and target memory corresponding to the data according to the identification information includes: judging whether the identification information is the preset identification information. Set the identification ID; when the identification information is not the preset identification ID, obtain the designated address corresponding to the designated identification ID as the starting address; when the identification information is the preset identification ID, A preset address corresponding to the preset identifier ID is acquired as a starting address.

Preferably, the preset address corresponding to the preset identifier ID is 468, and the designated address corresponding to the designated identifier ID is 476.

Preferably, the step of setting a preset storage module corresponding to the data as a target storage module, and setting a target control module according to a predetermined operation corresponding to the data comprises: setting the preset storage module corresponding to the data Set the storage module as the target storage module; determine whether the predetermined operation information is a read operation; when the predetermined operation information is a read operation, set the read control module in the memory as the target control module group; when the predetermined operation information is a write operation, set the write control module in the memory as the target control module.

Preferably, after the interrupt instruction is not received and the target control module completes the transmission from the starting point to the last address, the target control module returns to the starting address of the target storage module to continue the process. The transmission of the corresponding multi-segment data segment.

In addition, in order to achieve the above object, the present invention also provides an automatic data transmission device, the automatic data transmission device includes: a processor; a memory, which receives the data output by the processor, and includes a first storage module and a second storage module a storage module; the memory includes: a receiving module for receiving the data transmitted by the processor and acquiring the identification information of the data when a receiving instruction is detected; wherein, the data converts the first One of a storage module and the second storage module is used as a default storage module; the identification information is used to identify whether the data has a specified starting address in the target memory; identification detection module group, used for the memory to query the starting address corresponding to the data according to the identification information when the query command is detected; The receiving module is further configured to set the preset storage module corresponding to the data as a target storage module when a setting instruction is detected, and set a target control module according to a predetermined operation corresponding to the data The receiving module further controls the pointer of the target control module to transmit the corresponding multi-segment data segments from the starting address when the transmission instruction is detected; the receiving module is further When the detection command is detected, it is judged whether the interrupt command is received; the last address detection module is used to judge whether the address corresponding to the current pointer is the last address when the interrupt command is received; When the address corresponding to the pointer is the last address, the last address detection module turns off the output function of the memory.

Preferably, the identification detection module further determines whether the identification information is the preset identification ID; when the identification information is not the preset identification ID, the identification detection module further obtains and The designated address corresponding to the designated identification ID is used as the starting address; when the identification information is the preset identification ID, the identification detection module further obtains the preset position corresponding to the preset identification ID. address as the starting address.

Preferably, the preset address corresponding to the preset identifier ID is 468, and the designated address corresponding to the designated identifier ID is 476.

Preferably, the receiving module further sets the preset storage module corresponding to the data as a target storage module and determines whether the predetermined operation information is a read operation; if the predetermined operation information is a read operation During the fetch operation, the receiving module further sets the read control module as the target control module; when the predetermined operation information is the write operation, the receiving module further sets the write control module as the target control module.

In addition, in order to achieve the above object, the present invention also proposes a storage medium, the storage medium is a computer-readable storage medium, and stores at least one instruction. When the at least one instruction is executed by the processor, the following steps are implemented: when detecting When receiving the instruction, the memory receives the data transmitted by the processor and obtains the identification information of the data; wherein, the data uses one of the first storage module and the second storage module as a default storage module; The identification information is used to identify whether the data has a specified starting address in the target memory; when a query instruction is detected, the memory queries the starting address corresponding to the data according to the identification information; When the setting instruction is detected, the preset storage module corresponding to the data is set as the target storage module, and the target control module is set according to the predetermined operation corresponding to the data; when the transmission instruction is detected, control The pointer of the target control module starts to transmit the multi-segment data segments corresponding to the data from the starting point; when a detection command is detected, it is judged whether an interrupt command is received; when an interrupt command is received, it is judged that the current whether the address corresponding to the pointer is the last address; when the current address corresponding to the pointer is the last address, the output function of the memory is turned off.

In the above-mentioned automatic data transmission method, device and storage medium, the memory can automatically determine the starting address of the data and the transmission operation according to the input data or instructions, which reduces the occupation of the processor for the data transmission, thereby improving the memory during the data transmission process. The response speed of the body; and when the interrupt command is detected, the last bit address is further detected to ensure the integrity of the data during the data transmission process.

100: Automatic data transmission device

10: Processor

20: Memory

30: Communication bus

201: Receive module

202: Identification detection module

203: Write control module

204: Read control module

205: The first storage module

206: Second storage module

207: Last bit address detection module

208: The first cache module

209: Second cache module

210: Output control module

211: Output module

S10-S16: Steps

FIG. 1 is a schematic diagram of an automatic data transmission method of the present invention.

FIG. 2 is a schematic diagram of the refinement flow of step S11 in FIG. 1 .

FIG. 3 is a schematic diagram of the refinement flow of step S12 in FIG. 1 .

FIG. 4 is a functional module diagram of the data transmission device of the present invention.

In order to make those skilled in the art better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only Embodiments are part of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

The terms "first", "second" and "third" in the description of the present invention and the above-mentioned drawings are used to distinguish different items, rather than to describe a specific order. Furthermore, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or modules is not limited to the listed steps or modules, but may optionally also include unlisted steps or modules, or alternatively It also includes other steps or modules inherent to these processes, methods, products or devices.

The specific embodiments of the automatic data transmission method of the present invention will be described below with reference to the accompanying drawings.

In at least one embodiment of the present invention, the automatic data transmission method is applied to a data transmission system. The data transmission system includes a processor 10 (see FIG. 4 ) and at least one memory 20 (see FIG. 4 ). The data transmission system provides a visual interface. The visual interface is used to provide the user with a human-computer interaction interface, and the user can connect to the data transmission system through electronic equipment such as a mobile phone or a computer. The automatic data transmission method is used for the memory 20 to automatically perform transmission and interruption detection according to the data of the processor 10 .

The processor 10 may include one or more microprocessors, digital processors. The processor 10 can call the program codes stored in the memory 20 to execute related functions. For example, each module described in FIG. 4 is a program code stored in the memory 20 and executed by the processor 10 to implement an automatic data transmission method. The processor 10, also known as a central processing unit (CPU, Central Processing Unit), is an ultra-large-scale integrated circuit, and is a computing core (Core) and a control core (Control Unit).

The memory 20 is used for storing data and program codes. The memory 20 may be a circuit with a storage function that does not have a physical form in an integrated circuit, or the memory 20 may also be a memory with a physical form, such as a memory stick, a TF card (Trans-flash Card). ), smart media card (smart media card), secure digital card (secure digital card), flash memory card (flash card) and other storage devices. The memory 20 can communicate data with the processor 10 through the communication bus 30 . The memory 20 may include an operating system, a network communication module and a data transfer program. The operating system is a program that manages and controls the hardware and software resources of the data transfer device 100, and supports the operation of the data transfer program and other software and/or programs. The network communication module is used to realize the communication between the various components in the memory 20 and communicate with other hardware and software in the electronic device 100 .

Please refer to FIG. 1 , which is a flowchart of an automatic data transmission method.

S10. When the receiving instruction is detected, the memory receives the data transmitted by the processor and obtains the identification information of the data.

In at least one embodiment of the present invention, the data includes multiple pieces of information, predetermined storage module information, predetermined operation instruction information, and identification information. Wherein, the predetermined storage module information and the operation instruction information may be designated by symbols designated by the user's custom settings. In at least one embodiment of the present invention, the attribute information is a combination of digits and symbols. For example, the attribute information may be 0×2, wherein “0” indicates that the first storage module 205 is a predetermined storage module group, "2" indicates that the read operation is a predetermined operation command. The identification information is used to identify whether the data has a specified start address in the target storage module. The identification information is a positive integer. The identification information includes a preset identification ID and a designated identification ID. Wherein, the preset identification ID is used to indicate that the data corresponds to a preset starting address; the specified identification ID is used to indicate that the data corresponds to a designated starting address. In at least one embodiment of the present invention, the preset identification ID is 0, and the specified identification ID may be 1, 2, or 3 digits. The first storage module 205 and the second storage module 206 may store a list of preset identification IDs, designated identification IDs, preset starting addresses, and corresponding relationships among designated starting addresses.

S11. When a query command is detected, the memory queries the starting address corresponding to the data according to the identification information.

Please also refer to FIG. 2. In at least one embodiment of the present invention, the step of querying the memory for the starting address corresponding to the data according to the identification information includes: S110, judging whether the identification information is the preset address. Set an identification ID; S111, when the identification information is not the default identification ID, obtain a designated address corresponding to the designated identification ID as a starting address; S112, when the identification information is the default identification ID When identifying the ID, the preset address corresponding to the preset identification ID is obtained as the starting address.

In at least one embodiment of the present invention, the preset address corresponding to the preset identifier ID is 468, and the designated address corresponding to the designated identifier ID is 476.

S12. When a setting instruction is detected, set the preset storage module corresponding to the data as a target storage module, and set a target control module according to a predetermined operation corresponding to the data.

Please also refer to FIG. 3. In at least one embodiment of the present invention, the preset storage module corresponding to the data is set as the target storage module, and the target control is set according to the predetermined operation corresponding to the data The steps of the mod include: S121. Set the default storage module corresponding to the data as a target storage module; S122. Determine whether the predetermined operation information is a read operation; S123. When the predetermined operation information is a read operation, Set the read control module in the memory as the target control module; S124, when the predetermined operation information is a write operation, set the write control module in the memory as the target control module.

S13. When a transfer instruction is detected, control the pointer of the target control module to transfer the multi-segment data segments corresponding to the data from the start address.

In at least one embodiment of the present invention, the memory 20 further includes a first cache module corresponding to the first storage module 205 and a second cache module corresponding to the second storage module 206 . When the operation information is a read operation, the transmission operation is that the read control module starts to transmit the data corresponding to the target storage module to the first cache module from the starting point. When the operation information is a write operation, the transfer operation is for the write control module to start the data from the processor 10 from the start address in the target storage module storage.

S14, when the detection instruction is detected, determine whether an interrupt instruction is received.

S15. When receiving the interrupt instruction, determine whether the address corresponding to the current pointer is the last address.

S16 , when the address corresponding to the current pointer is the last address, turn off the output function of the memory 20 .

When the interrupt command is not received, the process returns to step S13.

In at least one embodiment of the present invention, after the interrupt instruction is not received and the target control module completes the transfer from the start to the end address, the target control module returns to the start of the target storage module The address continues to transmit the corresponding multi-segment data segment.

In at least one embodiment of the present invention, the output function of the memory 20 is turned off by controlling the output module 211 (see FIG. 4 ) of the memory 20 to turn off.

When the address corresponding to the current pointer is not the last address, return to step S14.

In at least one embodiment of the present invention, after the interrupt instruction is not received and the target control module completes the transmission from the starting point to the last bit address, the target control module returns to the first bit of the target storage module The address continues to transmit the corresponding multi-segment data segment.

In at least one embodiment of the present invention, all the above-mentioned instructions may be data request instructions received by an electronic device. The electronic device may include a keyboard, a touch screen, etc., but the user input method in the exemplary embodiment of the present disclosure is not limited thereto, and may be generated by a user through a specific operation on a visual interface. Specifically, the user's operation includes, but is not limited to, a sliding operation, a click operation (eg, a single-click operation, a double-click operation, etc.). Specifically, the preset button may be a physical button on the electronic device, or a virtual button on the electronic device, etc. (for example, the virtual button may be a button on the display of the electronic device. virtual diagrams, etc.), the present invention is not limited herein.

In the above-mentioned automatic data transmission method, the memory 20 can automatically determine the starting address of the data and the transmission operation according to the input data or instructions, which reduces the occupation of the processor 10 for data transmission, and further improves the memory 20 during the data transmission process. response speed; and further detect the last bit address when the interrupt command is detected to ensure the integrity of the data during the data transmission process.

Referring to FIG. 4 , the present invention provides an automatic data transmission device 100 including a processor 10 , a memory 20 and a communication bus 30 .

The processor 10 may include one or more microprocessors, digital word processors. The processor 10 can call the program codes stored in the memory 20 to execute related functions. For example, each module described in FIG. 4 is a program code stored in the memory 20 and executed by the processor 10 to implement an automatic data transmission method. The processor 10 is also called the central The CPU (Central Processing Unit) is a large-scale integrated circuit, which is the computing core (Core) and the control core (Control Unit).

The memory 20 is used for storing data and program codes. The memory 20 may be a circuit with a storage function that does not have a physical form in an integrated circuit, or the memory 20 may also be a memory with a physical form, such as a memory stick, a TF card (Trans-flash Card). ), smart media card (smart media card), secure digital card (secure digital card), flash memory card (flash card) and other storage devices. The memory 20 can communicate data with the processor 10 through the communication bus 30 . The memory 20 may include an operating system, a network communication module and a data transfer program. The operating system is a program that manages and controls the hardware and software resources of the data transfer device 100, and supports the operation of the data transfer program and other software and/or programs. The network communication module is used to realize the communication between various components in the memory 20 and communicate with other hardware and software in the data transmission device 100 . In at least one embodiment of the present invention, the memory 20 includes a first storage module 205 and a second storage module 206 .

In one embodiment of the present invention, the memory 20 includes: a receiving module 201, configured to receive the data transmitted by the processor 10 and obtain the identification information of the data when a receiving command is detected.

In at least one embodiment of the present invention, the data includes multiple pieces of information, predetermined storage module information, predetermined operation instruction information, and identification information. Wherein, the predetermined storage module information and the operation instruction information may be designated by symbols designated by the user's custom settings. In at least one embodiment of the present invention, the attribute information is a combination of digits and symbols. For example, the attribute information may be 0×2, wherein “0” indicates that the first storage module 205 is a predetermined storage module, and “2” indicates that the read operation is a predetermined operation command. The identification information is used to identify whether the data has a specified start address in the target storage module. The identification information is a positive integer. The identification information includes a preset identification ID and a designated identification ID. Wherein, the preset identification ID is used for the table Indicates that the data corresponds to a preset start address; the designated identifier ID is used to indicate that the data corresponds to a designated start address. In at least one embodiment of the present invention, the preset identification ID is 0, and the specified identification ID may be 1, 2, or 3 digits. The first storage module 205 and the second storage module 206 may store a list of preset identification IDs, designated identification IDs, preset starting addresses, and corresponding relationships among designated starting addresses.

The identification detection module 202 is used for inquiring the memory according to the identification information for the starting address corresponding to the data when the inquiry command is detected.

Please also refer to FIG. 2. In at least one embodiment of the present invention, the identification detection module 202 further determines whether the identification information is the default identification ID. When the identification information is not the default identification ID, the identification detection module 202 further acquires a designated address corresponding to the designated identification ID as a starting address. When the identification information is the preset identification ID, the identification detection module 202 further acquires a preset address corresponding to the preset identification ID as a starting address.

In at least one embodiment of the present invention, the preset address corresponding to the preset identifier ID is 468, and the designated address corresponding to the designated identifier ID is 476.

The receiving module 201 is further configured to set the default storage module corresponding to the data as a target storage module when a setting instruction is detected, and set a target control module according to a predetermined operation corresponding to the data. Group. The receiving module 201 further sets the default storage module corresponding to the data as a target storage module and determines whether the predetermined operation information is a read operation. When the predetermined operation information is a reading operation, the receiving module 201 further sets the reading control module 204 as a target control module. When the predetermined operation information is a writing operation, the receiving module 201 further sets the writing control module 203 as a target control module.

The receiving module 201 further controls the pointer of the target control module to transmit the multi-segment data segments corresponding to the data from the starting address when detecting the transmission instruction.

In at least one embodiment of the present invention, the memory 20 further includes a first cache module 208 corresponding to the first storage module 205 and a second cache module corresponding to the second storage module 206 Group 209. When the predetermined operation information is a read operation, the transmission operation is that the read control module 204 starts to transmit the data corresponding to the start address to the first cache module 208 from the start point. . When the predetermined operation information is a write operation, the transfer operation is for the write control module 203 to store the data from the processor 10 from the start address. The first cache module 208 and the second cache module 209 can be provided by the output control module 210 to the output module 211 for output.

The receiving module 201 further determines whether an interrupt command is received when the detection command is detected.

The last-bit address detection module 207 is used for determining whether the address corresponding to the current pointer is the last-bit address when the interrupt instruction is received. When the address corresponding to the current pointer is the last address, the last address detection module 207 turns off the output function of the memory 20 .

In at least one embodiment of the present invention, the output function of the memory 20 is turned off by controlling the output module 211 of the memory 20 to turn off.

In at least one embodiment of the present invention, after the interrupt instruction is not received and the target control module completes the transmission from the starting point to the last bit address, the target control module returns to the first bit of the target storage module The address continues to transmit the corresponding multi-segment data segment.

In the above-mentioned automatic data transmission device, the memory 20 can automatically determine the starting address of the data and the transmission operation according to the input data or instructions, which reduces the occupation of the processor 10 for data transmission, and further improves the memory 20 during the data transmission process. response speed; and further detect the last bit address when the interrupt command is detected to ensure the integrity of the data during the data transmission process.

The present invention also provides a storage medium. The storage medium is a computer-readable storage medium. Computer instructions are stored on the computer-readable storage medium. The computer instructions may be stored on memory 20 and, when executed by one or more processors 10, perform the following steps:

S10. When the receiving instruction is detected, the memory receives the data transmitted by the processor and obtains the identification information of the data.

In at least one embodiment of the present invention, the data includes multiple pieces of information, predetermined storage module information, predetermined operation instruction information, and identification information. Wherein, the predetermined storage module information and the operation instruction information may be designated by symbols designated by the user's custom settings. In at least one embodiment of the present invention, the attribute information is a combination of digits and symbols. For example, the attribute information may be 0×2, wherein “0” indicates that the first storage module 205 is a predetermined storage module, and “2” indicates that the read operation is a predetermined operation command. The identification information is used to identify whether the data has a specified start address in the target storage module. The identification information is a positive integer. The identification information includes a preset identification ID and a designated identification ID. Wherein, the preset identification ID is used to indicate that the data corresponds to a preset starting address; the specified identification ID is used to indicate that the data corresponds to a designated starting address. In at least one embodiment of the present invention, the preset identification ID is 0, and the specified identification ID may be 1, 2, or 3 digits. The first storage module 205 and the second storage module 206 may store a list of preset identification IDs, designated identification IDs, preset starting addresses, and corresponding relationships among designated starting addresses.

S11. When a query command is detected, the memory queries the starting address corresponding to the data according to the identification information.

Please also refer to FIG. 2. In at least one embodiment of the present invention, the step of querying the memory for the starting address and target storage module corresponding to the data according to the identification information includes: S110, determining the identification information Whether it is the preset identification ID; S111, when the identification information is not the default identification ID, obtain a designated address corresponding to the designated identification ID as a starting address; S112, when the identification information is the default identification ID, A preset address corresponding to the preset identifier ID is acquired as a starting address.

In at least one embodiment of the present invention, the preset address corresponding to the preset identifier ID is 468, and the designated address corresponding to the designated identifier ID is 476.

S12. When a setting instruction is detected, set the preset storage module corresponding to the data as a target storage module, and set a target control module according to a predetermined operation corresponding to the data.

Please also refer to FIG. 3. In at least one embodiment of the present invention, the preset storage module corresponding to the data is set as the target storage module, and the target control is set according to the predetermined operation corresponding to the data The steps of the module include: S121, setting the default storage module corresponding to the data as a target storage module; S122, judging whether the predetermined operation information is a read operation; S123, in the predetermined operation information When it is a read operation, set a read control module in the memory as a target control module; S124, when the predetermined operation information is a write operation, set a write control module in the memory as a target control module.

S13. When a transfer instruction is detected, control the pointer of the target control module to transfer the multi-segment data segments corresponding to the data from the start address.

In at least one embodiment of the present invention, the memory 20 further includes a first cache module corresponding to the first storage module 205 and a second cache module corresponding to the second storage module 206 . When the operation information is a read operation, the transmission operation is that the read control module starts to transmit the data corresponding to the target storage module to the first cache module from the starting point. When the operation information is a write operation, the transfer operation is the write control The module stores the data from the processor 10 starting from the starting address in the target storage module.

S14, when the detection instruction is detected, determine whether an interrupt instruction is received.

S15. When receiving the interrupt instruction, determine whether the address corresponding to the current pointer is the last address.

S16 , when the address corresponding to the current pointer is the last address, turn off the output function of the memory 20 .

In at least one embodiment of the present invention, the output function of the memory 20 is turned off by controlling the output module 211 (see FIG. 4 ) of the memory 20 to turn off.

When the address corresponding to the current pointer is not the last address, return to step S14.

When the interrupt command is not received, the process returns to step S13.

In at least one embodiment of the present invention, after the interrupt instruction is not received and the target control module completes the transmission from the starting point to the last bit address, the target control module returns to the first bit of the target storage module The address continues to transmit the corresponding multi-segment data segment.

In the above-mentioned automatic data transmission method, the memory can automatically determine the starting address of the data and the transmission operation according to the input data or instructions, which reduces the CPU usage of the data transmission, thereby improving the response speed of the memory during the data transmission process; and When the interrupt command is detected, the last bit address is further detected to ensure the integrity of the data during the data transmission.

It should be noted that, for the sake of simple description, the foregoing method embodiments are all expressed as a series of action combinations, but those skilled in the art should know that the present invention is not limited by the described action sequence. As in accordance with the present invention, certain steps may be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

In the several embodiments provided in this application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the device embodiments described above are only illustrative. For example, the division of the modules is only a logical function division. In actual implementation, there may be other division methods. For example, multiple modules or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented. On the other hand, the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or modules, and may be electrical or other forms.

The modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in one place, or may be distributed to multiple networks. on the road module. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution in this embodiment.

In addition, each functional module in each embodiment of the present invention may be integrated into one processor, or each module may exist physically alone, or two or more modules may be integrated into one module. The above-mentioned integrated modules can be implemented in the form of hardware, or can be implemented in the form of software function modules.

If the integrated module is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, Several instructions are included to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention.

It should also be noted that, herein, the terms "comprising", "comprising" or any other variation thereof are intended to encompass a non-exclusive inclusion such that a process including a series of elements, A method, article, or apparatus includes not only those elements, but also other elements not expressly listed, or that are inherent to such a process, method, article, or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in a process, method, article or apparatus that includes the element.

As mentioned above, the above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand: The technical solutions described in the embodiments are modified, or some technical features thereof are equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

To sum up, the present invention complies with the requirements of an invention patent, and a patent application can be filed in accordance with the law. However, the above descriptions are only the preferred embodiments of the present invention, and for those who are familiar with the techniques of this case, equivalent modifications or changes made in accordance with the creative spirit of this case should be included within the scope of the following patent application.

S10-S16: Steps

Claims (10)

An automatic data transmission method is applied to a memory that communicates with a processor; the memory includes a first storage module and a second storage module; wherein, the automatic data transmission method When instructed, the memory receives the data transmitted by the processor and obtains the identification information of the data; wherein the data is one of the first storage module and the second storage module As a default storage module; the identification information is used to identify whether the data has a specified starting address in the target memory; when a query command is detected, the memory queries the data according to the identification information The corresponding starting address; when detecting the setting instruction, the preset storage module corresponding to the data is set as the target storage module, and the target control module is set according to the predetermined operation corresponding to the data; When the transmission instruction is detected, the pointer that controls the target control module starts to transmit the multi-segment data segments corresponding to the data from the start address; when the detection instruction is detected, it is judged whether an interrupt instruction is received; When an interrupt instruction is received, it is judged whether the address corresponding to the current pointer is the last address; when the current address corresponding to the pointer is the last address, the output function of the memory is turned off. The automatic data transmission method according to claim 1, wherein the identification information includes a preset identification ID and a designated identification ID; the step of querying the starting address and target memory corresponding to the data according to the identification information includes the following steps: : determine whether the identification information is the default identification ID; when the identification information is not the default identification ID, obtain the designated address corresponding to the designated identification ID as the starting address; When the identification information is the preset identification ID, a preset address corresponding to the preset identification ID is acquired as a starting address. The automatic data transmission method according to claim 2, wherein the preset address corresponding to the preset identifier ID is 468, and the designated address corresponding to the designated identifier ID is 476. The automatic data transmission method according to claim 1, wherein the step of setting a preset storage module corresponding to the data as a target storage module, and setting a target control module according to a predetermined operation corresponding to the data Including: setting the preset storage module corresponding to the data as a target storage module; judging whether the predetermined operation information is a reading operation; when the predetermined operation information is a reading operation, setting the memory The read control module in the body is used as the target control module; when the predetermined operation information is a write operation, the write control module in the memory is set as the target control module. The automatic data transmission method according to claim 1, wherein after the target control module has not received an interrupt command and the target control module completes the transmission from the start address to the end address, the target control The module returns to the first address of the target storage module and continues to transmit the corresponding multi-segment data segment. An automatic data transmission device, wherein the automatic data transmission device comprises: a processor; a memory, for receiving data output by the processor; Receive the data transmitted by the processor and obtain the identification information of the data; wherein, the data uses one of the first storage module and the second storage module as a default storage module; the identification information Whether there is a specified start address in the target memory for identifying the data; The identification detection module is used to query the starting address corresponding to the data according to the identification information when the memory is detected when the query command is detected; the receiving module is further used to detect the setting command The preset storage module corresponding to the data is set as a target storage module, and a target control module is set according to a predetermined operation corresponding to the data; the receiving module further controls the The pointer of the target control module starts to transmit the multi-segment data segments corresponding to the data from the starting address; the receiving module further judges whether an interrupt command is received when detecting the detection command; the last bit The address detection module is used to judge whether the address corresponding to the current pointer is the last address when receiving the interrupt instruction; when the address corresponding to the current pointer is the last address, the last address The bit address detection module turns off the output function of the memory. The automatic data transmission device according to claim 6, wherein the identification information includes a preset identification ID and a designated identification ID; the identification detection module further determines whether the identification information is the preset identification ID; When the identification information is not the default identification ID, the identification detection module further acquires a designated address corresponding to the designated identification ID as a starting address; when the identification information is the default identification ID When identifying the ID, the identification detection module further acquires a preset address corresponding to the preset identification ID as a starting address. The automatic data transmission device according to claim 7, wherein the preset address corresponding to the preset identification ID is 468, and the designated address corresponding to the designated identification ID is 476. The automatic data transmission device according to claim 6, wherein the receiving module further sets the preset storage module corresponding to the data as a target storage module and determines whether the predetermined operation information is read when the predetermined operation information is a reading operation, the receiving module further sets the reading control module as the target control module; in the predetermined operation When the information is a writing operation, the receiving module further sets the writing control module as the target control module. A storage medium, wherein the storage medium is a computer-readable storage medium and stores at least one instruction, and when the at least one instruction is executed by a processor, the automatic data transmission method described in any one of request items 1 to 5 is realized .

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