TWI753541B - Chip and interface conversion device - Google Patents

Abstract

A chip and an interface conversion device are provided. The chip includes a first, a second, a third, a fourth, a fifth and a sixth pads. The first and the second pads are coupled to a first and a second SBU pins of a USB connector respectively. The fourth and the sixth pads are coupled to a first and a second pins of an AUX channel of a DP connector. When the chip is operated in a first mode, a first and a second AUX channel signals generated by the chip are delivered to the third and the fifth pads respectively, the voltage of the fourth pad is weakly pulled down and the voltage of the sixth pad is weakly pulled up. When the chip is operated in a second mode, one of the first and the second pads is connected to the fourth pad and another one is connected to the sixth pad.

Description

Chip and interface conversion device

The present invention relates to an electronic device, and more particularly, to a chip and an interface conversion device.

In the existing communication technology, the host and the device use the same transmission interface to transmit data to each other. When the transmission interface used by the host is different from the transmission interface used by the device, an interface conversion device needs to be configured between the host and the device. For example, it is assumed that the transmission interface of the host is Universal Serial Bus (hereinafter referred to as USB), and the transmission interface used by the device is DisplayPort (hereinafter referred to as DP). The interface conversion device can provide the interface conversion function to transfer data from the host's USB Type-C connector to the device's DP connector, and/or transfer data from the device's DP connector to the host's USB Type-C connector Connector.

The USB Type-C connector of the interface conversion device is connected to the USB Type-C connector of the host. When the USB Type-C connector of the host transmits signals conforming to the USB 3.1 specification, the host can operate in the DisplayPort Alternate Mode (ALT Mode, hereinafter referred to as ALT Mode) of USB Type-C, so that the output from the USB Type-C connector can be The data and auxiliary channel (AUX channel, hereinafter referred to as the AUX channel) signal conforming to the DP specification are output. When the USB Type-C connector of the host operates in ALT mode, the Side Band Use (SBU) pins of the USB Type-C connector of the host are used to transmit AUX channel signals that conform to the DP specification. When the host's USB Type-C connector transmits signals conforming to the USB 4.0 specification, the SBU pin of the host's USB Type-C connector is used to transmit sideband signals conforming to the USB standard.

Regardless of whether the host's USB Type-C connector operates in the ALT mode of USB or operates in USB 4.0, the interface conversion device must be capable of processing the signals of the host's USB Type-C connector. The DP connector of the interface conversion device is connected to the DP connector of the device. Regardless of whether the signal transmitted by the SBU pin of the USB Type-C connector of the host to the interface conversion device is an AUX channel signal conforming to the DP specification or a sideband signal conforming to the USB specification, the AUX channel pin of the DP connector of the interface conversion device needs to be Complies with DP specifications.

It should be noted that the content of the "prior art" paragraph is used to help understand the present invention. Some (or all) of the content (or all of the content) disclosed in the "prior art" paragraph may not be known in the prior art by those of ordinary skill in the art. The content disclosed in the "Prior Art" paragraph does not mean that the content has been known to those with ordinary knowledge in the technical field before the application of the present invention.

The present invention provides a chip and interface conversion device to enable display port The auxiliary channel (AUX channel, hereinafter referred to as AUX channel) pin of the (DisplayPort, hereinafter referred to as DP) connector can conform to the DP specification in different modes.

A chip of the present invention includes a first pad, a second pad, a third pad, a fourth pad, a fifth pad and a sixth pad. The first pad is suitable for coupling to the first Side Band Use (SBU) pin of the Universal Serial Bus (hereinafter referred to as USB) connector. The second pad is suitable for coupling to the second SBU pin of the USB connector. The third pad is suitable for coupling to the first end of the first capacitor. The fourth pad is adapted to be coupled to the second end of the first capacitor and to the first pin of the AUX channel of the DP connector. The fifth pad is suitable for coupling to the first end of the second capacitor. The sixth pad is adapted to be coupled to the second end of the second capacitor and to the second pin of the AUX channel of the DP connector. When the chip operates in the first mode, the first AUX channel signal and the second AUX channel signal conforming to the display port specification are selectively transmitted to the third pad and the fifth pad, respectively, and the voltage of the fourth pad is selected is selectively pulled down weakly, and the voltage of the sixth pad is selectively pulled up weakly. When the chip operates in the second mode, one of the first pad and the second pad is selectively connected to the fourth pad, and the other of the first pad and the second pad is selected is connected to the sixth pad.

A connection interface conversion device of the present invention includes a USB connector, a DP connector, a first capacitor, a second capacitor and a chip. The chip has a first pad, a second pad, a third pad, a fourth pad, a fifth pad and a sixth pad. The first pad is coupled to the first SBU pin of the USB connector, the second pad is coupled to the second SBU pin of the USB connector, the third pad is coupled to the first end of the first capacitor, and the fourth pad is coupled to the first end of the first capacitor. pad coupling The second end of the first capacitor and the first pin of the AUX channel of the DP connector, the fifth pad is coupled to the first end of the second capacitor, the sixth pad is coupled to the second end of the second capacitor and the DP connection The second pin of the AUX channel of the device. When the chip operates in the first mode, the chip selectively transmits the first AUX channel signal and the second AUX channel signal conforming to the display port specification to the third pad and the fifth pad, respectively, and the chip selectively pulls down the The voltage of the four pads, and the voltage of the sixth pad selectively weakly pulled up by the chip. When the chip operates in the second mode, the chip selectively connects one of the first pad and the second pad to the fourth pad, and the chip connects the other of the first pad and the second pad which is selectively connected to the sixth pad.

Based on the above, the interface conversion device can process the signal of the USB connector, regardless of whether the signal transmitted by the external device (eg, the host) to the USB connector is the signal of the first mode or the signal of the second mode. The chip can make the AUX channel pins of the DP connector conform to the DP specification in different modes.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

1: Interface conversion device

2, 2': host

3: Device

10, 20: USB connector

11, 30: DP connector

12: Wafer

100: Differential signal pin

101, 102: SBU pin

103: CC pin

110: The first pin

111: The second pin

120: Tunneling circuit

121: Connection circuit

121A, 121B: switch circuit

122: Microcontroller

200, 201, 202, 300, 301: Pins

AUX1: The first AUX channel signal

AUX2: The second AUX channel signal

AUX3: The third AUX channel signal

AUX4: The fourth AUX channel signal

CP1, CN1, CP2, CN2: Capacitors

N1, N2: Nodes

PD0~PD7: Pad

RN1, RN2: pull-up resistors

RP1, RP2: pull-down resistors

SW11~SW16, SW21~SW24: switch

DP_PWR: system voltage

GND: ground voltage

1A and FIG. 1B are schematic diagrams of circuit blocks of an interface conversion device connected between a host and a device according to an embodiment of the present invention.

FIG. 2 is a schematic circuit block diagram illustrating the chip shown in FIG. 1A and FIG. 1B according to an embodiment of the present invention.

FIG. 3A is a schematic diagram of a situation when the chip shown in FIG. 2 operates in a first mode according to an embodiment of the present invention.

FIG. 3B is a schematic diagram of a situation when the wafer shown in FIG. 2 is operated in the second mode according to an embodiment of the present invention.

3C is a schematic diagram of another situation when the wafer shown in FIG. 2 is operated in the second mode according to an embodiment of the present invention.

The term "coupled (or connected)" as used throughout this specification (including the scope of the application) may refer to any direct or indirect means of connection. For example, if it is described in the text that a first device is coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be connected to the second device through another device or some other device. indirectly connected to the second device by a connecting means. Terms such as "first" and "second" mentioned in the full text of the specification (including the scope of the patent application) are used to name the elements or to distinguish different embodiments or scopes, rather than to limit the number of elements The upper or lower limit of , nor is it intended to limit the order of the elements. Also, where possible, elements/components/steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Elements/components/steps that use the same reference numerals or use the same terminology in different embodiments may refer to relative descriptions of each other.

1A and 1B are schematic diagrams of circuit blocks of an interface conversion device 1 connected between a host 2 (or host 2') and a device 3 according to an embodiment of the present invention. The interface conversion device 1 has a universal serial bus (Universal Serial Bus, hereinafter referred to as USB) connector 10 and DisplayPort (hereinafter referred to as DP) connector 11 .

The USB connector 10 may be connected via a cable (or directly connected) to the USB connector 20 of the host 2 (or the host 2'). The at least one differential signal pin 100 of the USB connector 10 (or the at least one differential signal pin 200 of the USB connector 20 ) may include the SSTXp1 pin, SSTXn1 pin, SSRXp1 pin, SSRXn1 pin specified by the USB specification , SSTXp2 pin, SSTXn2 pin, SSRXp2 pin, SSRXn2 pin, Dp1 pin, Dn1 pin, Dp2 pin and/or Dn2 pin. The Side Band Use (SBU) pins 101 and 102 of the USB connector 10 (or the SBU pins 201 and 202 of the USB connector 20 ) may include the SBU1 pins and SBU2 pins specified by the USB specification. foot. The configuration channel (hereinafter referred to as CC) pin 103 of the USB connector 10 of the interface conversion device 1 may include the CC1 pin and/or the CC2 pin specified by the USB standard.

FIG. 1A shows that the host 2 is an electronic device that supports the USB 4.0 standard. The signal transmitted by the USB connector 20 of the host 2 conforms to the USB 4.0 standard, that is, the circuit configuration of the host 2 conforms to the USB 4.0 standard. When the USB connector 20 of the host 2 transmits a signal conforming to the USB 4.0 standard, the SBU pins 201 and 202 of the USB connector 20 of the host 2 can be used to transmit a side band signal conforming to the USB standard. The SBU pins and the sideband signals are regulated in the USB 4.0 specification, so they are not described here. When the signal transmitted by the host 2 is a USB 4.0 signal conforming to the USB 4.0 specification, the host 2 can use the tunneling (Tunneling) protocol to Specification data and AUX channel signals are encoded in the USB 4.0 signal packets. Therefore, the AUX channel signal can be transmitted to the differential signal pin 100 of the interface conversion device 1 through the pin 200 of the USB connector 20 . At this time, the interface conversion device 1 can correspondingly operate in the first mode.

In the first mode, the interface conversion device 1 can depacketize and/or decode the differential signal received by the differential signal pin 100 to generate data and AUX channel signals conforming to the Display Port (DP) specification. Therefore, the interface conversion device 1 can output the AUX channel signal to the device 3 from the first pin 110 and the second pin 111 of the AUX channel of the DP connector 11 .

FIG. 1B shows that the host 2' is an electronic device that supports DisplayPort Alternate Mode (ALT Mode, hereinafter referred to as ALT Mode) of USB Type-C. The host 2' also has a capacitor CP2, a capacitor CN2, a pull-down resistor RP2 and a pull-up resistor RN2. The first end of the pull-down resistor RP2 receives the first reference voltage (eg, the ground voltage GND). The second end of the pull-down resistor RP2 and the first end of the capacitor CP2 are coupled to the SBU pin 201 of the USB connector 20 . The first end of the pull-up resistor RN2 receives the second reference voltage (eg, the system voltage DP_PWR higher than the ground voltage GND). The second end of the pull-up resistor RN2 and the first end of the capacitor CN2 are coupled to the SBU pin 202 of the USB connector 20 . The host 2' can operate in the ALT mode, so as to output data conforming to the DP specification and an auxiliary channel (AUX channel, hereinafter referred to as AUX channel) signal from the USB connector 20. The AUX channel signal is regulated in the DP specification, so it will not be repeated here. When the USB connector 20 of the host 2' operates in the ALT mode, the SBU pins 201 and 202 of the USB connector 20 of the host 2' can be used to transmit DP-compliant Specifications of the AUX channel signal.

Please refer to FIG. 1A or FIG. 1B . The DP connector 11 may be connected (or directly connected) to the DP connector 30 of the device 3 via a cable. The AUX channel pins 110 and 111 of the DP connector 11 of the interface conversion device 1 (or the AUX channel pins 300 and 301 of the DP connector 30 of the device 3 ) may include the AUX_CH(p) pins and AUX_CH(n) pin. The interface conversion device 1 may provide an interface conversion function to transfer data from the USB connector 20 (eg, a USB Type-C connector) of the host 2 (or the host 2') to the DP connector 30 of the device 3, and (or Yes) Transfer the data of the DP connector 30 of the device 3 to the USB connector 20 of the host 2 (or the host 2').

The interface conversion device 1 further includes a chip 12 , a power delivery (Power Delivery, hereinafter referred to as PD) controller 13 , a first capacitor CP1 and a second capacitor CN1 . According to the connection configuration signal provided by the PD controller 13, the chip 12 of the interface conversion device 1 can selectively operate in the first mode, the second mode and/or other modes. For example, when the host 2 is connected to the USB connector 10 (as shown in FIG. 1A ), the chip 12 can selectively operate in the first mode (USB 4.0 mode). When the host 2' is connected to the USB connector 10 (as shown in FIG. 1B), the die 12 can selectively operate in a second mode (ALT mode).

The chip 12 also has pads PD0, PD1, PD2, PD3, PD4, PD5, and PD6. The differential signal pin 100 of the USB connector 10 is coupled to at least one pad PD0 of the chip 12 . The pads PD1 and PD2 of the chip 12 are suitable for coupling with the SBU pins 101 and the SBU pins of the USB connector 10 . feet 102.

The CC pin 103 of the USB connector 10 is coupled to the power delivery (PD) controller 13 . When the host 2 (or the host 2 ′) is connected to the USB connector 10 , the PD controller 13 can exchange configuration information with the host 2 (or the host 2 ′) via the CC pin 103 and detect the USB connection via the CC pin 103 The connection configuration of the device 10. The related operations of PD (Power Delivery) control and CC pins are regulated in the USB specification, so they will not be repeated here. Therefore, according to the detection result of the CC pin 103, the PD controller 13 can know whether the host connected to the USB connector 10 is an electronic device supporting the USB 4.0 specification (such as the host 2) or an electronic device running the ALT mode (such as the host). 2'). In addition, according to the detection result of the CC pin 103 , the PD controller 13 can know whether the USB Type-C plug (not shown) of the host 2 (or the host 2 ′) is inserted into the USB connector 10 with the front side up or the reverse side. Insert the USB connector 10 facing upwards. The PD controller 13 may provide a connection configuration signal to the pad PD7 of the chip 12 according to the connection configuration of the USB connector 10 to instruct the chip 12 to operate in the first mode or the second mode.

The pad PD3 is suitable for coupling to the first end of the capacitor CP1. The pad PD4 is suitable for coupling to the second end of the capacitor CP1. The pad PD5 is suitable for coupling to the first end of the capacitor CN1. The pad PD6 is suitable for coupling to the second end of the capacitor CN1. The first pin 110 and the second pin 111 of the AUX channel of the DP connector 11 are respectively connected to the pad PD4 and the pad PD6 of the chip 12 . The DP connector 30 of the device 3 has pins 300 and 301 of the AUX channel. When the DP connector 11 is connected to the DP connector 30, the device 3 can connect to the first pin 110 and the second pin of the AUX channel of the DP connector 11 through the pins 300 and 301. Pin 111 sends and receives signals.

The pad PD7 of the chip 12 of the interface conversion device 1 is coupled to the PD controller 13 to receive the connection configuration signal. The chip 12 can determine whether the interface conversion device 1 operates in the first mode, the second mode and/or other modes according to the connection configuration signal.

In an embodiment, please refer to FIG. 1A , when the chip 12 in the interface conversion device 1 is operating in the first mode (that is, the signal transmitted by the host 2 is a signal conforming to the USB 4.0 specification), the chip 12 can weakly pull down the The voltage of the four pads PD4 and the voltage of the sixth pad PD6 are weakly pulled up. The so-called "weak pull-down" means that when the fourth pad PD4 is floating, the chip 12 can pull down the voltage of the fourth pad PD4 to a low level; and when the fourth pad PD4 is coupled to external components , the external element can change the voltage of the fourth pad PD4. The so-called "weak pull-up" means that when the sixth pad PD6 is floating, the chip 12 can pull up the voltage of the sixth pad PD6 to a high level; and when the sixth pad PD6 is coupled to the outside When the component is used, the external component can change the voltage of the sixth pad PD6.

In the first mode, the chip 12 can depacketize and/or decode the differential signal received by the differential signal pin 100 to generate data and AUX channel signals conforming to the Display Port (DP) specification. The chip 12 can selectively transmit the AUX channel signal (the first AUX channel signal and the second AUX channel signal) conforming to the DP specification to the pad PD3 and the pad PD5, respectively. Therefore, the interface conversion device 1 can transmit the AUX channel signal (ie, the AUX channel signal of the host 2 ) to the device 3 according to the DP specification.

In another embodiment, please refer to FIG. 1B , when the signal transmitted by the host 2 is an ALT mode signal that conforms to the USB specification, the host 2 can transmit data conforming to the Display Port (DP) specification through the pin 200 , and the The SBU pins 201 and 202 are used to transmit data and AUX channel signals (the third AUX channel signal and the fourth AUX channel signal) conforming to the DP specification. When the signal transmitted by the host 2 is a signal conforming to the ALT mode, the chip 12 in the interface conversion device 1 can correspondingly operate in the second mode.

When the chip 12 in the interface conversion apparatus 1 operates in the second mode, the chip 12 can disable the capacitor CP1 and the capacitor CN1. In the second mode, the chip 12 can selectively connect one of the pads PD1 and PD2 to the pad PD4, and selectively connect the other of the pads PD1 and PD2 to the pad. Pad PD6. Therefore, one of the SBU pin 101 and the SBU pin 102 of the USB connector 10 can be selectively connected to the first pin 110 of the AUX channel of the DP connector 11, and the SBU pin 101 and the SBU pin The other of the two pins 102 can be selectively connected to the second pin 111 of the AUX channel of the DP connector 11 . That is, the host 2' can transmit the AUX channel signal to the device 3 through the interface conversion device 1 according to the DP specification.

For example, assuming that the third AUX channel signal received by the SBU pin 101 is a positive AUX channel signal and the fourth AUX channel signal received by the SBU pin 102 is a negative AUX channel signal, the SBU of the USB connector 10 The pin 101 can be connected to the first pin 110 of the AUX channel of the DP connector 11 through the chip 12, and the SBU pin 102 of the USB connector 10 can be connected to the first pin 110 of the AUX channel of the USB connector 10 through the chip 12. The chip 12 is connected to the second pin 111 of the AUX channel of the DP connector 11 . Alternatively, if the third AUX channel signal received by the SBU pin 101 is a negative AUX channel signal and the fourth AUX channel signal received by the SBU pin 102 is a positive AUX channel signal, the SBU pin of the USB connector 10 101 can be connected to the second pin 111 of the AUX channel of the DP connector 11 through the die 12, and the SBU pin 102 of the USB connector 10 can be connected to the second pin 111 of the AUX channel of the DP connector 11 through the die 12. A pin 110. Therefore, the SBU pins 201 and 202 of the USB connector 20 of the host 2' can transmit the AUX channel signals conforming to the DP specification to the AUX channel pins 300 and 301 of the DP connector 30 of the device 3, and/or the device The AUX channel pins 300 and 301 of the DP connector 30 of 3 can transmit AUX channel signals conforming to the DP specification to the SBU pins 201 and 202 of the USB connector 20 of the host 2'.

In short, the interface conversion device 1 is applicable to interface conversion between the host 2 and the device 3 of different specifications. The interface conversion device 1 can process the signal of the USB connector 10, regardless of whether the signal transmitted to the USB connector 10 by an external device (such as the host 2 or the host 2') is the signal of the first mode (USB 4.0 mode) or the second mode mode (ALT mode) signal. The chip 12 of the interface conversion device 1 can make the AUX channel pins of the DP connector 11 conform to the DP specification in different modes.

FIG. 2 is a schematic circuit block diagram illustrating the chip 12 shown in FIGS. 1A and 1B according to an embodiment of the present invention. The chip 12 can be connected to the first capacitor CP1 and the second capacitor CN1. The chip 12, the first capacitor CP1 and the second capacitor CN1 shown in FIG. 2 can refer to the chip 12, the first capacitor CP1 and the second capacitor shown in FIG. 1A and/or FIG. 1B The relevant description of CN1 is not included, so it will not be repeated here. In the embodiment shown in FIG. 2 , the chip 12 further includes a tunnel circuit 120 , a connection circuit 121 , a microcontroller 122 , a pull-down resistor RP1 and a pull-up resistor RN1 .

Please refer to FIG. 1A , FIG. 1B and FIG. 2 . The pad PD0 , the pad PD1 and the pad PD2 are connected to the tunneling circuit 120 . In the first mode (USB 4.0 mode), the tunneling circuit 120 can output the first AUX channel signal and the second AUX channel signal to the connection circuit 121 in the first mode. The connecting circuit 121 is coupled to the tunneling circuit 120 to receive the first AUX channel signal and the second AUX channel signal. The connection circuit 121 is further coupled to the pull-down resistor RP1 , the pull-up resistor RN1 , the pad PD1 , the pad PD2 , the pad PD3 , the pad PD4 , the pad PD5 , and the pad PD6 .

The microcontroller 122 is connected to the pad PD7 to receive the connection configuration signal from the PD controller 13 . The microcontroller 122 is also coupled to the connection circuit 121 . The microcontroller generates at least one switch signal to the connection circuit 121 according to the connection configuration signal to indicate whether the chip 12 operates in the first mode (USB 4.0 mode) or the second mode (ALT mode).

When the USB connector 20 of the external device (such as the host 2 shown in FIG. 1A ) transmits a signal conforming to the USB 4.0 specification to the USB connector 10 of the interface conversion device 1, and when the chip 12 operates in the first mode, the pad PD1 And the pad PD2 can receive (transmit) the sideband signal from the host 2 and conform to the USB 4.0 specification. When the chip 12 operates in the first mode (USB 4.0 mode), the tunneling circuit 120 can depacketize and/or decode the differential signal received by the docking pad PD0 to generate data and data that conform to the Display Port (DP) specification. AUX channel signal (first AUX channel signal and the second AUX channel signal). The tunneling circuit 120 can output the first AUX channel signal and the second AUX channel signal to the connection circuit 121 in the first mode. When the chip 12 operates in the first mode (USB 4.0 mode), the connection circuit 121 is configured to selectively transmit the first AUX channel signal and the second AUX channel signal generated by the tunneling circuit 120 to the pad PD3 respectively. and pad PD5, and the pad PD4 is selectively connected to the first end of the pull-down resistor RP1, and the pad PD6 is selectively connected to the first end of the pull-up resistor RN1. The second end of the pull-up resistor RN1 receives a reference voltage (eg, the system voltage DP_PWR). The second end of the pull-down resistor RP1 receives a reference voltage (eg, a ground voltage GND lower than the system voltage DP_PWR).

When the USB connector 20 of the external device (such as the host 2 ′ shown in FIG. 1A ) transmits the ALT mode signal conforming to the USB specification to the USB connector 10 of the interface conversion device 1 , that is, when the chip 12 operates in the second mode, The pads PD1 and PD2 can receive (transmit) AUX channel signals (a third AUX channel signal and a fourth AUX channel signal) from the host 2 ′ that conform to the DP specification. In the second mode (ALT mode), the tunneling circuit 120 may not output (not generate) the AUX channel signals (the first AUX channel signal and the second AUX channel signal) to the connection circuit 121 . When the chip 12 operates in the second mode (ALT mode), the connection circuit 121 is configured to selectively connect one of the pads PD1 and PD2 to the pad PD4, and to connect the pads PD1 and PD2 The other of the two pads PD2 is selectively connected to the pad PD6.

The invention does not limit the implementation details of the connection circuit 121 . For example, in the embodiment shown in FIG. 2 , the connection circuit 121 includes a switch circuit 121A and a switch circuit 121B. The switch circuit 121A is coupled to the tunneling circuit 120 , the pad PD1 , the pad PD2 , the microcontroller 122 , the node N1 and the node N2 . The second switch circuit 121B is connected to the node N1 , the node N2 , the pull-down resistor RP1 , the pull-up resistor RN1 , the pad PD3 , the pad PD4 , the pad PD5 , the pad PD6 and the microcontroller 122 .

When the chip 12 operates in the first mode (USB 4.0 mode), the switch circuit 121A can selectively transmit the first AUX channel signal and the second AUX channel signal generated by the tunneling circuit 120 to the node N1 and the node N2, respectively. When the chip 12 operates in the first mode (USB 4.0 mode), the switch circuit 121B is configured to connect the node N1 to the pad PD3 and the node N2 to the pad PD5.

When the chip 12 operates in the second mode (ALT mode), the switch circuit 121A is configured to selectively connect one of the pads PD1 and PD2 to the node N1, and to connect the pads PD1 and PD2 to the node N1. The other of the two pads PD2 is selectively connected to the node N2. For example, when the signal received by the SBU pin 101 of the USB connector 10 is a positive polarity AUX channel signal and the signal received by the SBU pin 102 of the USB connector 10 is a negative polarity AUX channel signal, the switch circuit 121A can Pad PD1 is connected to node N1, and pad PD2 is connected to node N2. Conversely, when the signal of the SBU pin 101 is a negative AUX channel signal and the signal of the SBU pin 102 is a positive AUX channel signal, the switch circuit 121A can connect the pad PD2 to the node N1 and the pad PD1 to the node N1. Node N2. When the chip 12 operates in the second mode (ALT mode), the switch circuit 121B can connect the node N1 to the pad PD4 and the node N2 to the pad PD6.

The present invention does not limit the implementation details of the switch circuit 121A. for example, In the embodiment shown in FIG. 2 , the switch circuit 121A includes a switch SW11 , a switch SW12 , a switch SW13 , a switch SW14 , a switch SW15 and a switch SW16 . The first end of the switch SW11 is coupled to the tunneling circuit 120 to receive the first AUX channel signal. The second terminal of the switch SW11 is coupled to the node N1. The switch SW12 is coupled to the tunneling circuit 120 to receive the second AUX channel signal. The second terminal of the switch SW12 is coupled to the node N2. The first end of the switch SW13 is coupled to the pad PD1. The second terminal of the switch SW13 is coupled to the node N1. The first end of the switch SW14 is coupled to the pad PD1. The second terminal of the switch SW14 is coupled to the node N2. The first end of the switch SW15 is coupled to the pad PD2. The second terminal of the switch SW15 is coupled to the node N1. The first end of the switch SW16 is coupled to the pad PD2. The second terminal of the switch SW16 is coupled to the node N2.

The present invention does not limit the implementation details of the switch circuit 121B. For example, in the embodiment shown in FIG. 2 , the switch circuit 121B includes a switch SW21 , a switch SW22 , a switch SW23 and a switch SW24 . The first end of the switch SW21 is coupled to the node N1 and the pad PD3. The second end of the switch SW21 is coupled to the pad PD4. The first end of the switch SW22 is coupled to the pad PD4. The second terminal of the switch SW22 is coupled to the pull-down resistor RP1. The first end of the switch SW23 is coupled to the node N2 and the pad PD5. The second end of the switch SW23 is coupled to the pad PD6. The first end of the switch SW24 is coupled to the pad PD6. The second end of the switch SW24 is coupled to the pull-up resistor RN1.

3A to 3C will illustrate detailed operations of the first switch circuit 121A and the second switch circuit 121B in different modes and states. FIG. 3A is a schematic diagram illustrating a situation when the chip 12 shown in FIG. 2 operates in the first mode (USB 4.0 mode) according to an embodiment of the present invention. As shown in FIG. 3A, when the wafer 12 is operated in the first mold In USB 4.0 mode (USB 4.0 mode), the tunneling circuit 120 of the chip 12 can depacketize and/or decode the differential signal received by the docking pad PD0 to generate data and AUX channel signals ( The first AUX channel signal AUX1 and the second AUX channel signal AUX2). Based on the control of the microcontroller 122, the turned-on switch SW11 and the second switch SW12 transmit the first AUX channel signal AUX1 and the second AUX channel signal AUX2 generated by the tunneling circuit 120 to the pad PD3 and the pad PD5. Based on the control of the microcontroller 122, in the first mode (USB 4.0 mode), the switch SW13, the switch SW14, the switch SW15, the switch SW16, the switch SW21 and the switch SW23 are turned off, and the switch SW22 and the switch SW24 are turned off. on. In this way, the first AUX channel signal AUX1 generated by the tunneling circuit 120 will be transmitted to the first pin 110 of the AUX channel of the DP connector 11 through the pad PD3 and the capacitor CP1, and the pull-down resistor RP1 will pass through the connection. The pad PD4 weakly pulls down the DC level of the first pin 110 to the first reference voltage (eg, the ground voltage GND). In addition, the second AUX channel signal AUX2 generated by the tunneling circuit 120 will be transmitted to the second pin 111 of the AUX channel of the DP connector 11 through the pad PD5 and the capacitor CN1, and the pull-up resistor RN1 will pass through the pad The PD6 weakly pulls up the DC level of the second pin 111 to the second reference voltage (eg, the system voltage DP_PWR higher than the ground voltage GND).

When the switch SW13 and the switch SW16 are turned on in the second mode (ALT mode), the switch SW14 and the switch SW15 are turned off. When the switch SW13 and the switch SW16 are turned off in the second mode (ALT mode), the switch SW14 and the switch SW15 are turned on. For example, when the SBU pin 101 of the USB connector 10 is When the received signal is a positive polarity AUX channel signal and the signal received by the SBU pin 102 of the USB connector 10 is a negative polarity AUX channel signal, based on the control of the microcontroller 122, the switch SW13 and the switch SW16 in the second mode are On, and switches SW14 and SW15 are off in the second mode. On the contrary, when the signal of the SBU pin 101 is a negative AUX channel signal and the signal of the SBU pin 102 is a positive AUX channel signal, based on the control of the microcontroller 122, the switch SW13 and the switch SW16 are turned off in the second mode. , and the switches SW14 and SW15 are turned on in the second mode.

3B is a schematic diagram of a situation when the chip 12 shown in FIG. 2 operates in the second mode (ALT mode) according to an embodiment of the present invention. When the chip 12 operates in the second mode (ALT mode), the pads PD1 and PD2 of the chip 12 receive the third AUX channel signal AUX3 and the fourth signal from the SBU pin 101 and the SBU pin 102 of the USB connector 10 . AUX channel signal AUX4. The situation shown in FIG. 3B is assuming that the signal received by the SBU pin 101 of the USB connector 10 is the third AUX channel signal AUX3 of positive polarity, and the signal received by the SBU pin 102 of the USB connector 10 is negative polarity The fourth AUX channel signal AUX4. Based on the control of the microcontroller 122, in the second mode (ALT mode), the switch SW13, the second switch SW16, the switch SW21, and the second switch SW23 that are turned on can connect the first and second pads PD1 and PD2. The three AUX channel signals AUX3 and the fourth AUX channel signal AUX4 are transmitted to the pads PD4 and PD6.

In the situation shown in FIG. 3B , based on the control of the microcontroller 122 , the switch SW11 , the switch SW12 , the switch SW14 , the switch SW15 , the switch SW22 and the switch SW24 is turned off, and switch SW13, switch SW16, switch SW21, and switch SW23 are turned on. Therefore, the capacitor CP1, the capacitor CN1, the pull-down resistor RP1 and the pull-up resistor RN1 are disabled. The pull-down resistor RP1, the pull-up resistor RN1, the capacitor CP1, and the capacitor CN1 do not become impedances of the pads PD4 and PD6.

3C is a schematic diagram of another situation when the chip 12 shown in FIG. 2 operates in the second mode (ALT mode) according to an embodiment of the present invention. When the chip 12 operates in the second mode (ALT mode), the pads PD1 and PD2 of the chip 12 receive the third AUX channel signal AUX3 and the fourth signal from the SBU pin 101 and the SBU pin 102 of the USB connector 10 . AUX channel signal AUX4. The situation shown in FIG. 3C is assuming that the signal received by the SBU pin 101 of the USB connector 10 is the third AUX channel signal AUX3 of negative polarity, and the signal received by the SBU pin 102 of the USB connector 10 is positive polarity The fourth AUX channel signal AUX4. Based on the control of the microcontroller 122 , in the second mode (ALT mode), the turned-on switch SW14 , the second switch SW15 , the switch SW21 and the second switch SW23 can connect the third AUX channel signal of the pad PD1 and the pad PD2 The AUX3 and the fourth AUX channel signal AUX4 are transmitted to the pads PD6 and PD4.

3C, based on the control of the microcontroller 122, switches SW11, SW12, SW13, SW16, SW22, and SW24 are turned off, and switches SW14, SW15, SW21, and SW23 are turned on. Therefore, the capacitor CP1, the capacitor CN1, the pull-down resistor RP1 and the pull-up resistor RN1 are disabled. The pull-down resistor RP1, the pull-up resistor RN1, the capacitor CP1, and the capacitor CN1 do not become impedances of the pads PD4 and PD6.

To sum up, the interface conversion device 1 and the chip 12 can provide interface conversion functions of different specifications in different operation modes. The interface conversion device 1 can process the signal of the USB connector 10, regardless of whether the signal transmitted to the USB connector 10 by an external device (such as the host 2 or the host 2') is the signal of the first mode (USB 4.0 mode) or the second mode mode (ALT mode) signal. The chip 12 can make the AUX channel pins of the DP connector 11 conform to the DP specification in different modes. Therefore, the interface conversion device 1 and the chip 12 can effectively improve the compatibility when connecting devices of different specifications.

Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

12: Wafer

120: Tunneling circuit

121: Connection circuit

121A, 121B: switch circuit

122: Microcontroller

CP1, CN1: Capacitor

N1, N2: Nodes

PD0~PD7: Pad

RN1: Pull-up resistor

RP1: pull-down resistor

SW11~SW16, SW21~SW24: switch

DP_PWR: system voltage

GND: ground voltage

Claims (19)

A chip, comprising: a first pad suitable for coupling with a first sideband-use pin of a universal serial bus connector; a second pad suitable for coupling with the universal serial bus connector a second sideband using pins; a third pad suitable for coupling to a first end of a first capacitor; a fourth pad suitable for coupling to a second end of the first capacitor, and a first pin suitable for coupling to an auxiliary channel of a display port connector; a fifth pad suitable for coupling with a first end of a second capacitor; and a sixth pad suitable for coupling A second end connected to the second capacitor, and a second pin adapted to be coupled to the auxiliary channel of the display port connector, wherein when the chip operates in a first mode, it complies with a display port specification A first auxiliary channel signal and a second auxiliary channel signal are selectively transmitted to the third pad and the fifth pad, respectively, the voltage of the fourth pad is selectively weakly pulled down, and the sixth The voltage of the pad is selectively pulled up weakly, and one of the first pad and the second pad is selectively connected to the fourth pad when the chip operates in a second mode , and the other one of the first pad and the second pad is selectively connected to the sixth pad. The chip according to claim 1, further comprising: a pull-up resistor; a pull-up resistor; a tunnel circuit configured to provide the first auxiliary channel signal and the second auxiliary channel signal in the first mode; and a connection circuit coupled to the tunnel circuit to receive the first auxiliary channel signal and the second auxiliary channel signal The second auxiliary channel signal is coupled to the pull-down resistor, the pull-up resistor, the first pad, the second pad, the third pad, the fourth pad, the fifth pad and the first pad Six pads; wherein when the chip operates in the first mode, the connection circuit is configured to selectively transmit the first auxiliary channel signal and the second auxiliary channel signal to the third pad and the third pad, respectively a fifth pad, selectively connecting the fourth pad to the pull-down resistor, and selectively connecting the sixth pad to the pull-up resistor; and wherein when the chip operates in the second mode, The connection circuit is configured to selectively connect one of the first pad and the second pad to the fourth pad, and to selectively connect the other of the first pad and the second pad One is selectively connected to the sixth pad. The chip of claim 2, further comprising: a microcontroller coupled to the connection circuit, wherein the microcontroller generates at least one switch signal to the connection circuit according to a connection configuration signal to indicate that the chip is operating in the first mode or the second mode. The chip of claim 2, wherein when the chip operates in the first mode, the signals transmitted by the first pads and the second pads are sideband signals conforming to a Universal Serial Bus 4.0 specification; and when the chip operates in the second mode, the first pad and the second pad are The transmitted signals are a third auxiliary channel signal and a fourth auxiliary channel signal conforming to the specification of the display port. The chip of claim 2, wherein the connection circuit comprises: a first node; a second node; a first switch circuit coupled to the first pad, the second pad, the tunnel circuit, the first node and the second node; and a second switch circuit coupled to the first node, the second node, the pull-down resistor, the pull-up resistor, the third pad, the fourth pad, the fifth pad and the sixth pad. The chip of claim 5, wherein when the chip operates in the first mode, the first switch circuit is configured to selectively transmit the first auxiliary channel signal and the second auxiliary channel signal to the the first node and the second node; and when the chip operates in the second mode, the first switch circuit is configured to selectively select one of the first pad and the second pad connecting to the first node, and selectively connecting the other of the first pad and the second pad to the second node. The chip of claim 5, wherein the first switch circuit comprises: a first switch having a first end coupled to the tunneling circuit to receive the first auxiliary channel signal, wherein a first switch of the first switch The two terminals are coupled to the first node; a second switch has a first terminal coupled to the tunnel circuit to receive the second auxiliary switch Auxiliary channel signal, wherein a second end of the second switch is coupled to the second node; a third switch has a first end coupled to the first pad and a second end coupled to the first node a fourth switch having a first end coupled to the first pad and a second end coupled to the second node; a fifth switch having a first end coupled to the second pad terminal and a second terminal coupled to the first node; and a sixth switch having a first terminal coupled to the second pad and a second terminal coupled to the second node; wherein in the first In a mode, the first switch and the second switch are turned on, and the third switch, the fourth switch, the fifth switch and the sixth switch are turned off; wherein in the second mode, the first switch the switch and the second switch are off; wherein in the second mode, when the third switch and the sixth switch are on, the fourth switch and the fifth switch are off; and wherein in the second mode Among them, when the third switch and the sixth switch are off, the fourth switch and the fifth switch are on. The wafer of claim 5, wherein the second switch circuit is configured to connect the first node to the third pad and to connect the second node when the wafer operates in the first mode to the fifth pad; and when the chip operates in the second mode, the second switch circuit is configured to connect the first node to the fourth pad and to connect the second node to the the first Six pads. The chip of claim 5, wherein the second switch circuit comprises: a first switch having a first end coupled to the first node and the third pad, and a first end coupled to the fourth pad a second end, wherein the first switch is turned off in the first mode, and the first switch is turned on in the second mode; a second switch has a first end coupled to the fourth pad and a coupling connected to a second end of the pull-down resistor, wherein the second switch is turned on in the first mode, and the second switch is turned off in the second mode; a third switch is coupled to the second node and the a first end of the fifth pad and a second end coupled to the sixth pad, wherein the third switch is turned off in the first mode, and the third switch is turned on in the second mode; and a fourth switch, having a first end coupled to the sixth pad and a second end coupled to the pull-up resistor, wherein the fourth switch is turned on in the first mode, and the fourth switch is on The second mode is cutoff. A connection interface conversion device, comprising: a universal serial bus connector; a display port connector; a first capacitor and a second capacitor; and a chip with a first pad, a second pad, a A third pad, a fourth pad, a fifth pad and a sixth pad, wherein the first pad is coupled to a first sideband-use pin of the universal serial bus connector, the The second pad is coupled to a second sideband pin of the universal serial bus connector, and the third pad is coupled to A first end of the first capacitor, the fourth pad is coupled to a second end of the first capacitor and a first pin of an auxiliary channel of the display port connector, and the fifth pad is coupled to A first end of the second capacitor, the sixth pad is coupled to a second end of the second capacitor and a second pin of the auxiliary channel of the display port connector; wherein when the chip operates on a In the first mode, the chip selectively transmits a first auxiliary channel signal and a second auxiliary channel signal conforming to a display port specification to the third pad and the fifth pad, respectively, and the chip selectively transmits a first auxiliary channel signal and a second auxiliary channel signal to the third pad and the fifth pad respectively. Weakly pull down the voltage of the fourth pad, and the chip selectively weakly pull up the voltage of the sixth pad; and wherein when the chip operates in a second mode, the chip operates the first pad and the One of the second pads is selectively connected to the fourth pad, and the chip selectively connects the other of the first pad and the second pad to the sixth pad. The connection interface conversion device of claim 10, wherein the chip further comprises: a pull-down resistor; a pull-up resistor; a tunnel circuit configured to provide the first auxiliary channel signal and the a second auxiliary channel signal; and a connection circuit coupled to the tunneling circuit to receive the first auxiliary channel signal and the second auxiliary channel signal, and coupled to the pull-down resistor, the pull-up resistor, and the first pad , the second pad, the third pad, the fourth pad, the fifth pad and the sixth pad; wherein when the chip operates in the first mode, the connection circuit is configured to selectively transmit the first auxiliary channel signal and the second auxiliary channel signal to the third pad respectively and the fifth pad, the fourth pad is selectively connected to the pull-down resistor, and the sixth pad is selectively connected to the pull-up resistor; and wherein when the chip operates in the second mode , the connection circuit is configured to selectively connect one of the first pad and the second pad to the fourth pad, and connect the first pad and the second pad to the fourth pad selectively The other of the is selectively connected to the sixth pad. The connection interface conversion device of claim 11, wherein the chip further comprises: a microcontroller coupled to the connection circuit, wherein the microcontroller generates at least one switch signal to the connection circuit according to a connection configuration signal, to indicate whether the wafer is operating in the first mode or the second mode. The connection interface conversion device of claim 11, wherein when the chip operates in the first mode, the signals transmitted by the first pad and the second pad are a side that complies with a universal serial bus 4.0 specification with a signal; and when the chip operates in the second mode, the signals transmitted by the first pad and the second pad are a third auxiliary channel signal and a fourth auxiliary channel signal conforming to the display port specification . The connection interface conversion device according to claim 11, wherein the connection circuit comprises: a first node; a second node; a first switch circuit coupled to the first pad, the second pad, the tunnel circuit, the first node and the second node; and a second switch The circuit is coupled to the first node, the second node, the pull-down resistor, the pull-up resistor, the third pad, the fourth pad, the fifth pad and the sixth pad. The connection interface conversion device of claim 14, wherein when the chip operates in the first mode, the first switch circuit is configured to selectively select the first auxiliary channel signal and the second auxiliary channel signal, respectively ground is transmitted to the first node and the second node; and when the chip operates in the second mode, the first switch circuit is configured to one of the first pad and the second pad selectively connecting to the first node, and selectively connecting the other of the first pad and the second pad to the second node. The connection interface conversion device of claim 14, wherein the first switch circuit comprises: a first switch having a first end coupled to the tunnel circuit to receive the first auxiliary channel signal, wherein the first switch A second end of the second switch is coupled to the first node; a second switch has a first end coupled to the tunnel circuit to receive the second auxiliary channel signal, wherein a second end of the second switch is coupled to the a second node; a third switch having a first end coupled to the first pad and coupled to the first a second end of a node; a fourth switch having a first end coupled to the first pad and a second end coupled to the second node; a fifth switch having a second end coupled to the second a first end of the pad and a second end coupled to the first node; and a sixth switch having a first end coupled to the second pad and a second end coupled to the second node terminal; wherein in the first mode, the first switch and the second switch are on, and the third switch, the fourth switch, the fifth switch and the sixth switch are off; wherein in the second switch In the mode, the first switch and the second switch are off; wherein in the second mode, when the third switch and the sixth switch are on, the fourth switch and the fifth switch are off; and In the second mode, when the third switch and the sixth switch are turned off, the fourth switch and the fifth switch are turned on. The connection interface conversion device of claim 14, wherein when the chip operates in the first mode, the second switch circuit is configured to connect the first node to the third pad, and to connect the first node to the third pad. Two nodes are connected to the fifth pad; and when the chip operates in the second mode, the second switch circuit is configured to connect the first node to the fourth pad and the second node connected to the sixth pad. The connection interface conversion device of claim 14, wherein the second switch circuit comprises: a first switch having a first end coupled to the first node and the third pad and coupled to the fourth pad a second end of the pad, wherein the first switch is turned off in the first mode, and the first switch is turned on in the second mode; a second switch has a first switch coupled to the fourth pad terminal and a second terminal coupled to the pull-down resistor, wherein the second switch is turned on in the first mode, and the second switch is turned off in the second mode; a third switch is coupled to the second switch A node and a first end of the fifth pad and a second end coupled to the sixth pad, wherein the third switch is off in the first mode, and the third switch is in the second mode and a fourth switch having a first end coupled to the sixth pad and a second end coupled to the pull-up resistor, wherein the fourth switch is turned on in the first mode, and the first The four switches are turned off in the second mode. The connection interface conversion device of claim 10, further comprising: a power transmission controller configured to provide a connection configuration signal to the chip according to the connection configuration of the universal serial bus connector to instruct the chip to The wafer operates in the first mode or the second mode.

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