TWI738825B - Server system - Google Patents

Abstract

A server system according to this invention has a main board, a processor disposed on the main board, a plurality of first buses, a plurality of second buses and a plurality of storage medium. The processor has a plurality of processing cores and at least one platform controller hub (PCH) electrically connected to the plurality of processing cores. The first buses and the second buses are all disposed on the main board and electrically connected to the PCH. Parts of the plurality of storage medium are plugged in the first buses and the other parts are plugged in the second buses.

Description

Server system

The present invention relates to a server system, in particular to a 1U server system.

Servers generally have complete chassis, power supplies, motherboards, storage and other standard components. Generally, a rack can hold about 42 1U servers. With the development of the era of big data, end users pay more and more attention to the application of big data (cloud), and because of such applications, a server with high storage capacity is needed to improve the ability of data exchange and communication. In particular, end users have a demand for PCIE interface type solid state drives. However, existing servers are often limited by their network communication capabilities and the number of input and output ports, and cannot meet the needs of current and future end users.

In view of the above problems, the present invention provides a server system. Based on the existing 1U server architecture, the configuration and connection relationship of the components are changed, and some components are added to improve the network communication capability and input and output ports of the 1U server. quantity.

A server system according to an embodiment of the present invention includes a main board, a processor disposed on the main board, a plurality of first bus bars, a plurality of second bus bars, and a plurality of storage media. The processor includes multiple processing cores and at least one platform controller hub (PCH) electrically connected to the multiple processing cores. The plurality of first bus bars and the plurality of second bus bars are both disposed on the main board and electrically connected to the platform path controller. Part of the plurality of storage media is inserted into the plurality of first bus bars, and another part is inserted into the plurality of second bus bars.

In the server system disclosed in the present invention, by integrating the platform path controller into the processor, space can be reserved for disposing more input and output components on the motherboard of the server system. Thereby, the number of input and output ports or the communication capability of the server system can be increased.

The above description of the disclosure and the following description of the embodiments are used to demonstrate and explain the spirit and principle of the present invention, and to provide a further explanation of the scope of the patent application of the present invention.

The detailed features and advantages of the present invention are described in detail in the following embodiments. The content is sufficient to enable anyone familiar with the relevant art to understand the technical content of the present invention and implement it accordingly, and is based on the content disclosed in this specification, the scope of patent application and the drawings. Anyone who is familiar with relevant skills can easily understand the purpose and advantages of the present invention. The following examples further illustrate the viewpoints of the present invention in detail, but do not limit the scope of the present invention by any viewpoint.

Please refer to FIG. 1, which is a schematic diagram of a server system architecture according to an embodiment of the present invention. As shown in FIG. 1, a server system 1000 according to an embodiment of the present invention has a main board 1100, a processor 1200 disposed on the main board, a plurality of first bus bars 1310 to 1340, a plurality of second bus bars 1410 to 1480, and multiple A storage medium 1500A~1500L.

The processor 1200 has multiple processing cores 1210-1240 and a platform controller hub (PCH) 1250. The processing cores 1210~1240 are capable of parallel instruction processing. The platform path controller 1250 is electrically connected to the aforementioned multiple processing cores 1210-1240. Since the platform path controller 1250 is built in the processor, compared to the prior art, the space normally reserved for the platform path controller 1250 on the motherboard 1000 can be vacated for other components. In an embodiment of the present case, the processor 1200 is, for example, a Naples processor (Naples®), but the present invention is not limited.

The first bus bars 1310 to 1340 and the second bus bars 1410 to 1480 are both disposed on the motherboard 1100 and electrically connected to the platform path controller 1250 in the processor 1200. Among them, the first bus bars 1310 to 1340 are, for example, slot slots, and the second bus bars 1410 to 1480 are, for example, slimline slots. The storage media 1500A~1500D are inserted in the first bus bars 1310~1340, and the storage media 1500E~1500L are inserted in the second bus bars 1410~1480. Although in the configuration in FIG. 1, the first bus bars 1310 to 1340 are located on the left and the second bus bars 1410 to 1480 are located on the right, those skilled in the art should understand that the configuration is not limited by the present invention.

Please refer to FIG. 2, which is a schematic diagram of a server system architecture according to another embodiment of the present invention. As shown in FIG. 2, compared with the server system 1000 in FIG. 1, the server system 1000-1 in this embodiment further has a storage media controller (AROC) 1600 disposed on the main board 1100 and electrically connected to it. The platform path controller 1250 in the device 1200. The processor 1200 accesses the storage medium through the storage medium controller 1600. The storage medium controller 1600 can be electrically connected to a hard disk backplane 3000 other than the server system 1000-1, and is responsible for handling the access to the storage medium on the hard disk backplane 3000.

In one embodiment, as shown in FIG. 2, the server system 1000-1 may further have a baseboard management controller (BMC) 1700 electrically connected to the processor 1200.

2 again, the server system 1000-1 according to an embodiment of the present invention may further have a serial gigabit Ethernet interface (SGMII) 1800 electrically connected to the baseboard management controller 1700, and the baseboard management controller 1700 through Serial Gigabit Ethernet interface 1800 is used to send and receive signals.

In addition, in another embodiment, as shown in FIG. 2, the server system 1000-1 further has a first read-only storage medium 1910 and a second read-only storage medium 1920. The first read-only storage medium 1910 is electrically connected to the baseboard management controller 1700 for storing the firmware of the baseboard management controller. Therefore, when the server system 1000-1 is started, the baseboard management controller 1700 reads the firmware from the first read-only storage medium 1910 and executes the firmware to manage the server system 1000-1.

The second read-only storage medium 1920 is electrically connected to the baseboard management controller 1700, and stores the firmware of the basic input output system. Therefore, when the server system 1000-1 is activated, the baseboard management controller 1700 controls the basic input/output system chip (BIOS chip) of the server system 1000-1 to read from the second read-only storage medium 1920 Fetch and execute basic input output system firmware.

Please refer to FIG. 2 again, the server system 1000-1 according to another embodiment of the present invention may further have a complex programmable logic device (CPLD) 2000, which is electrically connected to the baseboard management controller 1700 and controls the server system 1000-1的时间。 The timing. The so-called timing here is not limited to the generation and frequency division of the clock signal. In this embodiment, the complex programmable logic device 2000 can be implemented as a built-in finite state machine (FSM), which switches the state according to the received signal, so that the baseboard management controller 1700 can be based on the current state. Decide how to control the operation of each component on the server system 1000-1. For example, when the server system 1000-1 has been powered, the status can be divided into startup, maintenance, normal, and sleep. In the activated state, the baseboard management controller 1700 needs to sequentially control the activation of the components of the server system 1000-1. In the maintenance state, the baseboard management controller 1700 needs to disable some components of the control server system 1000-1. In the sleep state, the baseboard management controller 1700 only maintains part of the necessary components of the server system 1000-1 in an enabled state to wait for a wakeup signal.

2 again, the server system 1000-1 according to another embodiment of the present invention may also have a remote system controller (advanced lights out manager, ALOM) 2100 disposed on the motherboard 1100 and electrically connected to the processor 1200 The platform path controller 1250 and the remote system controller 2100 have multiple network interfaces. Therefore, the server system 1000-1 can communicate with one or more external end users while communicating with the main controller of the server chassis, which greatly improves the communication capability of the server system.

As shown in FIG. 2, in another embodiment of the present invention, the server system 1000-1 may further have a power supply 2200 to provide power to the processor 1200 and the storage medium in a single output manner. In one embodiment, the power supply 2200 has an electronic fuse function (effuse). Therefore, when the server administrator maintains the server system 1000-1 and there are problems such as wrong power connection or reverse connection, the electronic fuse function of the power supply 2200 will work to avoid the power supply 2200 or the server system 1000- 1 Damaged.

In summary, in the server system of an embodiment of the present invention, by integrating the platform path controller into the processor, the motherboard reserves more space for other electronic components such as remote system controllers and storage media control. It increases the number of input and output ports or communication capabilities of the server system.

Although the present invention is disclosed in the foregoing embodiments, it is not intended to limit the present invention. All changes and modifications made without departing from the spirit and scope of the present invention fall within the scope of the patent protection of the present invention. For the scope of protection defined by the present invention, please refer to the attached scope of patent application.

1000, 1000-1. 1480‧‧‧Second bus 1500A~1500L‧‧‧Storage medium 1600‧‧‧Storage medium controller 1700‧‧‧Baseboard management controller 1800‧‧‧Gigabit Ethernet interface 1910, 1920‧‧‧ Reading storage media 2000‧‧‧Complex programmable logic device 2100‧‧‧Remote system controller 2200‧‧‧Power supply 3000‧‧‧Hard disk backplane

FIG. 1 is a schematic diagram of a server system architecture according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a server system architecture according to another embodiment of the present invention.

1000‧‧‧Server System

1100‧‧‧Motherboard

1200‧‧‧Processor

1210~1240‧‧‧Processing core

1250‧‧‧Platform Path Controller

1310~1340‧‧‧First bus

1410~1480‧‧‧Second bus

1500A~1500L‧‧‧Storage medium

Claims (9)

A server system includes: a motherboard; a processor disposed on the motherboard, including: a plurality of processing cores; and at least one platform controller hub (PCH) electrically connected to the processing cores; The first bus bar is disposed on the main board and electrically connected to the platform path controller; a plurality of second bus bars are disposed on the main board and electrically connected to the platform path controller; and a plurality of storage media, part of the storage media The storage media is inserted in the first bus bars, and the other part of the storage media is inserted in the second bus bars. For example, the server system of claim 1 further includes a storage medium controller (AROC) disposed on the motherboard and electrically connected to the platform path controller. For example, the server system of claim 1 further includes a baseboard management controller (BMC) electrically connected to the processor. For example, the server system of claim 3 further includes a serial gigabit Ethernet interface (SGMII) that is electrically connected to the baseboard management controller, and the baseboard management controller performs operations through the serial gigabit Ethernet interface Signal transmission and reception. For example, the server system of claim 3, the server system further includes: a first read-only storage medium, which is electrically connected to the baseboard management controller, and stores a baseboard management controller firmware; and a second read-only storage The medium is electrically connected to the baseboard management controller and stores a basic input output system firmware. For example, the server system of claim 5 further includes a complex programmable logic device (CPLD), which is electrically connected to the baseboard management controller to control the timing of the server system. For example, the server system of claim 1, further includes a remote system controller (advanced lights out manager, ALOM) disposed on the motherboard and electrically connected to the platform path controller, and the remote system controller includes multiple networks interface. For example, the server system of claim 1 further includes a power supply to provide power to the processor and the storage media in a single output manner. Such as the server system of claim 1, wherein the processor is a Naples processor (Naples®).

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