TWI718925B - Short-time pulse elimination circuit, voltage detection circuit and display driver chip - Google Patents

Abstract

The present invention mainly discloses a voltage detection circuit, which includes a voltage adjustment module, a hysteresis comparator circuit and a short-term pulse elimination circuit. Wherein, the voltage adjustment module is used to perform a voltage adjustment process on a first voltage signal provided by an external power source, and the hysteresis comparator circuit is used to eliminate the ripple noise of the first voltage signal . Moreover, the glitch cancellation circuit performs a glitch cancellation process on the first voltage signal according to a preset glitch cancellation time, thereby transmitting an output signal without ripple noise and glitches to the rear Level of circuit unit. In particular, the short-term pulse elimination circuit of the present invention has the advantages of automatic start, automatic stop, flexible setting of the short-term pulse elimination time, and low power consumption.

Description

Short-term pulse elimination circuit, voltage detection circuit and display driver chip

The present invention relates to the technical field of display driver chips, in particular to a short-term pulse elimination circuit and a voltage detection circuit, which are applied to eliminate short-term pulses and noise of the power supply voltage, so that the operating voltage supplied to the display driver chip does not occur The phenomenon of insufficient voltage or power failure.

Due to the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption and high response rate, OLED displays have been widely used in various electronic products, which can be further divided into PMOLED displays and AMOLED displays. Please refer to FIG. 1, which shows a structure diagram of a conventional AMOLED display device. As shown in FIG. 1, the conventional AMOLED display device includes: an AMOLED panel 1', a gate driving unit 2', a source driving unit 3', a control unit 4', and a stabilized power supply unit 5' . The current technology can already integrate the control unit 4', the gate drive unit 2'and the source drive unit 3'into a single display drive chip. In FIG. 1, the stabilized power supply unit 5'is coupled to a voltage source, such as a power source provided by a lithium battery, so as to provide a working voltage V _DD to the control unit 4', the gate driving unit 2'and the source The electrode driving unit 3'provides a light emitting operating voltage ELVDD and a grounding operating voltage ELVDD to the AMOLED panel 1'.

Practical operating phenomena show that when the AMOLED display device turns from the sleep standby state to the normal display state, the stabilized power supply unit 5'will power on each circuit unit included in the display driver chip again. However, in the short time when the light load is suddenly changed to heavy load, the working voltage V _DD , the light-emitting working voltage ELVDD and the ground working voltage ELVDD output by the regulated power supply unit 5'will inevitably be subject to transients (short-term) Pulse interference. On the other hand, the regulated power supply unit 5'usually includes a bandgap reference voltage generating unit, a boost converter, and a low-dropout regulator (LDO). It is known that low-dropout linear regulators (LDO) have the advantages of simple structure and small footprint, but the output voltage provided by the low-dropout linear regulators (LDO) often has the problem of ripple noise. It should be understood that the working voltage V _DD with ripple noise will affect the accuracy of the circuit operation of some specific circuit units, such as circuit units used to perform charge sampling, capacitance sampling, or current sampling.

On the other hand, the regulated power supply unit 5'is powered by an external power source (such as a lithium battery). However, it is well known that the lithium battery itself is not a stable voltage source, and its output voltage will increase with the consumption of the battery. Continuous decline. Once the voltage source is too low or abnormally powered down, the regulated power supply unit 5'will also fail to supply the correct working voltage V _DD , the light-emitting working voltage ELVDD, and the grounding operation due to the lack of normal power supply or starting voltage. Voltage ELVDD to the corresponding circuit unit.

In view of this, the improvement scheme adopted by the prior art is to add a voltage detection module to the display driver chip including the control unit 4', the gate drive unit 2'and the source drive unit 3'to pass the real-time voltage The detection method monitors whether the various working voltage sources provided by the stabilized power supply unit 5'have undervoltage or abnormal power failure. Unfortunately, practical applications have shown that when the monitored voltage signal has a large voltage ripple or short-term (transient) pulse, the conventional voltage detection module may experience detection errors.

Therefore, it can be seen from the above description that there is an urgent need for a new short-term pulse elimination circuit and a voltage detection circuit in this field.

The main purpose of the present invention is to provide a glitch elimination circuit applied to a display driver chip for performing a glitch elimination process on a power supply voltage provided to the display driver chip, and the glitch The elimination circuit has the advantages of automatic start, automatic stop, flexible setting of short-term pulse elimination time, and low power consumption.

Another object of the present invention is to provide a voltage detection circuit, which also includes the aforementioned short-term pulse elimination circuit of the present invention, for performing wide-range voltage monitoring and voltage adjustment on the power supply voltage provided to the display driver chip, while eliminating the The ripple noise and short-time pulse of the supply voltage have the advantages of low power consumption and flexible setting of the detection voltage threshold.

To achieve the above objective, the present invention proposes an embodiment of the glitch elimination circuit, which has an input signal receiving end and an output signal transmitting end, and includes:

A logic operation unit receives an input signal through the input signal receiving terminal, and an output signal is transmitted to the logic operation unit, so that the logic operation unit is used to perform at least one logic operation process on the input signal and the output signal After that, an oscillator enable signal is generated;

An oscillator, coupled to the oscillator enable signal transmitted by the logic operation unit, so as to generate a clock signal and return it to the logic operation unit;

A counter, coupled to the input signal and the clock signal transmitted by the logic operation unit, and after performing a cycle count on the clock signal, generates a cycle count data signal;

A pre-reference signal generating unit coupled to a cancellation time setting signal to generate a first pre-reference signal based on the cancellation time setting signal; wherein the cancellation time setting signal is generated according to the period count data signal; as well as

A glitch elimination unit is coupled to the first pre-reference signal transmitted by the pre-reference signal generating unit, the input signal, and the clock signal transmitted by the logic operation unit, and is used for The first pre-reference signal and the clock signal perform a short-term pulse elimination process on the input signal, thereby generating the output signal and transmitting it to the output signal transmission terminal.

In one embodiment, the aforementioned glitch cancellation circuit of the present invention further includes an output buffer unit, which is coupled to the output signal transmitted by the glitch cancellation unit, and is used to perform an output buffer on the output signal It will be output after processing.

In an embodiment, the logic operation unit includes:

A first OR gate, two input terminals of which are respectively coupled to the input signal and the output signal, and one of its output terminals transmits the oscillator enable signal to the oscillator; and

A second OR gate has two input terminals respectively coupled to the output signal and the clock signal transmitted by the oscillator, and one output terminal transmits the clock signal to the counter.

In one embodiment, the pre-reference signal generating unit is a multi-input and gate.

In one embodiment, the clock signal CLK has a first period, and the cancellation time setting signal has a second period. The second period is n times the first period, and n is a positive number.

In one embodiment, the aforementioned short-term pulse elimination circuit of the present invention further includes a controller coupled to the periodic count data signal transmitted by the counter, so as to generate the elimination time setting according to the periodic count data signal signal.

In an embodiment, the short-term pulse elimination unit includes:

A first D-type flip-flop with an enable signal receiving terminal, a clock signal receiving terminal, a data signal receiving terminal, and a signal output terminal, and the enable signal receiving terminal, the clock signal The receiving end and the data signal receiving end are respectively coupled to the input signal, the clock signal, and the first pre-reference signal, thereby outputting the first pre-reference signal as a signal based on the clock signal and the input signal The second pre-reference signal;

An inverter, coupled to the clock signal, and after performing an inversion process on the clock signal, output an inverted clock signal;

A second D-type flip-flop with an enable signal receiving terminal, a clock signal receiving terminal, a data signal receiving terminal, and a signal output terminal, and the enable signal receiving terminal, the clock signal The receiving end and the data signal receiving end are respectively coupled to the input signal, the inverted clock signal, and the second pre-reference signal, so that the second pre-reference signal is converted based on the inverted clock signal and the input signal. Output as a third pre-reference signal; and

An inverter is coupled to the second pre-reference signal and the third pre-reference signal with its two input terminals, and the output signal is transmitted through one of its output terminals.

The present invention also provides a voltage detection circuit, which includes:

A voltage adjustment module, coupled to a first voltage signal transmitted by a power source, for performing a boost process on the first voltage signal when the first voltage signal is lower than a first threshold voltage , And when the first voltage signal is higher than a second threshold voltage, perform a step-down process on the first voltage signal;

A hysteresis comparator circuit, the two input terminals of which are respectively coupled to a second voltage signal and a reference voltage signal transmitted by the voltage adjustment module; and

As mentioned above, the glitch elimination circuit of the present invention uses its input signal receiving end to couple the input signal transmitted by the hysteresis comparator, so as to transmit the output through its output signal transmitting end. signal.

In one embodiment, the hysteresis comparator circuit includes a Schmidt trigger with hysteresis characteristics.

The present invention also provides a display driver chip, which uses the voltage detection circuit of the present invention as described above to perform voltage adjustment on a supply voltage, and is used to eliminate short-term pulses and ripple noise of the supply voltage.

In order to enable your reviewer to further understand the structure, features, purpose, and advantages of the present invention, the drawings and detailed descriptions of preferred specific embodiments are attached as follows.

The short-term pulse elimination circuit of the present invention is used to determine whether to generate an output pulse signal according to the pulse width of an input pulse signal, and its principle is that the short-term pulse elimination circuit drives a pulse signal according to a starting edge of the input pulse signal. The disabling oscillator and a counter count a predetermined time, and when the counter reaches the predetermined time, the glitch elimination circuit will perform the following operations: disable the disabling oscillator; and The output pulse signal starts to be generated when the input pulse signal is at a high level, and the output pulse signal is not generated when the input pulse signal is at a low level.

FIG. 2 shows a circuit structure diagram of a voltage detection circuit of the present invention. The voltage detection circuit 1 of the present invention is mainly used to perform voltage monitoring on a supply voltage, eliminate short-term (transient) pulses of the supply voltage, and filter out ripple noise of the supply voltage. In more detail, the power supply voltage is transmitted from a power supply unit (such as a lithium battery) to a display driver chip, such as the display driver chip of an AMOLED display panel. The display driver chip includes a control unit and a gate driver. Unit and a source drive unit. The voltage detection circuit 1 of the present invention can be integrated into the display driver chip, so as to perform voltage monitoring inside the display driver chip. In addition, in a possible embodiment, the voltage detection circuit 1 of the present invention can be coupled between the power supply voltage and the display driver chip, so that the power supply voltage is monitored before the display driver chip receives the power supply voltage. , Eliminate short-term (transient) pulses of the supply voltage, and filter out the ripple noise of the supply voltage.

As shown in FIG. 2, the voltage detection circuit 1 of the present invention mainly includes: a voltage adjustment module 11, a hysteresis comparator circuit 12 and a short-term pulse elimination circuit 13. Wherein, the voltage adjustment module 11 is coupled to a first voltage signal V _DET transmitted by an external power source, and is used to perform the first voltage signal V _{DET when the first voltage signal V DET is} lower than a first threshold voltage. The voltage signal V _DET performs a step-up process, and when the first voltage signal V _{DET is} higher than a second threshold voltage, a step-down process is performed _{on the first voltage signal V DET.} In other words, when _{the voltage value of the first voltage signal V DET} is too high or too low and exceeds the voltage input range of the subsequent hysteresis comparator circuit 12, the voltage adjustment module 11 responds to the first voltage The signal V _DET performs step-down processing or step-up processing, so as to provide a second voltage signal V _DET2 that meets the voltage input range to the hysteresis comparator circuit 12.

In more detail, when the _{voltage value of the first voltage signal V DET} is relatively high, the voltage adjustment module 11 can use the voltage dividing resistor unit to decrease the first voltage signal V _DET according to a specific ratio. Conversely, when the voltage value of the first voltage signal V _DET is low, the voltage adjustment module 11 uses a voltage regulator to increase the first voltage signal V _DET according to a specific ratio. It can be seen from the foregoing description that _{the ratio between the second voltage signal V DET2} and the first voltage signal V _DET can be expressed by the following mathematical formula: V _DET /V _DET2 =ΔV _DET /ΔVD _ET2 =K.

In one embodiment, the hysteresis comparator circuit 12 of the voltage detection circuit 1 of the present invention includes a Schmitt trigger with hysteresis characteristics. As shown in FIG. 2, the two input terminals of the hysteresis comparator circuit 12 are respectively coupled to a second voltage signal V _DET2 and a reference voltage signal V _REF transmitted by the voltage adjustment module 11. When the voltage detection circuit 1 of the present invention is integrated inside a display driver chip, the reference voltage signal V _{REF is} provided by a reference voltage generating circuit inside the display driver chip. Electronic engineers should know that the Schmitt trigger with hysteresis characteristics can be obtained by adding an inverting input comparator and a positive feedback network. In this way, when the voltage value of the input signal of the hysteresis comparator circuit 12 (that is, the second voltage signal V _DET2 transmitted by the voltage adjustment module 11) exceeds the upper threshold voltage of the Schmitt trigger with hysteresis characteristics ( When Voltage of upper threshold, V _UT ) or lower threshold voltage (Voltage of lower threshold, V _LT ), the hysteresis comparator circuit 12 outputs a square wave signal, so it is also called a waveform shaping circuit, which can effectively remove its input signal (That is, the second voltage signal V _DET2 transmitted by the voltage adjustment module 11) has ripple noise.

Continue to refer to Figure 2 and refer to Figures 3 and 4 at the same time. Among them, FIG. 3 is a block diagram of a glitch elimination circuit of the present invention, and FIG. 4 is a circuit structure diagram of the glitch elimination circuit of the present invention. As shown in FIGS. 2, 3, and 4, the glitch elimination circuit 13 of the present invention has an input signal receiving terminal 13I and an output signal transmitting terminal 13T, and the input signal receiving terminal 13I is coupled by the An input signal IN (that is, a comparator output signal COMP) transmitted by the hysteresis comparator 12. Moreover, after performing a glitch elimination process on the input signal IN, the glitch elimination circuit 13 of the present invention transmits an output signal OUT to a subsequent circuit unit, such as a display driver, through its output signal transmission terminal 13T. The control unit, gate drive unit and source drive unit inside the chip, and the AMOLED panel outside the display drive chip.

As shown in FIGS. 3 and 4, the glitch elimination circuit 13 of the present invention includes: a logic operation unit 131, an oscillator 132, a counter 133, a pre-reference signal generation unit 134, and a glitch elimination unit 135, an output buffer unit 136, and a controller 137. According to the design of the present invention, the logic operation unit 131 receives an input signal IN (that is, the comparator output signal COMP) through the input signal receiving terminal 13I, and a fourth pre-reference signal S_4 is sent to the logic operation The unit 131 uses the logic operation unit 131 to generate an oscillator enable signal EN_OSC after performing at least one logic operation process on the input signal IN and the fourth pre-reference signal S_4. It is supplemented that, in a possible embodiment, the glitch elimination circuit 13 of the present invention may not include the output buffer unit 136 for performing an output buffer (inversion) process for the fourth pre-reference signal S_4. In this case, the fourth pre-reference signal S_4 is directly output through the output signal transmission terminal 132 as an output signal OUT for transmission to the subsequent circuit unit.

In more detail, the logic operation unit 131 is composed of a first OR gate 1311 and a second OR gate 1312. The first OR gate 1311 has two input terminals respectively coupled to the input signal IN and the fourth pre-reference signal S_4, and one output terminal transmits the oscillator enable signal EN_OSC to the oscillator 132. In addition, the second OR gate 1312 has its two input terminals respectively coupled to the fourth pre-reference signal S_4 and the clock signal CLK transmitted by the oscillator 132, and one of its output terminals transmits the clock signal CLK to the Counter 133. On the other hand, as shown in FIG. 3 and FIG. 4, the oscillator 132 is coupled to the oscillator enable signal EN_OSC transmitted by the logic operation unit 131, thereby generating a clock signal CLK that is transmitted back to the logic operation unit 131 . The counter 133 is coupled to the input signal IN and the clock signal CLK transmitted by the logic operation unit 131, and after performing a cycle count on the clock signal CLK, a cycle count data signal CK<N:0> is generated and transmitted To the controller 137, the controller 137 generates a elimination time setting signal nT according to the received cycle count data signal CK<N:0>. In one embodiment, the clock signal CLK has a first period T, and the cancellation time setting signal nT has a second period. The second period is n times the first period, and n is a positive number. In other words, the value of n can be determined by the controller 137, and after the value of the first period of the clock signal CLK is obtained through the period count data signal CK<N:0>, the cancellation time setting signal is generated nT is transmitted to the pre-reference signal generating unit 134.

In one embodiment, the pre-reference signal generating unit 134 is a multi input AND gate, which is coupled to the cancellation time setting signal nT transmitted by the controller 137, so as to be based on the cancellation time The signal nT is set to generate a first pre-reference signal S_1. 3 and 4 also show that the glitch elimination unit 135 is coupled to the first pre-reference signal S_1 transmitted by the pre-reference signal generating unit 134, the input signal IN, and the logic operation unit The clock signal CLK transmitted by 131 further performs a glitch elimination process on the input signal IN based on the first pre-reference signal S_1 and the clock signal CLK, thereby generating the fourth pre-reference signal S_4 It is transmitted to the output signal transmission terminal 13T.

In particular, the present invention uses a first D-type flip-flop 1351, an inverter 1352, a second D-type flip-flop 1353, and an inverter 1354 to form the short-term pulse elimination unit 135. As shown in FIG. 4, the first D-type flip-flop 1351 has an enable signal receiving terminal (EN), a clock signal receiving terminal (CLK), a data signal receiving terminal (D), and a signal output terminal ( Q), and the enable signal receiving end, the clock signal receiving end, and the data signal receiving end are respectively coupled to the input signal IN, the clock signal CLK and the first pre-reference signal S_1, Therefore, the first pre-reference signal S_1 is output as a second pre-reference signal S_2 based on the clock signal CLK and the input signal IN. 4 also shows that the inverter 1352 is coupled to the clock signal CLK, and after performing an inversion process on the clock signal CLK, outputs an inverted clock signal CK_IN. On the other hand, the second D-type flip-flop 1353 also has an enable signal receiving terminal (EN), a clock signal receiving terminal (CLK), a data signal receiving terminal (D), and a signal output terminal (Q ), and the enable signal receiving end, the clock signal receiving end, and the data signal receiving end are respectively coupled to the input signal IN, the inverted clock signal CK_IN, and the second pre-reference signal S_2, Therefore, the second pre-reference signal S_2 is output as a third pre-reference signal S_3 based on the inverted clock signal CK_IN and the input signal IN. Further, the inverter 1354 has its two input terminals respectively coupled to the second pre-reference signal S_2 and the third pre-reference signal S_3, and one of its output terminals transmits the fourth pre-reference signal S_4 . Finally, the output buffer unit 136 is coupled to the fourth pre-reference signal S_4 transmitted by the glitch elimination unit 135, so as to output an output after performing an output buffering process on the fourth pre-reference signal S_4 Signal OUT.

5 shows a working timing diagram of the voltage detection circuit 1 of the present invention shown in FIG. 2, and FIG. 6 shows a working timing diagram of the short-term pulse elimination circuit 13 of the present invention shown in FIG. 3. As shown in FIGS. 2 and 5, after being coupled to a first voltage signal V _DET transmitted by a power source, the voltage adjustment module 11 adjusts the first voltage signal V _DET to a second voltage signal V _DET2 . It can be found from FIG. 5 that the first voltage signal V _{DET has} a short-term pulse T _{pulse , and the pulse} width of the short-term pulse T pulse is less than 10 μs. It is worth noting that after the voltage adjustment of the voltage adjustment module 11, the output second voltage signal V _DET2 still carries the short-time pulse T _pulse . Further, after receiving the reference voltage signal V _REF and the second voltage signal V _DET2 , the hysteresis comparator circuit 12 transmits a comparator output signal COMP as one of the input signals IN of the subsequent glitch cancellation circuit 13. _{Similarly, the short-term pulse T pulse} can still be seen on the signal waveform of the input signal IN.

As shown in FIGS. 4 and 6, after receiving the input signal IN, the logic operation unit 131 generates an oscillator enable signal EN_OSC and transmits it to the oscillator 132 to prompt the oscillator 132 to generate a clock correspondingly. The signal CLK is returned to the logic operation unit 131. Further, when the input signal IN is at a high level for more than nT, that is, the clock signal CLK of the oscillator 132 has been continuously transmitted for n cycles, at this time the first pre-reference signal S_1, the second pre-reference signal S_2, Both the third pre-reference signal S_3 and the fourth pre-reference signal S_4 are triggered to transition. It can be seen from the working timing diagram that the first pre-reference signal S_1, the second pre-reference signal S_2, and the third pre-reference signal S_3 all turn from low to high, and the fourth pre-reference signal S_4 Turn from high level to low level. In this case, the logic operation unit 131 will turn the oscillator enable signal EN_OSC from a high level to a low level based on the input signal IN and the fourth pre-reference signal S_4.

That is to say, after setting the value of n through the controller 137, the short-term pulse elimination circuit 13 of the present invention will only trigger an action when the input signal IN is high for more than nT, and will trigger when the input signal IN is When the high level time is less than nT, the operation will stop automatically. It can be seen from this that the short-term pulse elimination circuit 13 of the present invention has an automatic start/stop function, and thus has the advantage of low power consumption. Moreover, it can be clearly seen from the working timing diagram of FIG. 5 that the output signal OUT provided by the output signal transmission terminal 13T of the glitch elimination circuit 13 of the present invention does not contain any glitches in its signal waveform. Simply put, after receiving an input signal IN, the glitch cancellation circuit 13 of the present invention performs a glitch cancellation on the input signal IN, and then provides an output signal OUT without any glitches. Level circuit unit.

In this way, the above has completely and clearly explained a short-time pulse elimination circuit and a voltage detection circuit of the present invention; and from the above, it can be seen that the present invention has the following advantages:

(1) The present invention discloses a glitch elimination circuit, which is applied to a display driver chip for performing a glitch elimination process on a power supply voltage provided to the display driver chip, and the glitch The elimination circuit has the advantages of automatic start, automatic stop, flexible setting of short-term pulse elimination time, and low power consumption.

(2) The present invention also provides a voltage detection circuit, which includes the aforementioned short-term pulse elimination circuit of the present invention, which is used to perform wide-range voltage monitoring and voltage adjustment on the power supply voltage provided to the display driver chip, while eliminating the power supply voltage. Ripple noise and short-time pulses, with low power consumption, flexible setting of detection voltage threshold and other advantages.

It must be emphasized that the foregoing disclosures in this case are preferred embodiments, and any partial changes or modifications that are derived from the technical ideas of this case and are easily inferred by those who are familiar with the art will not deviate from the patent of this case. Right category.

In summary, regardless of the purpose, means and effects of this case, it is shown that it is very different from the conventional technology, and its first invention is practical, and it does meet the patent requirements of the invention. I implore the examiner to check it out and grant the patent as soon as possible. Society is for the best prayer.

<The present invention>

1: Voltage detection circuit

11: Voltage adjustment module

12: Hysteresis comparator circuit

13: Short-time pulse elimination circuit

13I: Input signal receiver

13T: Output signal transmission terminal

131: Logic Operation Unit

1311: first or gate

1312: second or gate

132: Oscillator

133: Counter

134: Front reference signal generation unit

135: Short-time pulse elimination unit

1351: The first D-type flip-flop

1352: inverter

1353: Second D-type flip-flop

1354: reverse and gate

136: output buffer unit

137: Controller

＜Acquaintances＞

1’: AMOLED panel

2’: Gate drive unit

3’: Source drive unit

4’: Control unit

5’: Regulated power supply unit

Fig. 1 is a structure diagram of a conventional AMOLED display device; Fig. 2 is a circuit structure diagram of a voltage detection circuit of the present invention; Fig. 3 is a block diagram of a short-term pulse elimination circuit of the present invention; Fig. 4 is the present invention Fig. 5 is a working timing diagram of the voltage detection circuit 1 of the present invention shown in Fig. 2; and Fig. 6 is a diagram of the glitch elimination circuit 13 of the present invention shown in Fig. 3 Working sequence diagram.

1: Voltage detection circuit

11: Voltage adjustment module

12: Hysteresis comparator circuit

13: Short-time pulse elimination circuit

13I: Input signal receiver

13T: Output signal transmission terminal

Claims (10)

A short-term pulse elimination circuit has an input signal receiving terminal and an output signal transmitting terminal, and includes: A logic operation unit receives an input signal through the input signal receiving terminal, and an output signal is transmitted to the logic operation unit, so that the logic operation unit is used to perform at least one logic operation process on the input signal and the output signal After that, an oscillator enable signal is generated; An oscillator, coupled to the oscillator enable signal transmitted by the logic operation unit, so as to generate a clock signal and return it to the logic operation unit; A counter, coupled to the input signal and the clock signal transmitted by the logic operation unit, and after performing a cycle count on the clock signal, generates a cycle count data signal; A pre-reference signal generating unit coupled to a cancellation time setting signal to generate a first pre-reference signal based on the cancellation time setting signal, wherein the cancellation time setting signal is generated according to the period count data signal; and A glitch elimination unit, coupled to the first pre-reference signal transmitted by the pre-reference signal generating unit, the input signal, and the clock signal transmitted by the logic operation unit, and which is used for The first pre-reference signal and the clock signal perform a short-term pulse elimination process on the input signal, thereby generating the output signal to be transmitted to the output signal transmission terminal. The glitch elimination circuit described in the first item of the scope of the patent application further includes an output buffer unit for coupling to the output signal transmitted by the glitch elimination unit and performing an output buffer on the output signal It will be output after processing. For example, in the short-term pulse elimination circuit described in item 1 of the scope of patent application, the pre-reference signal generating unit is a multi-input and gate, and the logic operation unit includes: A first OR gate, two input terminals of which are respectively coupled to the input signal and the output signal, and one of its output terminals transmits the oscillator enable signal to the oscillator; and A second OR gate has two input terminals respectively coupled to the output signal and the clock signal transmitted by the oscillator, and one output terminal transmits the clock signal to the counter. According to the glitch elimination circuit described in claim 1, wherein the clock signal has a first period, and the elimination time setting signal has a second period, and the second period is n of the first period. Times, n is a positive integer. The short-term pulse elimination circuit described in item 1 of the scope of patent application further includes a controller, which is coupled to the periodic count data signal transmitted by the counter, so as to generate the elimination time according to the periodic count data signal Set the signal. The short-term pulse elimination circuit described in item 1 of the scope of patent application, wherein the short-term pulse elimination unit includes: A first D-type flip-flop with an enable signal receiving terminal, a clock signal receiving terminal, a data signal receiving terminal and a signal output terminal, and the enable signal receiving terminal and the clock signal receiving terminal Terminal, and the data signal receiving terminal are respectively coupled to the input signal, the clock signal and the first pre-reference signal, thereby outputting the first pre-reference signal as a first reference signal based on the clock signal and the input signal Two front reference signals; An inverter, coupled to the clock signal, and output an inverted clock signal after performing an inversion process on the clock signal; A second D-type flip-flop has an enable signal receiving terminal, a clock signal receiving terminal, a data signal receiving terminal, and a signal output terminal, and the enable signal receiving terminal, the clock signal The receiving end and the data signal receiving end are respectively coupled to the input signal, the inverted clock signal, and the second pre-reference signal, so that the second pre-reference signal is converted based on the inverted clock signal and the input signal. Output as a third pre-reference signal; and An inverter is coupled to the second pre-reference signal and the third pre-reference signal with its two input terminals, and the output signal is transmitted through one of its output terminals. A short-time pulse elimination circuit is used to determine whether to generate an output signal according to the pulse width of an input signal, and is characterized by: Driving a disableable oscillator and a counter to count a predetermined time according to a starting edge of the input signal; and When the counter reaches the predetermined time, the disabling oscillator is disabled and the output signal is generated when the input signal is at a high level, and the output signal is not generated when the input signal is at a low level . A voltage detection circuit, comprising: a voltage adjustment module, coupled to a first voltage signal transmitted by a power source, for performing the first voltage signal when the first voltage signal is lower than a first threshold voltage The voltage signal performs a step-up process, and when the first voltage signal is higher than a second threshold voltage, a step-down process is performed on the first voltage signal; a hysteresis comparator circuit, the two input terminals of which are respectively coupled Is connected to a second voltage signal and a reference voltage signal transmitted by the voltage adjustment module, and its output terminal is used to provide the input signal; and as described in any one of items 1 to 7 of the scope of the patent application The short-time pulse elimination circuit described. The voltage detection circuit described in item 8 of the scope of patent application, wherein the hysteresis comparator circuit includes a Schmitt trigger with hysteresis characteristics. A display driver chip uses the voltage detection circuit as described in any one of items 8 to 9 of the scope of patent application to perform voltage adjustment on a supply voltage to eliminate short-term pulses and ripple noise of the supply voltage.

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