TWI696338B - Boost power converter capable of quickly responding to input voltage changes and electronic equipment using the same - Google Patents

Abstract

A boost power converter capable of quickly responding to input voltage changes has an energy transfer unit for periodically charging an input voltage to an inductor and discharging the inductor to an output terminal under the control of a PWM signal To generate an output voltage, the inductor has an equivalent inductance and an inductance parasitic resistance connected in series with it; a ramp signal generating unit for modulating a ramp signal according to a voltage across the inductor; and an error averaging circuit for Generating an error average voltage based on the average value of the difference between a feedback voltage of the output voltage and a reference voltage; and a PWM signal generating unit for determining the PWM signal based on the comparison result of the ramp signal and the error average voltage Starting point.

Description

Boost power converter capable of quickly responding to input voltage changes and electronic equipment using the same

The invention relates to a boost power converter, in particular to a boost power converter capable of quickly responding to changes in input voltage.

Please refer to FIG. 1, which illustrates a circuit diagram of a conventional boost power converter. As shown in FIG. 1, the boost power converter has an input capacitor 11, an inductor 12a and an inductive parasitic resistance 12b, an NMOS transistor 13a, a PMOS transistor 13b, a first voltage dividing resistor 14a and a second Voltage dividing resistor 14b, an output capacitor 15, a ramp signal generating unit 16, a transconductance amplifier 17, a filter resistor 18a and a filter capacitor 18b, a comparator 19, an oscillator 20, a flip-flop 21 and a PWMControl drive unit 22.

The input capacitor 11 is used to provide a filtering function at the input terminal.

The inductance 12a is connected in series with the inductance parasitic resistance 12b to represent an actual inductance.

The NMOS transistor 13a is used to turn on according to the control of the PWM control driving unit 22 to charge the inductor 12a with an input voltage V _IN during a PWM period of charging (ON).

The PMOS transistor 13b is used to turn on according to the control of the PWM control driving unit 22 to discharge the inductor 12a to the output terminal during the discharge period (OFF) of a PWM period.

The first voltage dividing resistor 14a and the second voltage dividing resistor 14b are used to form a voltage dividing circuit to generate a feedback voltage V _FB according to a ratio of the output voltage V _OUT established on the output capacitor 15.

The ramp signal generating unit 16 is used to generate a ramp signal V _RAMP .

The transconductance amplifier 17, the filter resistor 18a and the filter capacitor 18b are used to form an error average circuit to generate an error average voltage V _EA based on the average value of the difference between the feedback voltage V _FB and a reference voltage V _REF .

The comparator 19 is used to generate a charge start signal CHGON according to the comparison result of the ramp signal V _RAMP and the error average voltage V _EA .

The oscillator 20 is used to generate a clock signal CLK.

The flip-flop 21 is used to generate a PWM signal. The starting point of the charging period of the PWM signal is determined by the charging start signal CHGON, and the ending point of the charging period is determined by the clock signal CLK.

The PWM control driving unit 22 is used to generate a first switch signal SW1 according to the PWM signal to control the NMOS transistor 13a and a second switch signal SW2 to control the PMOS transistor 13b.

At steady state, the error average voltage V _EA will approach the DC level to determine one of the duty cycles of the PWM signal, so that the output voltage V _OUT = (1+R1/R2)V _REF , where R1 is the first division The resistance value of the piezoresistor 14a, R2 is the resistance value of the second voltage-dividing resistor 14b.

However, when the input voltage V _IN changes and jumps and the output current does not change suddenly, because the feedback path of the conventional circuit needs to pass through the voltage divider circuit and the error averaging circuit, the filter capacitor 18b of the error averaging circuit has a capacitance value The transduction amplifier 17 is relatively large and the transduction gain of the transconductance amplifier 17 is limited. Therefore, the conventional circuit must wait for a reaction time (on the order of tens of microseconds) to change the error average voltage V _EA to a new corresponding level to Generate a new duty cycle for the PWM signal, thereby pulling the output voltage V _OUT back to a predetermined level, and the output voltage V _OUT may have changed greatly (overshoot or undershoot) during the reaction time , And often exceeds the scope required by the specifications (SPEC). The whole process can be simply described as:

V _IN →V _OUT →V _FB →V _EA →CHGON→PWM→V _OUT

In order to solve the above problems, a novel boost power converter architecture is urgently needed in the art.

An object of the present invention is to provide a boost power converter that can quickly respond to changes in input voltage and reduce the amount of change in output voltage.

Another object of the present invention is to provide a boost power converter that can quickly change the duty cycle of a PWM signal by adjusting the slope of a ramp signal through the voltage across an inductor, so that an output voltage can respond quickly Changes in input voltage.

Another object of the present invention is to provide a boost power converter that can automatically measure the parasitic resistance value of an inductor at the initial stage of power-on to determine the resistance value in a resistance-capacitance compensation circuit.

To achieve the aforementioned objective, a boost power converter capable of quickly responding to changes in input voltage is proposed, which has:

An inductance with an equivalent inductance and an inductance parasitic resistance in series with it;

An NMOS transistor, which is used to control conduction according to a first switching signal to charge an input voltage to the inductor during a charging period of a PWM cycle;

A PMOS transistor for conducting according to the control of a second switching signal to discharge the inductor to an output terminal during the discharge period of the PWM period;

A voltage divider circuit for generating a feedback voltage according to a ratio of an output voltage established on an output capacitor;

A ramp signal generating unit for modulating a ramp signal according to a voltage across the inductor;

An error averaging circuit for generating an error average voltage based on the average value of the difference between the feedback voltage and a reference voltage;

A comparator for generating a charging start signal according to the comparison result of the ramp signal and the error average voltage V _EA ;

An oscillator is used to generate a clock signal;

A flip-flop is used to generate a PWM signal, wherein the starting point of the charging period of the PWM signal is determined by the charging start signal, and the ending point of the charging period is determined by the clock signal ;

A PWM control driving unit is used to generate the first switching signal according to the PWM signal to control the NMOS transistor and the second switching signal to control the PMOS transistor.

In an embodiment, the ramp signal generating unit has a certain current source, a switch, a first capacitor, a second capacitor, a transconductance amplifier, a first resistor, and a second resistor; its features are:

The constant current source is coupled between the input voltage and an upper electrode of the first capacitor to provide a certain current, and the first resistor is coupled between a lower electrode of the first capacitor and a reference ground. The channel of the switch is connected in parallel with the first capacitor, and the control terminal of the switch is coupled to a reset signal;

The second capacitor and the second resistor form a series circuit, and the series circuit is connected in parallel with the inductor, wherein the second capacitor and the second resistor are based on a formula: L/R _DCR = R _AUX ∙ C _AUX determines its value, where L is the equivalent inductance of the inductor, R _{DCR is} the resistance value of the parasitic resistance of the inductor, R _{AUX is} the resistance value of the second resistance, and C _{AUX is} the capacitance value of the second capacitor;

The input port of the transconductance amplifier is coupled to the second capacitor, and the output terminal is coupled to the lower electrode of the first capacitor;

During operation, the reset signal periodically resets the voltage across the first capacitor to zero to periodically generate the ramp signal.

In one embodiment, the ramp signal generating unit has a certain current source, a first switch, a first capacitor, a second capacitor, a transconductance amplifier, a first resistor, a control module, and a plurality of second The switch, a plurality of compensation resistors, a third switch and a measuring current source are characterized by:

The constant current source is coupled between the input voltage and an upper electrode of the first capacitor to provide a certain current, and the first resistor is coupled between a lower electrode of the first capacitor and a reference ground. The channel of the first switch is connected in parallel with the first capacitor, and the control terminal of the first switch is coupled to a reset signal;

The configuration of the second capacitor and one of the plurality of compensation resistors forms a series circuit, and the series circuit is connected in parallel with the inductor, wherein the equivalent resistance of the second capacitor and the configuration is based on a formula: L/R _DCR = R _AUX ∙C _AUX determines its value, where L is the equivalent inductance of the inductor, R _{DCR is} the resistance value of the parasitic resistance of the inductor, R _AUX is the resistance value of the equivalent resistance, and C _AUX is The capacitance value of the second capacitor, and the configuration is formed in such a way that, immediately after power-on, the control module outputs a plurality of switching signals to power on the measurement current source and make the plurality of compensation resistors Short circuit, the trans-voltage of the inductive parasitic resistance is converted into a current through the transconductance amplifier, and then the current will generate a trans-voltage across the first resistor; the control module calculates the resistance value of the inductive parasitic resistance according to the trans-voltage ; And the control module determines a number of the plurality of switching signals according to the resistance value R _DCR so that the plurality of compensation resistors form the configuration and disconnect the measurement current source; and

The input port of the transconductance amplifier is coupled to the second capacitor, and the output terminal is coupled to the lower electrode of the first capacitor;

During operation, the reset signal periodically resets the voltage across the first capacitor to zero to periodically generate the ramp signal.

To achieve the above objective, the present invention further provides a boost power converter capable of quickly responding to changes in input voltage, which has:

An energy transfer unit for periodically charging an input voltage to an inductor and discharging the inductor to an output terminal under the control of a PWM signal to generate an output voltage, the inductor having an equivalent inductance and its series connection One of the inductive parasitic resistance;

A ramp signal generating unit for modulating a ramp signal according to a voltage across the inductor;

An error averaging circuit for generating an error average voltage based on the average value of the difference between a feedback voltage of the output voltage and a reference voltage; and

A PWM signal generating unit is used to determine the starting point of the PWM signal according to the comparison result of the ramp signal and the error average voltage.

To achieve the above objective, the present invention further provides an electronic device having a boost power converter and an information processing circuit, wherein the boost power converter is used to generate an output voltage according to an input voltage to respond to the information The processing circuit is powered, and the boost power converter has:

An inductance with an equivalent inductance and an inductance parasitic resistance in series with it;

An NMOS transistor for controlling conduction according to a first switching signal to charge the inductor with the input voltage during a charging period of a PWM cycle;

A PMOS transistor for conducting according to the control of a second switching signal to discharge the inductor to an output terminal during the discharge period of the PWM period;

A voltage divider circuit for generating a feedback voltage according to a ratio of the output voltage established on an output capacitor;

A ramp signal generating unit for modulating a ramp signal according to a voltage across the inductor;

An error averaging circuit for generating an error average voltage based on the average value of the difference between the feedback voltage and a reference voltage;

A comparator for generating a charging start signal according to the comparison result of the ramp signal and the error average voltage V _EA ;

An oscillator is used to generate a clock signal;

A flip-flop is used to generate a PWM signal, wherein the starting point of the charging period of the PWM signal is determined by the charging start signal, and the ending point of the charging period is determined by the clock signal ;

A PWM control driving unit is used to generate the first switching signal according to the PWM signal to control the NMOS transistor and the second switching signal to control the PMOS transistor.

In an embodiment, the ramp signal generating unit has a certain current source, a switch, a first capacitor, a second capacitor, a transconductance amplifier, a first resistor, and a second resistor; its features are:

The constant current source is coupled between the input voltage and an upper electrode of the first capacitor to provide a certain current, and the first resistor is coupled between a lower electrode of the first capacitor and a reference ground. The channel of the switch is connected in parallel with the first capacitor, and the control terminal of the switch is coupled to a reset signal;

The second capacitor and the second resistor form a series circuit, and the series circuit is connected in parallel with the inductor, wherein the second capacitor and the second resistor are based on a formula: L/R _DCR = R _AUX ∙ C _AUX determines its value, where L is the equivalent inductance of the inductor, R _{DCR is} the resistance value of the parasitic resistance of the inductor, R _{AUX is} the resistance value of the second resistance, and C _{AUX is} the capacitance value of the second capacitor;

The input port of the transconductance amplifier is coupled to the second capacitor, and the output terminal is coupled to the lower electrode of the first capacitor;

During operation, the reset signal periodically resets the voltage across the first capacitor to zero to periodically generate the ramp signal.

In one embodiment, the ramp signal generating unit has a certain current source, a first switch, a first capacitor, a second capacitor, a transconductance amplifier, a first resistor, a control module, and a plurality of second The switch, a plurality of compensation resistors, a third switch and a measuring current source are characterized by:

The constant current source is coupled between the input voltage and an upper electrode of the first capacitor to provide a certain current, and the first resistor is coupled between a lower electrode of the first capacitor and a reference ground. The channel of the first switch is connected in parallel with the first capacitor, and the control terminal of the first switch is coupled to a reset signal;

The configuration of the second capacitor and one of the plurality of compensation resistors forms a series circuit, and the series circuit is connected in parallel with the inductor, wherein the equivalent resistance of the second capacitor and the configuration is based on a formula: L/R _DCR = R _AUX ∙C _AUX determines its value, where L is the equivalent inductance of the inductor, R _{DCR is} the resistance value of the parasitic resistance of the inductor, R _AUX is the resistance value of the equivalent resistance, and C _AUX is The capacitance value of the second capacitor, and the configuration is formed in such a way that, immediately after power-on, the control module outputs a plurality of switching signals to power on the measurement current source and make the plurality of compensation resistors Short circuit, the trans-voltage of the inductive parasitic resistance is converted into a current through the transconductance amplifier, and then the current will generate a trans-voltage across the first resistor; the control module calculates the resistance value of the inductive parasitic resistance according to the trans-voltage ; And the control module determines a number of the plurality of switching signals according to the resistance value R _DCR so that the plurality of compensation resistors form the configuration and disconnect the measurement current source; and

The input port of the transconductance amplifier is coupled to the second capacitor, and the output terminal is coupled to the lower electrode of the first capacitor;

During operation, the reset signal periodically resets the voltage across the first capacitor to zero to periodically generate the ramp signal.

To achieve the above objective, the present invention further provides an electronic device having a boost power converter and an information processing circuit, wherein the boost power converter is used to generate an output voltage according to an input voltage to respond to the information The processing circuit is powered, and the boost power converter has:

An energy transfer unit for periodically charging an input voltage to an inductor and discharging the inductor to an output terminal under the control of a PWM signal to generate an output voltage, the inductor having an equivalent inductance and its series connection One of the inductive parasitic resistance;

A ramp signal generating unit for modulating a ramp signal according to a voltage across the inductor;

An error averaging circuit for generating an error average voltage based on the average value of the difference between a feedback voltage of the output voltage and a reference voltage; and

A PWM signal generating unit is used to determine the starting point of the PWM signal according to the comparison result of the ramp signal and the error average voltage.

In a possible embodiment, the electronic device may be a display, a smart phone, or a portable computer.

Please refer to FIG. 2, which illustrates a circuit diagram of an embodiment of a boost power converter capable of quickly responding to input voltage changes according to the present invention. As shown in FIG. 2, a boost power converter 100 has an input capacitor 101, an inductor 102a and an inductive parasitic resistance 102b, an NMOS transistor 103a, a PMOS transistor 103b, a first voltage dividing resistor 104a and a The second voltage divider 104b, an output capacitor 105, a ramp signal generating unit 106, a transconductance amplifier 107, a filter resistor 108a and a filter capacitor 108b, a comparator 109, an oscillator 110, a flip-flop 111 And a PWM control driving unit 112.

The input capacitor 101 is used to provide a filtering function at the input terminal.

The inductance 102a is connected in series with the inductance parasitic resistance 102b to represent an actual inductance.

The NMOS transistor 103a is used to turn on according to the control of the PWM control driving unit 112 to charge an inductor 102a with an input voltage V _IN during a PWM period of charging (ON).

The PMOS transistor 103b is used to turn on according to the control of the PWM control driving unit 112 to discharge the inductor 102a to the output terminal during the discharge period (OFF) of a PWM period.

The first voltage dividing resistor 104a and the second voltage dividing resistor 104b are used to form a voltage dividing circuit to generate a feedback voltage V _FB according to a ratio of the output voltage V _OUT established on the output capacitor 105.

The ramp signal generating unit 106 is used to generate a ramp signal V _RAMP , which includes a certain current source 106 a, a switch 106 b, a first capacitor 106 c, a second capacitor 106 d, a transconductance amplifier 106 e, a first resistor 106 f and A second resistor 106g.

Constant current source 106a coupled to the input line to provide a constant current I _C, the first resistance line 106f coupled between the first capacitor voltage V _IN 106c and 106c on one of the first electrode of the capacitor lower electrode and a reference ground of In the meantime, the channel of the switch 106b is connected in parallel with the first capacitor 106c, and the control terminal of the switch 106b is coupled to a reset signal RESET.

The second capacitor 106d and the second resistor 106g form a series circuit, and the series circuit is connected in parallel with the actual inductance (having the inductance 102a and the inductance parasitic resistance 102b connected in series therewith), wherein the second capacitor 106d and the second resistor 106g is determined by a formula: L/R _DCR = R _AUX ∙C _AUX determines its value, where L is the inductance value of the inductor 102a, R _DCR is the resistance value of the inductor parasitic resistance 102b, and R _AUX is the resistance value of the second resistor 106g , And C _AUX is the capacitance of the second capacitor 106d.

The input port of the transconductance amplifier 106e is coupled to the second capacitor 106d, and its output terminal is coupled to the lower electrode of the first capacitor 106c to provide an input voltage sensing current I _SENSE . During operation, the reset signal RESET periodically resets the voltage across the first capacitor 106c to zero, so that the ramp signal V _RAMP periodically generates an upward ramp voltage.

The transconductance amplifier 107, the filter resistor 108a and the filter capacitor 108b are used to form an error average circuit to generate an error average voltage V _EA according to the average value of the difference between the feedback voltage V _FB and a reference voltage V _REF .

The comparator 109 is used to generate a charge start signal CHGON according to the comparison result of the ramp signal V _RAMP and the error average voltage V _EA .

The oscillator 110 is used to generate a clock signal CLK.

The flip-flop 111 is used to generate a PWM signal, wherein the starting point of the charging period of the PWM signal is determined by the charging start signal CHGON, and the ending point of the charging period is determined by the clock signal CLK.

The PWM control driving unit 112 is used for generating a first switching signal SW1 according to the PWM signal to control the NMOS transistor 103a and a second switching signal SW2 to control the PMOS transistor 103b.

At steady state, the error average voltage V _EA will approach the DC level to determine one of the duty cycles of the PWM signal, so that the output voltage V _OUT = (1+R1/R2)V _REF , where R1 is the first division The resistance value of the piezoresistor 104a, R2 is the resistance value of the second voltage-dividing resistor 104b.

The present invention is characterized in that during the discharge (OFF) period of the PWM period, the ramp voltage of the ramp signal V _RAMP can be expressed as (I _C +I _SENSE ) ∙R _RAMP + I _C ∙t/C _RAMP , where R _RAMP is The resistance value of the first resistor 106f, C _RAMP is the capacitance value of the first capacitor 106c, and I _C /(R _RAMP ∙ C _RAMP )>-d I _SENSE /dt.

Accordingly, if there is any change in V _IN , the trans-voltage of the second capacitor 106d and the output current I _{SENSE of the} transconductance amplifier 106e will follow the change in sequence, thereby immediately reacting on V _RAMP to quickly adjust the duty cycle of PWM (or Duty cycle), so that the output voltage V _OUT can quickly respond to changes in V _IN . The whole process can be simply described as:

V _IN →V _RAMP →CHGON→PWM→V _OUT .

Please refer to FIG. 3, which illustrates a circuit diagram of another embodiment of the boost power converter of the present invention that can quickly respond to input voltage changes. As shown in FIG. 3, a boost power converter 100 has an input capacitor 101, an inductor 102a and an inductive parasitic resistance 102b, an NMOS transistor 103a, a PMOS transistor 103b, a first voltage dividing resistor 104a and a The second voltage divider 104b, an output capacitor 105, a ramp signal generating unit 106, a transconductance amplifier 107, a filter resistor 108a and a filter capacitor 108b, a comparator 109, an oscillator 110, a flip-flop 111 And a PWM control driving unit 112.

The input capacitor 101 is used to provide a filtering function at the input terminal.

The inductance 102a is connected in series with the inductance parasitic resistance 102b to represent an actual inductance.

The NMOS transistor 103a is used to turn on according to the control of the PWM control driving unit 112 to charge an inductor 102a with an input voltage V _IN during a PWM period of charging (ON).

The PMOS transistor 103b is used to turn on according to the control of the PWM control driving unit 112 to discharge the inductor 102a to the output terminal during the discharge period (OFF) of a PWM period.

The first voltage dividing resistor 104a and the second voltage dividing resistor 104b are used to form a voltage dividing circuit to generate a feedback voltage V _FB according to a ratio of the output voltage V _OUT established on the output capacitor 105.

The ramp signal generating unit 106 is used to generate a ramp signal V _RAMP , which includes a certain current source 106 a, a switch 106 b, a first capacitor 106 c, a second capacitor 106 d, a transconductance amplifier 106 e, a first resistor 106 f, A control module 106g1, n switches 106g2, n compensation resistors 106g3, a switch 106g4, and a measurement current source 106g5.

Constant current source 106a coupled to the input line to provide a constant current I _C, the first resistance line 106f coupled between the first capacitor voltage V _IN 106c and 106c on one of the first electrode of the capacitor lower electrode and a reference ground of In the meantime, the channel of the switch 106b is connected in parallel with the first capacitor 106c, and the control terminal of the switch 106b is coupled to a reset signal RESET.

The second capacitor 106d and one of the n compensation resistors 106g3 are configured to form a series circuit, and the series circuit is connected in parallel with the actual inductance (having an inductance 102a and an inductance parasitic resistance 102b connected in series therewith), wherein the second capacitor The equivalent resistance of 106d and the configuration is based on a formula: L/R _DCR = R _AUX ∙C _AUX determines its value, where L is the inductance value of the inductor 102a, R _DCR is the resistance value of the inductor parasitic resistance 102b, R _AUX for the equivalent resistance value of the resistor, and C _AUX is the capacitance of the second capacitor 106d. This configuration is formed so as: (1) when the boosting power converter 100 has just powered on, the switch control module 106g1 output signals _{S 0, S 1, S 2} ... S n with the measured power current source 106g5 And short-circuit n compensation resistors 106g3 to convert the trans-voltage of the inductive parasitic resistor 102b into a current through the transconductance amplifier 106e, and then the current will generate a trans-voltage across the first resistor 106f; (2) the control module 106g1 Calculate the resistance value R _DCR of the inductive parasitic resistance 102b across the voltage; (3) Then, the control module 106g1 can determine the number of one of the switching signals S ₁ , S ₂ ...S _n according to the resistance value R _DCR to make n compensation resistors 106g3 form the configuration, the switching signals S ₀ and outputting a disconnection to disconnect the level measured by the current source 106g5.

The input port of the transconductance amplifier 106e is coupled to the second capacitor 106d, and its output terminal is coupled to the lower electrode of the first capacitor 106c to provide an input voltage sensing current I _SENSE . During operation, the reset signal RESET periodically resets the voltage across the first capacitor 106c to zero, so that the ramp signal V _RAMP periodically generates an upward ramp voltage.

The transconductance amplifier 107, the filter resistor 108a and the filter capacitor 108b are used to form an error average circuit to generate an error average voltage V _EA according to the average value of the difference between the feedback voltage V _FB and a reference voltage V _REF .

The comparator 109 is used to generate a charge start signal CHGON according to the comparison result of the ramp signal V _RAMP and the error average voltage V _EA .

The oscillator 110 is used to generate a clock signal CLK.

The flip-flop 111 is used to generate a PWM signal, wherein the starting point of the charging period of the PWM signal is determined by the charging start signal CHGON, and the ending point of the charging period is determined by the clock signal CLK.

The PWM control driving unit 112 is used for generating a first switching signal SW1 according to the PWM signal to control the NMOS transistor 103a and a second switching signal SW2 to control the PMOS transistor 103b.

At steady state, the error average voltage V _EA will approach the DC level to determine one of the duty cycles of the PWM signal, so that the output voltage V _OUT =(1+R1/R2)V _REF , where R1 is the first division The resistance value of the piezoresistor 104a, R2 is the resistance value of the second voltage-dividing resistor 104b. In other words, the boost power converter of the present invention capable of quickly responding to changes in input voltage has an energy transfer unit for periodically charging an inductor with an input voltage and causing the inductor to be controlled by a PWM signal Discharging an output terminal to generate an output voltage, the inductor has an equivalent inductance and an inductance parasitic resistance in series with it; a ramp signal generating unit is used to modulate a ramp signal according to a voltage across the inductor; an error An averaging circuit for generating an error average voltage based on the average value of the difference between a feedback voltage of the output voltage and a reference voltage; and a PWM signal generating unit for comparing the ramp signal and the error average voltage Determine the starting point of the PWM signal.

According to the above description, the present invention further provides an electronic device. Please refer to FIG. 4, which illustrates a block diagram of an embodiment of an electronic device of the present invention. As shown in FIG. 4, an electronic device 200 has a boost power converter 210 and an information processing circuit 220 that can quickly respond to changes in the input voltage. The boost power converter 210 that can quickly respond to changes in the input voltage is described above The boost power converter 100 is implemented to generate an output voltage V _OUT according to an input voltage V _IN to supply power to the information processing circuit 220.

In addition, in a possible embodiment, the electronic device 200 may be a display, a smart phone, or a portable computer.

According to the above description, the present invention can provide the following advantages:

1. The boost power converter of the present invention can quickly respond to changes in input voltage and reduce the amount of change in output voltage.

2. The boost power converter of the present invention can rapidly change the duty cycle of a PWM signal by adjusting the slope of a ramp signal through an inductance across the voltage, so that an output voltage can quickly respond to changes in the input voltage.

3. The boost power converter of the present invention can automatically measure the parasitic resistance value of an inductor at the initial stage of power-on to determine the resistance value in a resistance-capacitance compensation circuit.

The disclosure of the present invention is one of the preferred embodiments. Any partial changes or modifications that originate from the technical idea of the present invention and are easily inferred by those skilled in the art will not deviate from the scope of the patent right of the present invention.

In summary, regardless of the purpose, means and effects of this case, it shows that it is very different from the conventional technology, and its first invention is practical and indeed meets the patent requirements of the invention. Society is for supreme prayer.

11: Input capacitance

12a: inductance

12b: Inductive parasitic resistance

13a: NMOS transistor

13b: PMOS transistor

14a: First voltage divider resistor

14b: Second voltage divider resistor

15: output capacitance

16: Ramp signal generation unit

17: Transduction amplifier

18a: filter resistor

18b: filter capacitor

19: Comparator

20: Oscillator

21: flip-flop

22: PWM control drive unit

100: Boost power converter

101: input capacitance

102a: inductance

102b: Inductive parasitic resistance

103a: NMOS transistor

103b: PMOS transistor

104a: first voltage divider resistor

104b: second voltage divider resistor

105: output capacitance

106: ramp signal generating unit

106a: constant current source

106b: switch

106c: the first capacitor

106d: second capacitor

106e: transduction amplifier

106f: first resistance

106g: second resistance

106g1: control module

106g2: switch

106g3: compensation resistor

106g4: switch

106g5: current source for measurement

107: transduction amplifier

108a: filter resistor

108b: filter capacitor

109: Comparator

110: Oscillator

111: flip-flop

112: PWM control drive unit

200: Electronic equipment

210: Boost power converter capable of quickly responding to input voltage changes

220: Information processing circuit

FIG. 1 shows a circuit diagram of a conventional boost power converter. 2 is a circuit diagram of an embodiment of a boost power converter capable of quickly responding to input voltage changes according to the present invention. FIG. 3 is a circuit diagram of another embodiment of a boost power converter capable of quickly responding to changes in input voltage according to the present invention. 4 is a block diagram of an embodiment of an electronic device of the invention.

100: Boost power converter

101: input capacitance

102a: inductance

102b: Inductive parasitic resistance

103a: NMOS transistor

103b: PMOS transistor

104a: first voltage divider resistor

104b: second voltage divider resistor

105: output capacitance

106: ramp signal generating unit

106a: constant current source

106b: switch

106c: the first capacitor

106d: second capacitor

106e: transduction amplifier

106f: first resistance

106g: second resistance

107: transduction amplifier

108a: filter resistor

108b: filter capacitor

109: Comparator

110: Oscillator

111: flip-flop

112: PWM control drive unit

Claims (13)

A boost power converter capable of quickly responding to changes in input voltage has: an inductance with an equivalent inductance and an inductance parasitic resistance connected in series with it; an NMOS transistor for controlling conduction according to a first switching signal An input voltage is used to charge the inductor during a charging period of a PWM period; a PMOS transistor is used to conduct conduction according to a second switching signal to make the inductor to an output terminal during the discharging period of the PWM period Discharge; a voltage divider circuit for generating a feedback voltage based on a ratio of an output voltage established on an output capacitor; a ramp signal generating unit for modulating a ramp signal according to a voltage across the inductor; An error averaging circuit to generate an error average voltage based on the average value of the difference between the feedback voltage and a reference voltage; a comparator to generate a charging start based on the comparison result of the ramp signal and the error average voltage Start signal; an oscillator is used to generate a clock signal; a flip-flop is used to generate a PWM signal, wherein the starting point of the charging period of the PWM signal is determined by the charging start signal, and The end point of the charging period is determined by the clock signal; a PWM control drive unit is used to generate the first switching signal according to the PWM signal to control the NMOS transistor and the second switching signal to Control the PMOS transistor. A boost power converter capable of quickly responding to input voltage changes as described in item 1 of the patent application scope, wherein the ramp signal generating unit has a certain current source, a switch, a first capacitor, a second capacitor, and a transduction An amplifier, a first resistor, and a second resistor; characterized in that the constant current source is coupled between the input voltage and an upper electrode of the first capacitor to provide a certain current, and the first resistor is coupled Between a lower electrode of the first capacitor and a reference ground, the channel of the switch is connected in parallel with the first capacitor, and the control terminal of the switch is coupled to a reset signal; the second capacitor and the second capacitor The resistance forms a series circuit, and the series circuit is connected in parallel with the inductance; The input port of the transconductance amplifier is coupled to the second capacitor, and its output terminal is coupled to the lower electrode of the first capacitor; during operation, the reset signal periodically A voltage across a capacitor is reset to zero to periodically generate the ramp signal. As mentioned in item 2 of the patent application scope, a boost power converter capable of quickly responding to input voltage changes, wherein the second capacitor and the second resistor are based on a formula: L/R _DCR = R _AUX . C _AUX determines its value, where L is the equivalent inductance of the inductor, R _{DCR is} the resistance value of the parasitic resistance of the inductor, R _{AUX is} the resistance value of the second resistor, and C _{AUX is} the capacitance value of the second capacitor. As described in item 1 of the patent application scope, a boost power converter capable of quickly responding to input voltage changes, wherein the ramp signal generating unit has a certain current source, a first switch, a first capacitor, a second capacitor, a A transconductance amplifier, a first resistor, a control module, a plurality of second switches, a plurality of compensation resistors, a third switch, and a measurement current source, characterized in that the constant current source is coupled to the A certain current is provided between the input voltage and an upper electrode of the first capacitor. The first resistor is coupled between a lower electrode of the first capacitor and a reference ground. The channel of the first switch is connected to the first A capacitor is connected in parallel, and the control terminal of the first switch is coupled to a reset signal; the second capacitor and one of the plurality of compensation resistors are configured to form a series circuit, and the series circuit is connected in parallel with the inductor , And the configuration is formed as follows: immediately after power-on, the control module outputs a plurality of switching signals to power up the measurement current source and short-circuit the plurality of compensation resistors, and parasitic resistance of the inductor The trans-voltage is converted into a current through the transconductance amplifier, and then the current will generate a trans-voltage in the first resistor; the control module calculates the resistance value of the inductance parasitic resistance according to the trans-voltage; and the control module according to The resistance value determines a number of the plurality of switching signals so that the plurality of compensation resistors form the configuration and disconnect the measurement current source; and the input port of the transconductance amplifier is coupled to the second capacitor The output terminal is coupled to the lower electrode of the first capacitor; during operation, the reset signal periodically resets the voltage across the first capacitor to zero to make the ramp signal periodic To produce. As mentioned in item 4 of the patent application scope, a boost power converter capable of quickly responding to changes in input voltage, wherein the second capacitor and the equivalent resistance of the configuration are based on a formula: L/R _DCR = R _AUX . C _AUX determines its value, where L is the equivalent inductance of the inductor, R _{DCR is} the resistance value of the parasitic resistance of the inductor, R _AUX is the resistance value of the equivalent resistance, and C _{AUX is} the capacitance value of the second capacitor. A boost power converter capable of quickly responding to changes in input voltage has an energy transfer unit for periodically charging an inductor with an input voltage and causing the inductor to an output terminal under the control of a PWM signal Discharge to generate an output voltage, the inductor has an equivalent inductance and an inductance parasitic resistance connected in series with it; a ramp signal generating unit for modulating a ramp signal according to the voltage across one of the inductors; an error averaging circuit, used Generating an error average voltage based on the average value of the difference between a feedback voltage of the output voltage and a reference voltage; and a PWM signal generating unit for determining the PWM based on the comparison result of the ramp signal and the error average voltage The starting point of the signal. An electronic device has a boost power converter and an information processing circuit, wherein the boost power converter is used to generate an output voltage according to an input voltage to supply power to the information processing circuit, and the boost power conversion The device has an inductance with an equivalent inductance and an inductance parasitic resistance connected in series with it; an NMOS transistor for controlling conduction according to a first switching signal to make the input voltage to the charging period of a PWM period The inductor is charged; a PMOS transistor is used to conduct according to the control of a second switching signal to discharge the inductor to an output during the discharge period of the PWM period; a voltage divider circuit is used to depend on an output capacitor A ratio of the output voltage established above generates a feedback voltage; a ramp signal generation unit for modulating a ramp signal according to a voltage across the inductor; and an error averaging circuit for the feedback voltage and An average value of the difference of a reference voltage generates an error average voltage; a comparator is used to generate a charging start signal according to the comparison result of the ramp signal and the error average voltage; An oscillator is used to generate a clock signal; a flip-flop is used to generate a PWM signal, wherein the starting point of the charging period of the PWM signal is determined by the charging start signal, and the charging The end point of the period is determined by the clock signal; a PWM control drive unit is used to generate the first switching signal according to the PWM signal to control the NMOS transistor and the second switching signal to control the PMOS Transistor. The electronic device as described in item 7 of the patent application scope, wherein the ramp signal generating unit has a certain current source, a switch, a first capacitor, a second capacitor, a transconductance amplifier, a first resistor and a second Resistor; characterized in that: the constant current source is coupled between the input voltage and one of the upper electrodes of the first capacitor to provide a certain current, and the first resistor is coupled to a lower electrode of the first capacitor and a Between reference grounds, the channel of the switch is connected in parallel with the first capacitor, and the control terminal of the switch is coupled to a reset signal; the second capacitor and the second resistor form a series circuit, and the series circuit Is connected in parallel with the inductor; the input port of the transconductance amplifier is coupled to the second capacitor, and the output terminal is coupled to the lower electrode of the first capacitor; during operation, the reset The signal periodically resets the voltage across the first capacitor to zero to periodically generate the ramp signal. The electronic device as described in item 8 of the patent application scope, wherein the second capacitor and the second resistor are based on a formula: L/R _DCR = R _AUX . C _AUX determines its value, where L is the equivalent inductance of the inductor, R _{DCR is} the resistance value of the parasitic resistance of the inductor, R _{AUX is} the resistance value of the second resistor, and C _{AUX is} the capacitance value of the second capacitor. The electronic device as described in item 7 of the patent application scope, wherein the ramp signal generating unit has a certain current source, a first switch, a first capacitor, a second capacitor, a transconductance amplifier, a first resistor, a The control module, the plurality of second switches, the plurality of compensation resistors, a third switch, and a measurement current source are characterized in that: the constant current source is coupled to one of the input voltage and the first capacitor To provide a certain current between the electrodes, the first resistor is coupled between a lower electrode of the first capacitor and a reference ground, the channel of the first switch is connected in parallel with the first capacitor, and the first switch The control terminal is coupled to a reset signal; the second capacitor and one of the plurality of compensation resistors form a series circuit, the series circuit is connected in parallel with the inductor, and the configuration is formed as follows: At the time of power-on, the control module outputs a plurality of switching signals to power on the measurement current source and short-circuit the plurality of compensation resistors, and the trans-voltage of the inductive parasitic resistance is converted into Current, and then the current will generate a trans-voltage across the first resistor; the control module calculates the resistance value of the inductance parasitic resistance according to the trans-voltage; and the control module determines the plurality of the resistance values according to the resistance value R _DCR One digit of the switch signal to make the plurality of compensation resistors form the configuration and disconnect the measurement current source; and the input port of the transconductance amplifier is coupled to the second capacitor, and the output end thereof is It is coupled to the lower electrode of the first capacitor; during operation, the reset signal periodically resets the voltage across the first capacitor to zero to periodically generate the ramp signal. The electronic equipment as described in item 10 of the patent application scope, wherein the second capacitor and the equivalent resistance of the configuration are based on a formula: L/R _DCR = R _AUX . C _AUX determines its value, where L is the equivalent inductance of the inductor, R _{DCR is} the resistance value of the parasitic resistance of the inductor, R _AUX is the resistance value of the equivalent resistance, and C _{AUX is} the capacitance value of the second capacitor. The electronic device as described in any one of the items 7 to 11 of the patent application range is a display, a smartphone or a portable computer. An electronic device, which is a display, a smart phone or a portable computer, and has a boost power converter and an information processing circuit, wherein the boost power converter is used to depend on an input voltage An output voltage is generated to power the information processing circuit, and the boost power converter has: an energy transfer unit for periodically charging an inductor with an input voltage and enabling the inductor under the control of a PWM signal Discharging an output terminal to generate an output voltage, the inductor has an equivalent inductance and an inductance parasitic resistance in series with it; A ramp signal generating unit for modulating a ramp signal according to a voltage across the inductor; an error averaging circuit for generating an error average based on the average value of the difference between a feedback voltage and a reference voltage of the output voltage Voltage; and a PWM signal generating unit for determining the starting point of the PWM signal according to the comparison result of the ramp signal and the error average voltage.

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