TWI694684B - Wireless communication circuit with scheduling circuit in mac layer - Google Patents

Abstract

A wireless communication circuit includes: a physical-layer circuit, arranged to operably communicate with other wireless communication devices through an antenna; a micro-controller, arranged to operably generate data frames to be transmitted to other wireless communication devices; and a MAC-layer circuit comprising: a MAC-layer storage circuit for storing a data queue; a MAC-layer control circuit, coupled with the physical-layer circuit, the micro-controller, and the MAC-layer storage circuit, arranged to temporarily store the data frames generated by the micro-controller in the data queue; and a scheduling circuit, coupled with the MAC-layer storage circuit and the MAC-layer control circuit, arranged to operably schedule a timing that the MAC-layer control circuit transmits data stored in the data queue to the physical-layer circuit.

Description

Wireless communication circuit with scheduling circuit in circuit of media access control layer

The invention relates to a wireless communication circuit, in particular to a wireless communication circuit which can increase the data transmission amount.

Many wireless communication circuits use a carrier sense multiple access (CSMA) mechanism as a media access control protocol to achieve time-division multiple access (TDMA) transmission purposes. In the traditional wireless communication circuit, the microprocessor needs to frequently read the temporary memory in the circuit of the media access control layer to know the progress of data transmission in the circuit of the media access control layer.

However, the aforementioned microprocessor frequently reads the register in the circuit of the media access control layer, which will increase the amount of information communication between the microprocessor and the circuit of the media access control layer, thus reducing the wireless communication circuit. Overall transmission performance.

In view of this, how to improve the transmission performance of wireless communication circuits is really a problem to be solved.

The present invention provides an embodiment of a wireless communication circuit, including: a physical layer circuit configured to communicate with other wireless communication devices through an antenna; a microprocessor configured to generate data frames to be transmitted to other wireless communication devices; and media An access control layer circuit, the media access control layer circuit includes: a media access control layer storage circuit for storing data queues; a media access control layer control circuit, coupled to the physical layer circuit and the microprocessor , And the storage circuit of the media access control layer, configured to temporarily store the data frame generated by the microprocessor in the data queue; and a scheduling circuit, coupled to the media The access control layer storage circuit and the media access control layer control circuit are configured to control the scheduling of the media access control layer control circuit to transmit the data stored in the data queue to the physical layer circuit.

The present invention also provides an embodiment of a wireless communication circuit, which includes: a physical layer circuit configured to communicate with other wireless communication devices through an antenna; a microprocessor configured to generate data frames and related data to be transmitted to other wireless communication devices Action frame; and a media access control layer circuit, the media access control layer circuit includes: a media access control layer storage circuit for storing data queues and management queues; a media access control layer control circuit, coupled The physical layer circuit, the microprocessor, and the media access control layer storage circuit are configured to temporarily store the data frame and the related action frame generated by the microprocessor in the data queue and the management queue, respectively Row; scheduling circuit, coupled to the media access control layer storage circuit and the media access control layer control circuit, configured to intermittently check the contents of the data queue and the management queue to control the media storage The fetch control layer control circuit sends the data queue and the data stored in the management queue to the schedule of the physical layer circuit; and the media access control layer register is coupled to the media access control layer control circuit And the microprocessor are arranged to store the operating state value of the media access control layer circuit, which can be used by the microprocessor to judge the operating state of the media access control layer circuit; wherein, the media access control layer controls The timing of the circuit transmitting the data queue and the data stored in the management queue to the physical layer circuit is controlled by the scheduling circuit, not by the microprocessor, if the scheduling circuit determines that the data queue If there is no data to be transmitted in the row, the scheduling circuit will control the media access control layer control circuit to release the network occupation right of the wireless communication circuit to other wireless communication devices in advance.

One of the advantages of the above embodiments is that the scheduling of the media access control layer circuit to transmit data to the physical layer circuit is controlled by the scheduling circuit in the media access control layer circuit, not the media access control It is controlled by the microprocessor outside the layer circuit, so it can greatly reduce the communication burden between the microprocessor and the media access control layer circuit, thereby improving the overall transmission performance of the wireless communication circuit.

Another advantage of the above embodiment is that the scheduling circuit in the media access control layer circuit is used to control the data transmission timing of the media access control layer control circuit, which can improve the timing accuracy of the wireless communication circuit transmitting data to other wireless communication devices. .

Other advantages of the present invention will be explained in more detail with the following description and drawings.

100: wireless communication circuit (wireless communication circuit)

102~106: wireless communication device (wireless communication device)

108: antenna

110: physical-layer circuit

120: Microprocessor (micro-controller)

130: storage circuit

140: data bus

150: MAC-layer circuit

151: MAC-layer storage circuit

152: data queue (data queue)

153: management queue (management queue)

154: MAC-layer control circuit

155: Scheduling circuit

156: MAC-layer register

FIG. 1 is a simplified functional block diagram of a wireless communication circuit according to an embodiment of the present invention.

The embodiments of the present invention will be described below in conjunction with related drawings. In these drawings, the same reference numerals indicate the same or similar elements or method flows.

FIG. 1 is a simplified functional block diagram of a wireless communication circuit 100 according to an embodiment of the present invention. The wireless communication circuit 100 may perform data communication with a plurality of wireless communication devices (for example, the exemplary wireless communication devices 102 to 106 in FIG. 1) through the antenna 108 by wireless transmission.

The wireless communication circuit 100 uses a carrier detection multiple access (CSMA) mechanism as a media access control protocol to achieve time division multiple access (TDMA) transmission purposes. The wireless communication circuit 100 and other wireless communication devices 102-106 within the wireless signal transmission range can form a wireless local area network (WLAN), and each acts as a network node in the wireless local area network.

During operation, the wireless communication circuit 100 and the wireless communication devices 102-106 may adopt an appropriate token passing mechanism to determine network nodes with network occupation rights. Generally speaking, only the network nodes possessing tokens have the right to use network media for data transmission. The use of a token transfer mechanism can maximize the bandwidth usage of the wireless local area network to take full advantage of the network bandwidth.

As shown in FIG. 1, the wireless communication circuit 100 includes a physical layer circuit 110, a microprocessor 120, a storage circuit 130, a data bus 140, and a medium access control layer circuit 150.

The microprocessor 120 is configured to generate data frames and related action frames to be transmitted to other wireless communication devices 102-106. The foregoing action frame may include token request information and token request related to the token delivery mechanism. Token release information.

The storage circuit 130 is coupled to the microprocessor 120 through a data bus 140, and is configured to store software programs and related data required for the operation of the microprocessor 120.

The media access control layer circuit 150 is coupled to the microprocessor 120 through the data bus 140, and is configured to process the data frames and related action frames generated by the microprocessor 120, and connect the data frames and the related action frames at an appropriate time. The action frame is transmitted to the physical layer circuit 110 in a suitable packet form for processing.

The physical layer circuit 110 is coupled to the media access control layer circuit 150, and is configured to convert the packets from the media access control layer circuit 150 into an appropriate analog signal and transmit it to other wireless communication devices 102-106 through the antenna 108. .

In practice, the aforementioned wireless communication devices 102-106 can be implemented with various suitable devices having wireless network communication capabilities, such as smart phones, computers, tablet computers, notebook computers, and so on. In addition, the physical layer circuit 110, the microprocessor 120, the storage circuit 130, and the data bus 140 in the wireless communication circuit 100 can be implemented with various existing suitable circuits.

As shown in FIG. 1, the media access control layer circuit 150 in this embodiment includes a media access control layer storage circuit 151, a media access control layer control circuit 154, a scheduling circuit 155, and a media access control layer temporary storage器156.

The storage circuit 151 of the media access control layer is divided into at least two blocks for storing the data queue 152 and the management queue 153 respectively, wherein the data queue 152 further includes quality of service corresponding to different quality of service , QoS) multiple data sub-queues.

The media access control layer control circuit 154 is coupled to the physical layer circuit 110, the microprocessor 120, and the media access control layer storage circuit 151, and is configured to temporarily store the data frame generated by the microprocessor 120 in the data queue 152. The operation frame generated by the microprocessor 120 is temporarily stored in the management queue 153.

The scheduling circuit 155 is coupled to the media access control layer storage circuit 151 and the media access control layer The control circuit 154 is configured to control the scheduling of the media access control layer control circuit 154 to transmit the data stored in the data queue 152 and the management queue 153 to the physical layer circuit 110.

The media access control layer register 156 is coupled to the media access control layer control circuit 154 and the microprocessor 120, and is configured to store the operating state value of the media access control layer circuit 150. During the operation of the media access control layer control circuit 154, the operating state of the media access control layer circuit 150 (such as the progress of data transmission) can be written into the media access control layer register 156 in an appropriate data format , So that the microprocessor 120 can learn the relevant operating status of the media access control layer circuit 150 by reading the content of the media access control layer register 156.

In practice, the media access control layer storage circuit 151, the media access control layer control circuit 154, and the media access control layer register 156 in the media access control layer circuit 150 can all use various existing suitable circuits. to fulfill. The scheduling circuit 155 can be implemented by a digital circuit with data reading capability and judgment capability.

In addition, the different functional blocks in the aforementioned wireless communication circuit 100 can be implemented by different circuits, or can be integrated into a single circuit chip.

Please note that in the wireless communication circuit 100, the timing at which the media access control layer circuit 150 transmits related data frames and/or action frames to the physical layer circuit 110 for processing is not controlled by the microprocessor 120, but rather It is controlled by the scheduling circuit 155 in the media access control layer circuit 150.

In an embodiment, because the timing of the media access control layer circuit 150 transmitting related data frames and/or action frames to the physical layer circuit 110 for processing is not controlled by the microprocessor 120, the microprocessing can be performed The software program required by the device 120 to perform the above control is removed. That is, in this embodiment, the software program stored in the storage circuit 130 does not include the relevant software program that controls the timing at which the microprocessor 120 controls the transmission of related data frames and/or action frames to the physical layer circuit 110 for processing.

During operation, the scheduling circuit 155 intermittently checks the contents of the data queue 152 and the management queue 153 to determine whether there is data that needs to be transmitted to other wireless communication devices, According to the result of the judgment, the timing of the media access control layer control circuit 154 transmitting the data stored in the data queue 152 and the management queue 153 to the physical layer circuit 110 is controlled. For example, the scheduling circuit 155 may periodically check the amount of remaining data in the data queue 152 and the management queue 153 to be transmitted to individual wireless communication devices.

If the scheduling circuit 155 determines that there is data in the data queue 152 and/or management queue 153 that needs to be transmitted to a specific wireless communication device, the scheduling circuit 155 will control the media storage when the wireless communication circuit 100 has the network occupation right The control layer control circuit 154 transmits the data in the data queue 152 and/or the management queue 153 to the physical layer circuit 110 for processing, and transmits the corresponding wireless communication device through the antenna 108, for example, the aforementioned wireless communication device 102~ One or more of 106 devices.

On the other hand, if the scheduling circuit 155 determines that there is no data in the data queue 152 and the management queue 153 that needs to be transmitted to other wireless communication devices, the scheduling circuit 155 controls the media access control layer control circuit 154 to convert the wireless communication circuit The 100 network occupancy rights are released in advance for use by other wireless communication devices.

In this way, when the wireless communication circuit 100 does not need to send data to other wireless communication devices 102-106, the time that the wireless communication circuit 100 occupies the network medium can be shortened, so that the other wireless communication devices 102-106 can be obtained early The right to use network media.

As can be seen from the foregoing description, the schedule and timing at which the media access control layer control circuit 154 transmits the data stored in the data queue 152 and the management queue 153 to the physical layer circuit 110 is controlled by the schedule circuit 155, not by The microprocessor 120 controls.

Therefore, the microprocessor 120 does not need to read the media access control layer register 156 frequently, so the communication load between the microprocessor 120 and the media access control layer circuit 150 can be greatly reduced, thereby improving the wireless communication circuit 100 The overall transmission performance.

In addition, since the scheduling circuit 155 in the media access control layer circuit 150 can directly read and check the data in the data queue 152 and the management queue 153, the media access control layer control circuit 154 can be accurately and instantly informed Progress of data transmission. Therefore, use the schedule The circuit 155 controls the data transmission timing of the media access control layer control circuit 154, which can improve the timing accuracy of the wireless communication circuit 100 transmitting data to other wireless communication devices, and avoid the situation where the transmitting end and the receiving end of the data are out of synchronization.

Please note that the aforementioned circuit architecture is only an embodiment of the present invention and does not limit the actual implementation of the present invention. For example, in some embodiments, the aforementioned data bus 140 may be replaced with other suitable data and command transmission mechanisms.

For another example, in another embodiment, the scheduling circuit 155 can be coupled to the media access control layer register 156, and the media storage can be learned by reading the content of the media access control layer register 156. Take the data transmission progress of the control layer control circuit 154. In this case, the scheduling circuit 155 does not need to check the contents of the data queue 152 and the management queue 153, so it does not need to be coupled to the storage circuit 151 of the media access control layer.

Certain words are used in the specification and patent application scope to refer to specific elements, and those skilled in the art may use different terms to refer to the same element. This specification and the scope of patent application do not use the difference in names as a means of distinguishing elements, but the difference in function of elements as a basis for distinguishing. "Inclusion" mentioned in the description and the scope of patent application is an open term and should be interpreted as "including but not limited to." In addition, the term "coupled" here includes any direct and indirect connection means. Therefore, if it is described that the first element is coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection, wireless transmission, optical transmission, or other signal connection, or through other elements or connections The means is indirectly electrically or signally connected to the second element.

The description method of "and/or" used in the specification includes any one of the listed items or any combination of multiple items. In addition, unless otherwise specified in the specification, any singular expressions also include the plural meaning.

The above are only preferred embodiments of the present invention, and any equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

100: wireless communication circuit

102~106: wireless communication device

108: antenna

110: Physical layer circuit

120: Microprocessor

130: storage circuit

140: data bus

150: Media access control layer circuit

151: Media access control layer storage circuit

152: Data Queue

153: Management Queue

154: Media access control layer control circuit

155: Schedule circuit

156: Media access control layer register

Claims (7)

A wireless communication circuit (100), including: a physical layer circuit (110) configured to communicate with other wireless communication devices through an antenna (108); a microprocessor (120) configured to generate signals to be transmitted to other wireless communication devices Data frame; and media access control layer circuit (150), the media access control layer circuit (150) includes: media access control layer storage circuit (151) for storing data queue (152); media access The control layer control circuit (154), coupled to the physical layer circuit (110), the microprocessor (120), and the media access control layer storage circuit (151), is configured to configure the microprocessor (120) The generated data frame is temporarily stored in the data queue (152); and the scheduling circuit (155) is coupled to the media access control layer storage circuit (151) and the media access control layer control circuit (154) ), set to control the scheduling of the media access control layer control circuit (154) to transmit the data stored in the data queue (152) to the physical layer circuit (110), and set to intermittently check the data queue The content of the row (152) to adjust the timing of the media access control layer control circuit (154) transmitting the data stored in the data queue (152) to the physical layer circuit (110); wherein, the media access The control layer control circuit (154) sends the data stored in the data queue (152) to the physical layer circuit (110) for scheduling and timing, not controlled by the microprocessor (120), but by the The scheduling circuit (155) controls to reduce the communication burden between the microprocessor (120) and the media access control layer circuit (150). The wireless communication circuit (100) according to claim 1, wherein if the scheduling circuit (155) determines that there is no data to be transmitted in the data queue (152), the scheduling The circuit (155) controls the media access control layer control circuit (154) to release the network occupation right (occupation) of the wireless communication circuit (100) to other wireless communication devices in advance. The wireless communication circuit (100) according to claim 2, wherein the microprocessor (120) is further configured to generate an action frame corresponding to the data frame, and the media access control layer control circuit (154) is further provided The action frame is temporarily stored in the management queue (153) of the media access control layer storage circuit (151); wherein, the scheduling circuit (155) is also configured to intermittently check the management queue (153) Content to adjust the timing of the media access control layer control circuit (154) transmitting the data stored in the management queue (153) to the physical layer circuit (110). The wireless communication circuit (100) according to claim 1, further comprising: a storage circuit (130), coupled to the microprocessor (120), configured to store software programs required for the operation of the microprocessor (120) And related data, wherein the software program stored in the storage circuit (130) does not include the related software program that controls the timing of sending data frames and action frames to the physical layer circuit (110) for processing. The wireless communication circuit (100) according to claim 1, wherein the media access control layer circuit (150) further includes: a media access control layer register (156) coupled to the media access control layer The control circuit (154) and the microprocessor (120) are configured to store the operating state value of the media access control layer circuit (150), which can be used by the microprocessor (120) to determine the media access control layer The operating state of the circuit (150). The wireless communication circuit (100) according to claim 1, wherein the microprocessor (120) is further configured to generate an action frame corresponding to the data frame, and the media access control layer control circuit (154) is further provided The action frame is temporarily stored in the management queue (153) of the media access control layer storage circuit (151); wherein, the scheduling circuit (155) is also configured to intermittently check the management queue (153) Content to adjust the media access control layer control circuit (154) to manage The timing of the data stored in the queue (153) is sent to the physical layer circuit (110). A wireless communication circuit (100) includes: a physical layer circuit (110) configured to communicate with other wireless communication devices through an antenna (108); a microprocessor (120) configured to generate signals to be transmitted to other wireless communication devices Data frames and related action frames; and a media access control layer circuit (150), the media access control layer circuit (150) includes: a media access control layer storage circuit (151) for storing data queues (152) ) And management queue (153); media access control layer control circuit (154), coupled to the physical layer circuit (110), the microprocessor (120), and the media access control layer storage circuit (151) ), configured to temporarily store the data frame and related action frame generated by the microprocessor (120) in the data queue (152) and the management queue (153), respectively; the scheduling circuit (155), The media access control layer storage circuit (151) and the media access control layer control circuit (154) are coupled to intermittently check the contents of the data queue (152) and the management queue (153), To control the scheduling and timing of the media access control layer control circuit (154) to transmit the data stored in the data queue (152) and the management queue (153) to the physical layer circuit (110); and the media The access control layer register (156), coupled to the media access control layer control circuit (154) and the microprocessor (120), is configured to store the operating state of the media access control layer circuit (150) Value for the microprocessor (120) to determine the operating state of the media access control layer circuit (150); where the media access control layer control circuit (154) queues the data (152) and The timing at which the data stored in the management queue (153) is sent to the physical layer circuit (110) is controlled by the scheduling circuit (155), not by the microprocessor (120), to reduce the micro Processor (120) and the media access control layer The communication burden between the circuits (150); wherein, if the scheduling circuit (155) determines that there is no data to be transmitted in the data queue (152), the scheduling circuit (155) will control the media access control The layer control circuit (154) releases the network occupation right of the wireless communication circuit (100) to other wireless communication devices in advance.

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