TWI680511B - Semiconductor structure and manufacturing method thereof - Google Patents

Abstract

The present disclosure relates to a multi-ring bonding pad, a semiconductor structure having the multi-ring bonding pad, and a manufacturing method thereof. The bonding pad includes an inner ring member, an outer ring member, and a plurality of bridge members. The inner ring member has a pair of first inner edges facing each other, a pair of second inner edges facing each other, and a plurality of third inner edges connecting the first inner edge to the second inner edge. The outer ring member surrounds the inner ring member and has a pair of first outer edges facing each other, a pair of second outer edges facing each other, and a plurality of third outer edges connecting the first outer edge to the second outer edge edge. The plurality of bridge members are disposed between the inner ring member and the outer ring member to connect the inner ring member to the outer ring member.

Description

Semiconductor structure and manufacturing method thereof

This application claims the priority and benefits of U.S. Provisional Application No. 62 / 770,952 for 2018/11/23 and U.S. Formal Application No. 16 / 268,954 for 2019/02/06. The contents of the official US application are incorporated herein by reference in their entirety.

The present disclosure relates to a bonding pad, a semiconductor structure having a bonding pad, and a manufacturing method thereof, and more particularly to a multi-ring bonding pad, a semiconductor structure having a multi-ring bonding pad, and a manufacturing method thereof.

The manufacturing process of a semiconductor integrated circuit includes a front-end-of-line (FEOL), a middle-end-of-line (MEOL), and a back-end-of-line (BEOL) process. The front-end process includes wafer preparation, isolation, well formation, gate patterning, spacers, extension and source (and) drain implantation, silicide formation, and dual stress pad formation. The middle process includes gate contact formation. The back-end process includes a series of wafer processing steps to interconnect semiconductor components produced during the front-end process and the middle-end process. In addition, successful manufacturing of qualified semiconductor wafer products requires consideration of the interaction between materials and processes.

The above description of the "prior art" is only for providing background technology. It does not recognize that the above description of the "prior technology" reveals the subject matter of this disclosure, does not constitute the prior technology of this disclosure, and any description of the "prior technology" above. Neither shall be part of this case.

The present disclosure provides a bonding pad including an inner ring member, an outer ring member, and a plurality of bridge members. The inner ring member has a pair of first inner edges facing each other, a pair of second inner edges facing each other, and a plurality of numbers provided at corners defined by extension lines of the first inner edge and the second inner edge Third inner edge. The first inner edge is connected to the second inner edge through the third inner edge. The outer ring member surrounds the inner ring member and is spaced apart from the inner ring member. The outer ring member has a pair of first outer edges facing each other, a pair of second outer edges facing each other, and a plurality of numbers provided at corners defined by extension lines of the first outer edge and the second outer edge Third outer edge. The first outer edge is connected to the second outer edge through the third outer edge. The plurality of bridge members are disposed between the inner ring member and the outer ring member to connect the inner ring member to the outer ring member.

In some embodiments, an included angle between the third inner edge and the first inner edge is approximately 135 degrees, and an included angle between the third inner edge and the second inner edge is approximately 135 degrees.

In some embodiments, the first outer edge is substantially parallel to the first inner edge, and the second outer edge is substantially parallel to the second inner edge.

In some embodiments, a first distance between two adjacent bridge members connected to the first inner edge is substantially smaller than a second distance between two adjacent bridge members connected to the second inner edge distance.

In some embodiments, the inner ring member further includes a plurality of inner notches provided on the first inner edge and the second inner edge, and a plurality of inner notches provided on the first outer edge and the second outer edge. Outer notches.

In some embodiments, the inner recess is equidistant from the third inner edge, and the outer recess is equidistant from the third outer edge.

In some embodiments, the inner notch is disposed between the third inner edge and the bridge member closest to the third inner edge, and the outer notch is disposed between the third outer edge and the bridge member. The position closest to the third outer edge.

In some embodiments, the inner notch and the outer notch are respectively disposed on the first inner edge and the first outer edge, or are disposed on the second inner edge and the second outer edge, respectively, away from each other. Ground setting.

In some embodiments, the inner ring member and the outer ring member have a uniform width.

In some embodiments, the width of the inner ring member is equal to twice the width of the bridge member.

The disclosure further provides a semiconductor structure including a multilayer component, a dielectric layer, and a bonding pad. The dielectric layer is disposed above the multilayer component. The bonding pad is disposed in the dielectric layer and includes an inner ring member, an outer ring member, and a plurality of bridge members. The inner ring member has a pair of first inner edges facing each other, a pair of second inner edges facing each other, and a plurality of numbers provided at corners defined by extension lines of the first inner edge and the second inner edge Third inner edge. The first inner edge is connected to the second inner edge through the third inner edge. The outer ring member surrounds the inner ring member and is spaced apart from the inner ring member. The outer ring member has a pair of first outer edges facing each other, a pair of second outer edges facing each other, and a plurality of numbers provided at corners defined by extension lines of the first outer edge and the second outer edge Third outer edge. The first outer edge is connected to the second outer edge through the third outer edge. The plurality of bridge members are disposed between the inner ring member and the outer ring member to connect the inner ring member to the outer ring member.

In some embodiments, the multilayer component includes a main component, an insulating layer, and at least one through hole, wherein the insulating layer is disposed above the main component, the through hole is disposed within the insulating layer, and the main component passes through the A via is electrically connected to the bonding pad.

The disclosure further provides a method for manufacturing a semiconductor structure, including the steps of: providing a multilayer component; depositing a dielectric layer over the multilayer device; forming a recessed pattern in the dielectric layer; and depositing a recessed pattern in the recessed pattern. Metal layer.

In some embodiments, the metal layer extends along an upper surface of the dielectric layer and enters the recessed pattern.

In some embodiments, the manufacturing method further includes: performing a planarization process to remove a portion of the metal layer above the upper surface.

In some embodiments, the manufacturing method further includes: performing a grinding process to obtain a flat upper surface of the dielectric layer.

In some embodiments, the manufacturing method further includes: before depositing the metal layer, depositing a barrier layer over the dielectric layer and entering the recessed pattern; and depositing a crystalline layer over the barrier layer.

In some embodiments, the barrier layer and the seed layer are substantially conformal layers.

In some embodiments, the formation of the recessed pattern includes the steps of: coating a photoresist layer over the dielectric layer; patterning the photoresist layer to form at least one opening in the photoresist layer, wherein the dielectric A portion of the layer is exposed through the opening; and an etching process is performed to remove a portion of the dielectric layer exposed through the opening to form the recessed pattern.

In some embodiments, the metal layer is in contact with the multilayer component.

The technical features and advantages of this disclosure have been outlined quite extensively above, so that the detailed description of this disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the patent application of this disclosure will be described below. Those with ordinary knowledge in the technical field to which this disclosure belongs should understand that the concepts and specific embodiments disclosed below can be used quite easily to modify or design other structures or processes to achieve the same purpose as this disclosure. Those with ordinary knowledge in the technical field to which this disclosure belongs should also understand that such equivalent constructions cannot be separated from the spirit and scope of this disclosure as defined by the scope of the attached patent application.

The following description of this disclosure is accompanied by drawings that form a part of the description to illustrate the embodiment of the disclosure, but the disclosure is not limited to this embodiment. In addition, the following embodiments can be appropriately integrated with the following embodiments to complete another embodiment.

"One embodiment", "embodiment", "exemplified embodiment", "other embodiment", "another embodiment", etc. refer to the embodiment described in this disclosure may include specific features, structures, or characteristics, however Not every embodiment must include the particular feature, structure, or characteristic. Furthermore, the repeated use of the phrase "in the embodiment" does not necessarily refer to the same embodiment, but may be the same embodiment.

In order that this disclosure may be fully understood, the following description provides detailed steps and structures. Obviously, the implementation of this disclosure does not limit the specific details known to those skilled in the art. In addition, the known structures and steps are not described in detail, so as not to unnecessarily limit the present disclosure. The preferred embodiments of the present disclosure are detailed below. However, in addition to the embodiments, the disclosure can be widely implemented in other embodiments. The scope of this disclosure is not limited to the content of the embodiments, but is defined by the scope of patent application.

FIG. 1 is a top view illustrating a bonding pad 10 according to some embodiments of the present disclosure. 1, the bonding pad 10 includes an inner ring member 20, an outer ring member 30 surrounding the inner ring member 20 and spaced apart from the inner ring member 20, and a plurality of bridges provided between the inner ring member 20 and the outer ring member 30. Component 40. The bridge member 40 connects the inner ring member 20 to the outer ring member 30. In some embodiments, the bonding pad 10 is used as the first metal layer (ie, M1 layer) or the second metal layer (ie, M2 layer) of a semiconductor device, and the semiconductor device may be, for example, a dynamic random access memory. Memory (dynamic random access memory, DRAM). In some embodiments, the contour of the bonding pad 10 is designed to reduce stress caused during a planarization process, such as a chemical mechanical polishing (CMP) process.

In some embodiments, the inner ring member 20 has a pair of first inner edges 210 opposite to each other, a pair of second inner edges 220 opposite to each other, and a plurality of pluralities connecting the first inner edge 210 to the second inner edge 220. Third inner edge 230. In some embodiments, the first inner edge 210 is not directly connected to the second inner edge 220. In some embodiments, the first inner edge 210 has a first length L1 and the second inner edge 220 has a second length L2 that is greater than the first length L1.

FIG. 2 is an enlarged view of a region A in FIG. 1. Referring to FIGS. 1 and 2, in some embodiments, the third inner edge 230 is disposed at a plurality of corners defined by extension lines 212, 222 of the first inner edge 210 and the second inner edge 220. In some embodiments, the extension line 212 of the first inner edge 210 is perpendicular to the extension line 222 of the second inner edge 220. In some embodiments, the angle α between the first inner edge 210 and the third inner edge 230 is about 135 degrees, and the angle β between the second inner edge 220 and the third inner edge 230 is about 135 degrees. This configuration is used to relieve stress during the planarization process, as described below.

In some embodiments, the outer ring member 310 has a pair of first outer edges 310 opposite to each other, a pair of second outer edges 320 opposite to each other, and a plurality of first connecting edges connecting the first outer edge 310 to the second outer edge 320. Three outer edges 330. In some embodiments, the first outer edge 310 is not directly connected to the second outer edge 320. In some embodiments, the first outer edge 310 is substantially parallel to the first inner edge 210, the second outer edge 320 is substantially parallel to the second inner edge 220, and the third outer edge 330 is substantially parallel to the third inner edge 230.

In some embodiments, the third outer edge 330 is disposed at a plurality of corners defined by the extension lines 312, 322 of the first outer edge 310 and the second outer edge 320. In some embodiments, the extension line 312 of the first outer edge 310 is perpendicular to the extension line 322 of the second outer edge 320. In some embodiments, to reduce stress, the angle φ between the first outer edge 310 and the third outer edge 330 is about 135 degrees, and the angle δ between the second outer edge 320 and the third outer edge is about 135 degrees. .

In some embodiments, the bridge member 40 is disposed between the inner ring member 20 and the outer ring member 30 to connect the inner ring member 20 to the outer ring member 30. In some embodiments, the bridge member 40 is disposed between the first inner edge 210 and the first outer edge 310 and between the second inner edge 220 and the second outer edge 320. In some embodiments, the bridge member 40 is not disposed between the third inner edge 230 and the third outer edge 330. In some embodiments, because the bridge member 40 has a uniform size and the first length L1 of the first inner edge 210 is smaller than the second length L2 of the second inner edge 220, two phases connected to the first inner edge 210 A first distance D1 between adjacent bridge members 40 is substantially smaller than a second distance D2 between two adjacent bridge members 40 connected to the second inner edge 220. In some embodiments, the space between two adjacent bridge members 40 is used for heat dissipation and stress distribution, and is designed to prevent excessive polishing during the planarization process.

In some embodiments, the inner ring member 20 further includes a plurality of inner notches 50 respectively disposed on the first inner edge 210 and the second inner edge 220. In some embodiments, the inner notch 50 is equidistant from the third inner edge 230. In some embodiments, the inner notch 50 is disposed between the third inner edge 230 and the bridge member 40 closest to the third inner edge 230.

In some embodiments, the outer ring member 30 further includes a plurality of outer notches 52 respectively disposed on the first outer edge 310 and the second outer edge 320. In some embodiments, the outer notch 52 is equidistant from the third outer edge 330. In some embodiments, the outer notch 52 is disposed between the third outer edge 330 and the bridge member 40 closest to the third outer edge 330. In some embodiments, the inner notch 50 and the outer notch 52 are disposed on the first inner edge 210 and the first outer edge 310, respectively, or on the second inner edge 220 and the second outer edge 320, respectively, away from each other. The ground is provided to prevent a loop current caused by a change in electromagnetic flux when power is supplied to the semiconductor element having the bonding pad 10. In some embodiments, such a discontinuous profile of the bonding pad 10 can reduce the propagation of noise therethrough.

Referring again to FIGS. 1 and 2, in some embodiments, the bonding pad 10 has a width W, which can be, for example, in a range between 2.70 and 6.0 micrometers (μm), such as about 2.75 micrometers. In some embodiments, the inner ring member 20 has a first width W1, the outer ring member 30 has a second width W2 substantially equal to the first width W1, and the bridge member 40 has a third width substantially smaller than the first width W1 W3. In some embodiments, the third width W3 may be equal to half of the first width W1. For example, the first width W1 and the second width W2 are about 1.1 microns, and the third width W3 is about 0.55 microns. In some embodiments, the inner ring member 20, the outer ring member 30, and the bridge member 40 are integrally formed. In some embodiments, the bonding pad 10 is made of a metallic material, such as copper or aluminum.

FIG. 3 is a flowchart illustrating a method 600 of fabricating a semiconductor structure 70 / 70A according to some embodiments of the present disclosure. 4 to 12 are cross-sectional views illustrating stages of forming the semiconductor structures 70 / 70A of some embodiments of the present disclosure. The flowchart of FIG. 3 also schematically shows the stages in FIGS. 4 to 12. In the subsequent discussion, the manufacturing stages shown in FIGS. 4 to 12 refer to the process steps in FIG. 3.

Referring to FIG. 4, according to step 602 in FIG. 3, a multilayer component 700 is provided. In some embodiments, the multilayer component 700 may include a main assembly 710 that includes one or more features, such as transistors, resistors, capacitors, diodes, dielectrics, vias, and the like. In some embodiments, the multilayer component 700 may further include an insulating layer 720 covering the main component 710, and at least one through hole 730 provided in the insulating layer 720. In some embodiments, the end surface 732 of the through hole 730 is coplanar with the upper surface 722 of the insulating layer 720. In some embodiments, the multilayer component 700 may be formed using conventional process steps.

Referring to FIG. 5, in some embodiments, a dielectric layer 740 is deposited over the insulating layer 720 and the via 730 according to step 604 in FIG. 3. In some embodiments, the dielectric layer 740 completely covers the insulating layer 720 and the via 730. In some embodiments, the dielectric layer 740 includes an oxide. In some embodiments, the dielectric layer 740 may be formed by chemical vapor deposition (CVD), spin coating, or other suitable methods. In some embodiments, after the dielectric layer 740 is deposited, a polishing process may be performed according to step 606 in FIG. 3 to obtain a flat upper surface 742 of the second dielectric layer 740.

Referring to FIG. 6, in some embodiments, a photoresist layer 750 is coated on the second dielectric layer 740 according to step 608 in FIG. 3. In some embodiments, according to step 610 in FIG. 3, the photoresist layer 750 is patterned to define an area where the dielectric layer 740 will be subsequently etched. In some embodiments, patterning the photoresist layer 750 through the following steps, including (1) exposing the photoresist layer 750 to a pattern (not shown), and (2) performing a post-exposure bake process (PEB) ) Process, and (3) developing the photoresist layer 750 to form a photoresist pattern 752 having at least one opening 754, as shown in FIG. 7. In some embodiments, a portion of the dielectric layer 740 to be subsequently etched is exposed through the opening 754. In some embodiments, the photoresist layer 740 may be patterned by, for example, electron-beam writing, ion-beam writing, or molecular imprint.

Referring to FIG. 8, in some embodiments, an etching process is performed to etch the dielectric layer 740 and a recess pattern 744 is defined in the dielectric layer 740 according to step 612 of FIG. 3. After the etching process, portions of the insulating layer 720 and the through holes 730 are exposed through the recessed pattern 744. In some embodiments, the etching process may be a single or multiple step etching process. In some embodiments, the etching process includes a wet etching process, a dry etching process, or a combination thereof. In some embodiments, the dry etching process may be an anisotropic etching process. In some embodiments, the depression pattern 744 may be formed to have a contour corresponding to the contour of the bonding pad 10 shown in FIG. 1.

Referring to FIG. 9, after the etching process, according to step 614 in FIG. 3, the photoresist pattern 752 is removed. In some embodiments, the photoresist pattern 752 may be removed using an ashing process or a wet strip process, wherein the wet strip process may chemically change the photoresist pattern 752 so that it is no longer adhered to the remaining second dielectric layer 740 on.

Referring to FIG. 10, in some embodiments, according to step 620 in FIG. 10, a metal layer 760 is deposited over the dielectric layer 740 and into the recessed pattern 744. In some embodiments, the metal layer 760 extends along the upper surface 742 of the dielectric layer 740 and enters the recessed pattern 744. In some embodiments, the metal layer 760 has a thickness sufficient to fill the recessed pattern 744. In some embodiments, the metal layer 760 is in contact with the via 730. In some embodiments, the metal layer 760 includes copper or aluminum. In some embodiments, the metal layer 760 is formed using an electroplating process.

Referring to FIGS. 11 and 12, in some embodiments, according to step 622 in FIG. 6, a planarization process is performed to expose the dielectric layer 740. Therefore, the semiconductor structure 70 is completely formed, and the bonding pad 10 shown in FIG. 3 is formed. In some embodiments, the semiconductor structure 70 includes a main component 710, an insulating layer 720 disposed above the main component 710, at least one through hole 730 disposed within the insulating layer 720, and a semiconductor layer 70 disposed above the insulating layer 720 and the through hole 730. A dielectric layer 740 and a bonding pad 10 disposed in the dielectric layer 740 and in contact with the through-hole 730. In some embodiments, the bonding pad 10 is electrically connected to the main main component 710 for electrical conduction through the through hole 730. In some embodiments, the top surface 102 of the bonding pad 10 is coplanar with the upper surface 742 of the dielectric layer 740. In some embodiments, the bonding pad 10 has a thickness of less than 0.2 microns.

It is worth noting that the metal layer 760 recessed into the dielectric layer 740 is subjected to mechanical stress during the planarization process. This stress often causes deformation of the bonding pad 10, and cracks are generated at the corners of the bonding pad 10 to cause bonding defects or deterioration of the semiconductor structure 70. Therefore, the contour of the bonding pad 10 is designed to have included angles α, β, φ, and δ so as to release stress during the planarization process. In addition, the bridge member 40 provided between the inner ring member 20 and the outer ring member 30 serves as a dielectric layer 740 to be prevented from being excessively polished, and the space between the inner ring member 20, the outer ring member 30, and the bridge member 40 can be used for Cooling.

13 to 16 illustrate the formation of a semiconductor structure 70A according to an alternative embodiment of the present disclosure. Unless otherwise stated, the materials and forming methods of the components in these embodiments are basically the same as those of the same components in the embodiments shown in FIGS. 4 to 12, and these components are denoted by the same reference numerals. . Details of the same components shown in FIGS. 13 to 16 can be found in the discussion of the embodiment shown in FIGS. 4 to 12.

Referring to FIG. 13, in some embodiments, the semiconductor structure 70A further includes a barrier layer 770 and a seed layer 780 disposed in the recessed pattern 744 of the dielectric layer 740, wherein the bonding pad 10 is blocked by the seed layer 780 and is blocked. A layer 770 surrounds the seed layer 780. In some embodiments, the barrier layer 770 is in contact with the insulating layer 720 and the via 730.

The formation process of the semiconductor device 70A is similar to the process of forming the semiconductor structure 70 shown in FIGS. 1 and 2, as shown in FIGS. 11 and 12, except that the formation of the semiconductor structure 70A includes an additional step after forming the recessed pattern 744. . For example, FIGS. 14 to 16 illustrate cross-sectional views of the formation stages of the semiconductor structure 70A shown in FIG. 13. In these exemplary embodiments, after the recessed pattern 744 is formed, according to step 616 in FIG. 3, a barrier layer 770 is deposited to extend along the upper surface 742 of the dielectric layer 740 and enter the recessed pattern 744. In some embodiments, the barrier layer 770 is used as an adhesive layer. In some embodiments, the barrier layer 770 is a substantially conformal layer. In some embodiments, the barrier layer 770 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium silicon nitride (TiSN), tantalum silicon nitride (TaSiN )Wait. In some embodiments, the barrier layer 770 may be formed through, for example, physical vapor deposition (PVD).

Referring to FIG. 15, in some embodiments, according to step 618 in FIG. 3, a seed layer 780 is deposited over the barrier layer 770. In some embodiments, the seed layer 780 may be blanket-formed over the barrier layer 770. In some embodiments, the seed layer 780 has a uniform thickness. In some embodiments, the seed layer 780 includes copper or a copper alloy, and may further include a metal such as tungsten, silver, gold, aluminum, and combinations thereof. In some embodiments, the seed layer 780 is formed by a physical vapor deposition process. In other embodiments, other methods may be used, such as electroplating or electroless plating.

Referring to FIG. 16, in some embodiments, a metal layer 760 is deposited on the seed layer 780 according to step 620 in FIG. 3. The process steps and materials used to form the metal layer 760 can be found with reference to the embodiment shown in FIG. 10. In some embodiments, a chemical mechanical planarization (CMP) process is then performed to remove portions of the metal layer 760, the seed layer 780, and the barrier layer 770 above the upper surface 742 of the dielectric layer 740 to form the bonding pad 10. Therefore, the semiconductor structure 70A shown in FIG. 13 is completely formed. In the resulting structure, the upper surface 742 of the dielectric layer 740 is coplanar with the top surface 102 of the bonding pad 10.

The present disclosure provides a bonding pad including an inner ring member, an outer ring member, and a plurality of bridge members. The inner ring member has a pair of first inner edges facing each other, a pair of second inner edges facing each other, and a plurality of numbers provided at corners defined by extension lines of the first inner edge and the second inner edge A third inner edge, wherein the first inner edge is connected to the second inner edge through the third inner edge. The outer ring member surrounds the inner ring member and is spaced apart from the inner ring member. The outer ring member has a pair of first outer edges facing each other, a pair of second outer edges facing each other, and a plurality of numbers provided at corners defined by extension lines of the first outer edge and the second outer edge A third outer edge, wherein the first outer edge is connected to the second outer edge through the third outer edge. The bridge member is disposed between the inner ring member and the outer ring member to connect the inner ring member to the outer ring member.

The present disclosure provides a semiconductor structure including a multilayer component, a dielectric layer, and a bonding pad. The dielectric layer is disposed above the multilayer component. The bonding pad is disposed in the dielectric layer and includes an inner ring member, an outer ring member, and a plurality of bridge members. The inner ring member has a pair of first inner edges facing each other, a pair of second inner edges facing each other, and a plurality of numbers provided at corners defined by extension lines of the first inner edge and the second inner edge Third inner edge. The first inner edge is connected to the second inner edge through the third inner edge. The outer ring member surrounds the inner ring member and is spaced apart from the inner ring member. The outer ring member has a pair of first outer edges facing each other, a pair of second outer edges facing each other, and a plurality of numbers provided at corners defined by extension lines of the first outer edge and the second outer edge Third outer edge. The first outer edge is connected to the second outer edge through the third outer edge. The bridge member is disposed between the inner ring member and the outer ring member to connect the inner ring member to the outer ring member.

The disclosure further provides a method for manufacturing a semiconductor structure. The manufacturing method includes the steps of: providing a multilayer component; depositing a dielectric layer over the multilayer device; forming a recessed pattern in the dielectric layer; and depositing a metal layer in the recessed pattern.

Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the scope of the patent application. For example, many of the processes described above can be implemented in different ways, and many of the processes described above can be replaced with other processes or combinations thereof.

Moreover, the scope of the present application is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods and steps described in the description. Those skilled in the art can understand from the disclosure of this disclosure that according to this disclosure, they can use existing, or future developmental processes, machinery, manufacturing, materials that have the same functions or achieve substantially the same results as the corresponding embodiments described herein. Composition, means, method, or step. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included in the scope of the patent application of this application.

10‧‧‧Joint pad
20‧‧‧Inner ring member
30‧‧‧ outer ring member
40‧‧‧bridge member
50‧‧‧ inner notch
52‧‧‧Outer notch
70‧‧‧semiconductor structure
70A‧‧‧Semiconductor Structure
102‧‧‧Top
210‧‧‧first inner edge
212‧‧‧ extension line
220‧‧‧ Second inner edge
222‧‧‧ extension line
230‧‧‧ Third inner edge
310‧‧‧ first outer edge
312‧‧‧ extension line
320‧‧‧ second outer edge
322‧‧‧ extension line
330‧‧‧ Third outer edge
600‧‧‧ Method
602‧‧‧ steps
604‧‧‧step
606‧‧‧step
608‧‧‧step
610‧‧‧step
612‧‧‧step
614‧‧‧step
616‧‧‧step
618‧‧‧step
620‧‧‧step
622‧‧‧step
700‧‧‧ multilayer components
710‧‧‧Main components
720‧‧‧ Insulation
722‧‧‧upper surface
730‧‧‧ buried hole
732‧‧‧ buried hole
740‧‧‧Dielectric layer
742‧‧‧upper surface
744‧‧‧ Depression Pattern
750‧‧‧Photoresist layer
752‧‧‧Photoresist pattern
754‧‧‧ opening
760‧‧‧metal layer
770‧‧‧Barrier layer
780‧‧‧ seed layer
A‧‧‧Area
D1‧‧‧distance
D2‧‧‧distance
L1‧‧‧first length
L2‧‧‧Second Long
W‧‧‧Width
W1‧‧‧first width
W2‧‧‧Second width
W3‧‧‧ third width α‧‧‧ angle β‧‧‧ angle δ‧‧‧ angle φ‧‧‧ angle

When referring to the drawings combined with the embodiments and the scope of the patent application, the disclosure in this application can be understood more fully. The same component symbols in the drawings refer to the same components.
FIG. 1 is a top view illustrating a bonding pad of some embodiments of the present disclosure.
FIG. 2 is an enlarged view of a region A in FIG. 1.
FIG. 3 is a flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.
4 to 11 are cross-sectional views illustrating stages of forming a semiconductor structure according to some embodiments of the present disclosure.
FIG. 12 is a top view illustrating stages of forming a semiconductor structure according to some embodiments of the present disclosure.
FIG. 13 is a cross-sectional view illustrating a semiconductor structure according to some embodiments of the present disclosure.
14 to 16 are cross-sectional views illustrating stages of forming a semiconductor structure according to some embodiments of the present disclosure.

Claims (12)

A bonding pad includes: an inner ring member having a pair of first inner edges facing each other, a pair of second inner edges facing each other, and an extension line provided by the first inner edge and the second inner edge A plurality of third inner edges at the defined corner, wherein the first inner edge is connected to the second inner edge through the third inner edge; an outer ring member surrounds the inner ring member and is separated from the inner ring member Open, wherein the outer ring member has a pair of first outer edges facing each other, a pair of second outer edges facing each other, and a corner disposed at an angle defined by an extension line of the first outer edge and the second outer edge A plurality of third outer edges, wherein the first outer edge is connected to the second outer edge through the third outer edge; and a plurality of bridge members are disposed between the inner ring member and the outer ring member, and Connect the inner ring member to the outer ring member. The bonding pad according to claim 1, wherein an angle between the third inner edge and the first inner edge is about 135 degrees, and an angle between the third inner edge and the second inner edge is about 135 degrees . The bonding pad of claim 2, wherein the first outer edge is substantially parallel to the first inner edge, and the second outer edge is substantially parallel to the second inner edge. The bonding pad of claim 1, wherein a first distance between two adjacent bridge members connected to the first inner edge is substantially smaller than that of two adjacent bridge members connected to the second inner edge. A second distance between them. The bonding pad according to claim 1, wherein the inner ring member further includes a plurality of inner notches provided on the first inner edge and the second inner edge, and the first outer edge and the second inner edge A plurality of outer notches on the outer edge. The bonding pad of claim 5, wherein the inner notch is equidistant from the third inner edge, and the outer outer notch is equidistant from the third outer edge. The bonding pad according to claim 6, wherein the inner notch is arranged between the third inner edge and the bridge member closest to the third inner edge, and the outer notch is provided at the third outer edge The third outer edge position is closest to the bridge member. The bonding pad according to claim 6, wherein the inner recess and the outer recess are respectively provided on the first inner edge and the first outer edge, or are respectively provided on the second inner edge and the second outer edge. Placed away from each other on the edges. The bonding pad according to claim 1, wherein the inner ring member and the outer ring member have a uniform width. The bonding pad of claim 8, wherein the width of the inner ring member is equal to twice a width of the bridge member. A semiconductor structure includes: a multilayer component; a dielectric layer disposed above the multilayer component; and a bonding pad disposed within the dielectric layer and including: an inner ring member having a pair of opposite to each other A first inner edge, a pair of second inner edges facing each other, and a plurality of third inner edges disposed at a corner defined by an extension line of the first inner edge and the second inner edge, wherein the first inner edge The inner edge is connected to the second inner edge through the third inner edge; an outer ring member surrounds the inner ring member and is separated from the inner ring member, wherein the outer ring member has a pair of first outer edges opposite to each other A pair of second outer edges opposite to each other, and a plurality of third outer edges disposed at a corner defined by an extension line of the first outer edge and the second outer edge, wherein the first outer edge passes through the A third outer edge is connected to the second outer edge; and a plurality of bridge members are provided between the inner ring member and the outer ring member, and the inner ring member is connected to the outer ring member. The semiconductor structure according to claim 11, wherein the multilayer component includes: a main component; an insulating layer provided above the main component; and at least one through hole provided in the insulating layer, wherein the main component passes through The through hole is electrically coupled to the bonding pad.