TWI676134B - Accelerated calculating architecture for proof of work in blockchain based on lookup table method - Google Patents

Abstract

The invention discloses an accelerated calculus framework for proof of work in a blockchain based on a look-up table method. The accelerated calculus architecture includes a DAG page data acquisition circuit, a position update circuit, a first workload proof circuit, a second workload proof circuit, a judgment circuit, a nonce value temporary storage memory, a data storage circuit, and A comparison circuit. Because the accelerated calculus architecture can calculate the same DAG page data in synchronization with the main calculus architecture, it gets rid of the bottleneck of proof of workload in general blockchain based on table lookup method, which can greatly reduce the need to find the solution of proof of workload algorithm time.

Description

Accelerated calculus framework for proof-of-work in blockchain based on look-up table method

The invention relates to an accelerated calculus architecture, in particular to an accelerated calculus framework for proof of work in a blockchain based on a table lookup method.

Blockchain (Blockchain) is based on the individual computing power of countless small miners (mining machines), a huge network of cloud-based distributed storage computing power. The entire blockchain must achieve the important core goals of decentralization and immutability. Miner rewards (virtual currency) are given to the fastest completion of the bookkeeping step based on the record of the completed transaction ledger. Therefore, all major IC design manufacturers have invested in the development of ASIC chips that increase computing power.

Due to the low price, mass production, and powerful computing power of ASICs, it has resulted in a weak point where the computing power is too concentrated. Therefore, the organization headed by Ethereum has proposed a form based on a large number of units generated by Directed Acyclic Graph (DAG) as a table inspection mining inspection algorithm. The form has a high number of storage bits, so it can only be stored in SDRAM. The bandwidth limitation of SDRAM limits the computing power, thereby limiting the unfair competition of ASIC.

However, the bandwidth limitation of SDRAM can reduce the impact and increase the computing power by other means. The invention proposes an innovative accelerated algorithm here, in particular to accelerate the calculation framework of proof of work in the blockchain based on the look-up table method.

This paragraph extracts and compiles certain features of the invention. Other features will be revealed in subsequent paragraphs. Its purpose is to cover the spirit and scope of the scope of additional patent applications, with various modifications and similar arrangements.

An object of the present invention is to provide an accelerated calculus architecture for proof-of-work in a blockchain based on a look-up table method, which is used to execute the same header hash value and different regions in synchronization with a main calculus architecture. The segment nonce value proof-of-work operation includes a DAG (Directed Acyclic Graph) page data acquisition circuit connected to the main calculus architecture signal to obtain the nonce in the first segment obtained by the main calculus architecture. A DAG page data and a DAG index of the workload proof operation program; a first workload proof circuit, which sequentially performs a first round of work on each nonce value in the second section and the header hash value Quantity proof operation to obtain an initial position value; a second workload proof circuit for the nonce value and the header hash value in the memory section corresponding to the DAG page index in the second section, and the DAG Page data performs a second workload proof operation to obtain an updated position value; a judgment circuit is connected to the second workload proof circuit signal to determine whether a state value corresponding to the nonce value is greater than a calculation Count the threshold value, if the state value is not greater than the threshold of the number of calculations, add 1 to the state value, and output the nonce value and the corresponding state value according to the judgment result; Segments are used to temporarily store nonce values and their corresponding status values, where each group of nonce values and status values are stored in the same memory segment; a position update circuit, the DAG page data acquisition circuit, the The second proof of work circuit and the judgment circuit are connected to obtain all nonce values and corresponding state values in the memory section corresponding to the DAG indicator, and send the header hash value and the DAG page data together. Give the second workload proof circuit, receive a state value from the judgment circuit that is not greater than the threshold of the number of calculations and a corresponding nonce value, and an updated position value from the second workload proof circuit corresponding to the aforementioned nonce value, and set An update program to update the aforementioned nonce value and corresponding state value to the memory section corresponding to the updated position value; and a data storage circuit, the first workload proof circuit, The position update circuit and the nonce value temporary memory signal are connected to store the nonce value and the state value of 0 in the corresponding memory section according to the initial position value, execute the update procedure, and follow the The DAG indicator finds a memory segment corresponding to the DAG index, and returns all nonce values and corresponding status values in the foregoing memory segment.

Preferably, the threshold of the number of calculations may be 63.

Preferably, the first workload proof circuit may further include: a first SHA-3 arithmetic unit for sequentially performing a SHA-3 operation on the header hash value and different nonce values; and a first A mixing unit is used to mix the results of the SHA-3 operation and perform the FNV operation to obtain different initial position values.

Preferably, the first workload proof circuit may further include: a second SHA-3 operation unit for performing a SHA-3 operation on the header hash value and different nonce values; and a second mixed operation A unit for mixing SHA-3 operation results with the DAG page data and performing FNV operations to obtain different update position values.

Preferably, the correspondence between the DAG index and the memory segment may be a one-to-one correspondence in sequence.

Preferably, the DAG indicator may be the same as the numerical pattern of the initial position value or the updated position value.

Preferably, the data storage circuit can conform to the Advanced eXtensible Interface (AXI) protocol architecture specification.

Preferably, the accelerated calculation architecture may further include a comparison circuit connected to the judgment circuit signal, receiving a nonce value corresponding to a state value from the judgment circuit that is greater than the calculation number threshold, and the update position value, and the update The position value executes a post-execution function to obtain a mixed digest, compares the mixed digest with a target threshold, and sends the nonce value when the mixed digest is less than the target threshold.

Preferably, the DAG page data acquisition circuit can temporarily store the number of DAG pages and DAG indicators, and provide DAG page data and DAG indicators according to a First In, First Out (FIFO) method.

Preferably, the nonce value temporary storage memory may be a Synchronous Dynamic Random Access Memory (SDRAM).

According to the present invention, since the accelerated calculus architecture can calculate the same DAG page data in synchronization with the main calculus architecture, it gets rid of the bottleneck of proof of workload in the general blockchain based on table lookup method, which can greatly reduce the need to find proof of workload Algorithmic solution time.

The present invention will be described more specifically by referring to the following embodiments.

Before starting to explain the technical features of the present invention, the operation method of the proof of workload in the blockchain based on the table lookup method applied to the subject of the present invention. Please refer to Figure 1, which is a flowchart of the Ethereum's proof-of-work algorithm, Ethash. It is worth noting that the present invention is not limited to application in Ethash-related blockchain architectures; on the contrary, as long as the proof of workload of any blockchain is based on a look-up table method, the internal data of the memory is calculated instead of relying on a large number of All hardware resources to process can be the object of the application of the present invention. Figure 1 reveals that Ethash initially obtained the Hash of the current Preprocessed Header 32-Byte, plus any specified 8-Byte nonce value (a continuous integer value expressed in two bits) To perform SHA3-like function operations. The operation result of this type of SHA3 function is called Mix, and Mix 0 represents the first operation result. After further calculation, Mix obtained the position of the 128-Byte DAG (Directed Acyclic Graph) page, and obtained data according to the position to the corresponding position of the DAG stored in the computer memory. The obtained data is combined with Mix 0 and a mixed function calculation is performed to obtain the next Mix value, Mix 1. The operation of Mix operation is repeated 64 times until Mix64 is obtained. Mix64 performs function processing after getting a 32-Byte mixed digest. The mixed digest will be compared with a preset 32-Byte target threshold. If the mixed digest is less than the target threshold, the current nonce value meets the requirements of the Ethash algorithm, the operation result is successful and the nonce value is sent out. Otherwise, the operation fails and the next nonce value will be used to re-execute all the above processes.

There will be many nonce values that meet the target threshold, so the entire Ethash algorithm uses a brute force method (or exhaustive method) to find the solution. Each computer that participates in the proof of work has a certain level of computing power, but because it needs to frequently obtain data in the memory for calculation, there will not be a disguised "centralization" in which the computing power is too concentrated. As can be seen from the above description, the natural bottleneck (latency) of the Ethash algorithm exists in the bandwidth limitation of memory access. To solve this problem, it is unrealistic to rely on copying the DAG to other external memory for synchronous calculation, because the DAG will increase its content every 100 hours (currently its content is about 2GB), and the delay is the problem still exists. However, another feasible method is to synchronize the obtained DAG page data with all other required nonce values for partial calculations, and repeatedly calculate the calculation results with the newly acquired DAG page data until there is a final mixed summary obtained from the nonce values. Less than the target threshold. This is the spirit of the present invention, and an embodiment thereof is illustrated in FIG. 2.

In Figure 2, an accelerated calculus architecture for proof-of-work in a blockchain based on a look-up table method is used to execute the same header hash value and different sections in synchronization with a main calculus architecture 1 Nonce value proof-of-work operation (ie Ethash algorithm). The main calculus architecture 1 is the hardware that executes related programs according to the requirements of the Ethash algorithm. In contrast, the accelerated calculus architecture is only used to perform part of the requirements of the Ethash algorithm, and does not actually go to memory (such as an SDRAM) to obtain the required DAG page data. In addition, the accelerated calculus architecture stores many nonce values that need to correspond to DAG page data, and after the nonce value passes the workload proof operation program 64 times, the nonce value that satisfies the mixed digest less than the target threshold is sent directly to the blockchain. Each node proves the workload of completing a block without having to pass the main calculus architecture1. The difference between the main calculus architecture 1 and the accelerated calculus architecture also includes the difference in the nonce value of the operation. If the main calculus architecture 1 calculates nonce values in sequence from 0 down to half of the total number, the nonce value of the accelerated calculus calculation operation can start from the next half of the total number to the last nonce value. In addition, the main calculus architecture 1 and accelerated calculus architecture can also assign different numbers of nonce according to different computing power, such as 1: 2. However, for one main calculus architecture 1, more than one accelerated calculus architecture can be matched, and each calculus architecture is responsible for a different nonce value, which can speed up the workload proof operation.

The accelerated calculus architecture includes a DAG page data acquisition circuit 10, a position update circuit 20, a first workload proof circuit 30, a second workload proof circuit 40, a judgment circuit 50, and a nonce value temporary storage memory 60. A data storage circuit 70 and a comparison circuit 80. The functions and interactions of the aforementioned elements are detailed below.

The DAG page data acquisition circuit 10 is connected to the main calculus structure 1 for obtaining a DAG page data and a DAG index obtained by the main calculus structure 1 and used to perform a workload proof operation procedure on a nonce value in a first section. The nonce value in the first section is handled by the main calculus architecture 1. The nonce value in the second section mentioned later is handled by the accelerated calculus architecture. The allocation of the number of nonce between the two sections has been mentioned above and will not be repeated here. In some embodiments, the DAG page data acquisition circuit 10 may also temporarily store the number of DAG pages and DAG indicators, and provide DAG page data and DAG indicators according to a First In, First Out (FIFO) method.

The first workload proof circuit 30 sequentially performs a first workload proof operation on each nonce value in the second section and the header hash value to obtain an initial position value. Here, the first workload proof circuit 30 mainly performs the procedure of obtaining Mix 0 in FIG. 1. Both the initial position value and the DAG index are obtained in accordance with the Ethash algorithm. The position information points to a page in the DAG, and the numerical values of the two are the same. However, for convenience of explanation, the DAG indicator from the main calculus structure 1 is also called a DAG indicator. The DAG indicator calculated in the accelerated calculus structure has initial position values and updated position values according to different sources. Since the program for obtaining Mix 0 includes two main sub-algorithms, the first workload proof circuit 30 can be further divided into a first SHA-3 arithmetic unit 32 and a first hybrid arithmetic unit 34. The first SHA-3 operation unit 32 is used to sequentially perform a SHA-3 operation on the header hash value of the current block and different nonce values, and the first mixed operation unit 34 is used to perform the SHA-3 operation. After the operation results are mixed, FNV operation is performed to obtain different initial position values.

The second proof-of-work circuit 40 may perform a second proof-of-work operation on the DAG page data for a nonce value in the memory section corresponding to the DAG page index in the second section and the header hash value. Update the position value. Here, the second workload proof circuit 40 mainly performs a program for obtaining Mix 1 to Mix 64 in FIG. 1. Similarly, the updated position value and the DAG index are both obtained according to the Ethash algorithm. To point to the position information of a page in the DAG, the numerical values of the two are the same. Since the program for obtaining Mix 1 ~ Mix 64 also includes two main sub-algorithms, the second workload proof circuit 40 can be further divided into a second SHA-3 arithmetic unit 42 and a first hybrid arithmetic unit 44. The first SHA-3 operation unit 32 is used to sequentially perform a SHA-3 operation on the header hash value of the current block and different nonce values, and the first mixed operation unit 34 is used to perform the SHA-3 operation. After the operation results are mixed, FNV operation is performed to obtain different initial position values. The second SHA-3 operation unit 42 is used to perform a SHA-3 operation on the header hash value and different nonce values, and the second mixing operation unit 44 is used to perform the operation after mixing the SHA-3 operation result with the DAG page data. FNV operations to obtain different update position values. In this embodiment, it should be noted that the first workload proof circuit 30 will only perform one operation on one nonce value, but the second workload proof circuit 40 will perform a maximum of 64 on each nonce value due to luck. Operations, at least 0 operations.

The judging circuit 50 is connected to the second workload proof circuit 40 by a signal, and is used to judge whether a state value corresponding to the nonce value is greater than a threshold value of calculations. If the state value is not greater than the threshold value of calculations, the status value is increased by 1, The nonce value and the corresponding state value are output separately according to the judgment result. According to different proof-of-work algorithms, the number of second proof-of-work operations performed will be different. In this embodiment, the threshold for the number of calculations is the number of second workload proof operations minus 1,63. That is, after the nonce value is controlled 64 times by the judgment circuit 50, the nonce value may be a solution of the Ethash algorithm. Therefore, if other proof-of-work algorithms adjust the number of second proof-of-work operations, the threshold of the number of calculations will also change.

Nonce value temporary memory 60, such as a synchronous dynamic random access memory (SDRAM), has a plurality of memory segments (each memory segment has the same number of memory cells), Used to temporarily store nonce values and their corresponding status values. Each set of nonce value and status value is stored in the same memory section, and its data storage form will be explained by an operation example later.

The position update circuit 20 is connected to the DAG page data acquisition circuit 10, the second workload certification circuit 40, and the determination circuit 50, and is used to obtain all nonce values and corresponding state values 40 in the memory section corresponding to the DAG index. The nonce values and status values are sent to the second workload certification circuit 40 together with the header hash value and the DAG page data. In addition, the position update circuit 20 may also receive the state value from the judgment circuit 50 that is not greater than the threshold value of the calculation times and the corresponding nonce value, and the updated position value from the second workload proof circuit 40 corresponding to the aforementioned nonce value, and set a The update program updates the nonce value and the corresponding status value to the memory segment corresponding to the update position value. The foregoing update procedure and the nonce value, the updated status value, and the updated position value can be used to request the data storage circuit 70 to perform a memory segment update (deleting the nonce value in the original memory segment and the old status value, The nonce value and the updated status value are temporarily stored in the memory section corresponding to the update position value). The correspondence between the memory segment and the DAG index, the initial position value, and the updated position value will be described here. Please refer to FIG. 3, which is a diagram illustrating initialization of the nonce value temporary storage memory 60. In order to simplify the description, the following description and the following operation examples assume that there are only 10 DAG pages of data (Page 1 to Page 10) in the DAG, and the corresponding DAG index is only 10 (Index-1 to Index-10). It is millions of times. According to the present invention, the correspondence between the DAG index and the memory segment is a one-to-one correspondence. That is to say, 10 memory sections (Section 1 to Section 10) are set in the nonce value temporary storage memory 60, and each memory section is pointed by a DAG indicator. Since the initial position value and the updated position value are DAG indicators (obtained in different places), the initial position value or the updated position value will also correspond to a memory segment, but the initial position value of each nonce value and the update of subsequent calculations The position value will be different (the calculated DAG indicator has changed).

The data storage circuit 60 is connected to the first workload proof circuit 30, the position update circuit 20, and the nonce value temporary storage memory 60. Its function is to store the nonce value and the state value of 0 in the corresponding memory area according to the initial position value. Segment, execute the update procedure of the position update circuit 20, and find out the corresponding memory segment according to the DAG index from the position update circuit 20, and return all nonce values and corresponding status values in the aforementioned memory segment The position update circuit 20 is used for calculation by the second workload proof circuit 40. In practice, the data storage circuit 60 can conform to the Advanced eXtensible Interface (AXI) protocol architecture specification, so as to achieve fast and effective data access between circuits.

The comparison circuit 80 is connected to the judgment circuit 50, and can receive the nonce value and the updated position value corresponding to the state value from the judgment circuit 50 that is greater than the threshold value of the calculation times, execute the updated position value and execute the function to obtain A mixed digest (Mix Digest), comparing the mixed digest with a target threshold, and sending the nonce value when the mixed digest is less than the target threshold. That is, the comparison circuit 80 performs the steps included in the dotted line frame in FIG. 1.

Next, an operation example is used to explain the operation of the accelerated calculus architecture.

Please refer to FIGS. 3 to 9 at the same time. As mentioned above, FIG. 3 is the correspondence between the nonce value temporary storage memory 60 and the DAG index when the accelerated calculation framework has not yet started to perform calculations. In this operation example, it is assumed that the total number of nonce is 20 (nonce values 1 to 20). The main calculus architecture 1 processes nonce values from 1 to 10, and the accelerated calculus framework processes nonce values from 11 to 20. In fact, more than 20 nonce values are used in proof-of-work calculations for a block. When the main calculus architecture 1 started to operate on the first nonce value, 1, it found that the DAG index Index-4 and the corresponding DAG page data Page 4 were needed, so it took some time to obtain. At the same time, the first workload proof circuit 30 performs operations on the nonce values 11 to 15 and obtains the initial position values Index-2, Index-6, Index-9, Index-4, and Index-6, respectively. Therefore, the data storage circuit 70 fills the nonce values 11 to 15 into the memory sections Section 2, Section 6, Section 9, Section 4 and Section 6, as shown in FIG. 4. Next, the DAG page data acquisition circuit 10 obtains the DAG index Index-4 and the DAG page data Page 4 from the main calculus architecture 1, and obtains all nonce values and their correspondences in the memory section corresponding to the DAG index through the position update circuit 20. The state value, that is, the nonce value 14 and the state value 0, are sent to the second workload proof circuit 40 for calculation together with the header hash value of the current block and the DAG page data Page 4. The second workload proof circuit 40 obtains the updated position value, Index-3. At the same time, the judging circuit 50 judges that the state value 0 corresponding to the nonce value 14 is not greater than the threshold of the number of calculations, so the updated position value Index-3, the nonce value 14 and the state value 1 are given to the position update circuit 20 to set the update program. Further, the data in the original memory section Section 4 is emptied through the data storage circuit 70, and the memory section Section 3 temporarily stores the nonce value 14 and the state value 1, as shown in FIG. 5.

Then, the main calculus architecture 1 starts to perform operations on the second nonce value, 2. The main calculation framework 1 calculated the DAG index Index-6 and the corresponding DAG page data Page 6 and also took some time to obtain it. At the same time, the first workload proof circuit 30 performs operations on the nonce values 16 to 20, and obtains the initial position values Index-4, Index-7, Index-1, Index-4, and Index-6, respectively. Therefore, the data storage circuit 70 fills the nonce values 16 to 20 into the memory sections Section 4, Section 7, Section 1, Section 4 and Section 6, as shown in FIG. 6. Next, the DAG page data acquisition circuit 10 obtains the DAG index Index-6 and the DAG page data Page 6 from the main calculus architecture 1, and obtains all nonce values in the memory section corresponding to the DAG index and their correspondence through the position update circuit 20. The state values are nonce value 12 and state value 0, nonce value 15 and state value 0 and nonce value 20 and state value 0. The position update circuit 20 sends the foregoing data together with the header hash value of the current block and the DAG page data Page 6 to the second workload proof circuit 40 for calculation. The second workload proof circuit 40 thus calculates the updated position values Index-5, Index-6, and Index-10 for the nonce values 12, 15, and 20, respectively. The judging circuit 5 sequentially judges that the state value 0 corresponding to each nonce value is not greater than the threshold of the number of calculations, so each updated position value is given to the position update circuit 20 along with its nonce value 14 and the state value 1 which is added by 1. Therefore, the data storage circuit 70 empties the data in the original memory section 6 and temporarily stores the nonce value 12 and the state value 1 in the memory section 5 and the memory section 10 temporarily stores the nonce value 20 and The state value is 1, and the memory section Section 6 temporarily stores the nonce value and the state value 1, as shown in FIG. 7.

After completing two rounds of calculations, the main calculus architecture 1 starts to operate on the third nonce value, 3. The main calculation framework 1 calculates the DAG index Index-10 and the corresponding DAG page data Page 10. At this time, the first workload proof circuit 30 is no longer operable. However, this is rarely the case in practice unless the number of accelerated calculus architectures and main calculus architecture 1 is high. Therefore, before the DAG page data acquisition circuit 10 starts the operation, the data in the memory section does not change, as shown in FIG. 8. Next, the DAG page data acquisition circuit 10 obtains the DAG index Index-10 and the DAG page data Page 10 from the main calculus architecture 1, and obtains all nonce values and their correspondences in the memory section corresponding to the DAG index through the position update circuit 20. The status value, namely the nonce value of 20 and the status value of 1. The position update circuit 20 sends the foregoing data together with the header hash value of the current block and the DAG page data Page 10 to the second workload certification circuit 40 respectively for calculation. The second workload proof circuit 40 thus calculates the update position value Index-7 for the nonce value 20. The judging circuit 5 sequentially judges that the state value 1 corresponding to each nonce value is not greater than the threshold of the number of calculations, so the updated position value is given to the position update circuit 20 along with its nonce value 20 and the state value 2 added by 1. Therefore, the data storage circuit 70 clears the data in the original memory section Section 10 and temporarily stores the nonce value 20 and the state value 2 in the memory section 7 as shown in FIG. 9.

After continuously repeating the foregoing steps, there will eventually be a state value of nonce value greater than 63. The nonce value may be the solution of the Ethash algorithm, so it will be sent to the comparison circuit 80 for subsequent processing. Of course, a number of nonce values that satisfy this condition will be calculated in sequence, and will also be sent to the comparison circuit 80 for subsequent processing. The whole operation will complete the proof of work for a block in about 15 seconds, and restart it (that is, the main calculus architecture 1 restarts from the nonce value 1 to find a solution that meets this round).

Although the present invention has been disclosed as above in the embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

1‧‧‧ lead calculus structure

10‧‧‧DAG page data acquisition circuit

20‧‧‧Position update circuit

30‧‧‧First workload proof circuit

32‧‧‧The first SHA-3 arithmetic unit

34‧‧‧The first mixed arithmetic unit

40‧‧‧Second workload proof circuit

42‧‧‧Second SHA-3 arithmetic unit

44‧‧‧Second Mixed Computing Unit

50‧‧‧ Judgment Circuit

60‧‧‧nonce value temporary memory

70‧‧‧Data storage circuit

80‧‧‧ comparison circuit

FIG. 1 is a workload proof algorithm used in the conventional technology; FIG. 2 is an accelerated algorithm framework for workload proof in a blockchain based on a table lookup method according to an embodiment of the present invention; Figure 9 illustrates an example of the operation of the accelerated calculus architecture.

Claims (10)

An accelerated calculus architecture for proof-of-work in a blockchain based on a look-up table method, used to perform the same proof-of-work workload for the same Header hash value and nonce value in different sections in synchronization with a main calculus architecture , Including: A DAG (Directed Acyclic Graph) page data acquisition circuit, connected to the main calculus architecture signal, used to obtain the main calculus architecture to obtain a workload proof operation program for a nonce value in a first section A DAG page of data and a DAG indicator; a first workload proof circuit, which sequentially performs a first workload proof operation on each nonce value and the header hash value in a second section to obtain an initial Position value; a second workload proof circuit that performs a second round of work on the nong value and the header hash value in the memory section corresponding to the DAG page index in the second section Quantity proof operation to obtain an updated position value; a judging circuit connected to the second workload proof circuit signal to determine whether a state value corresponding to the nonce value is greater than a threshold value of a calculation number, if the state value When the threshold is exceeded, the state value is increased by 1, and the nonce value and the corresponding state value are respectively output according to the judgment result. A nonce value is temporarily stored in the memory, and a plurality of memory sections are used for temporary storage. nonce value and corresponding state value, wherein each group of nonce value and state value are stored in the same memory section; a position update circuit, the DAG page data acquisition circuit, the second workload proof circuit and the The judging circuit signal is connected to obtain all nonce values and corresponding state values in the memory segment corresponding to the DAG indicator, and send them to the second workload certification circuit together with the header hash value and the DAG page data. Receive a state value from the judging circuit that is not greater than the threshold of the number of calculations and a corresponding nonce value, and an updated position value corresponding to the aforementioned nonce value from the second workload proof circuit, and set an update program to convert the aforementioned nonce value Update the corresponding state value to the memory section corresponding to the updated position value; and a data storage circuit, the first workload proof circuit, the position update circuit, and the The nonce value temporarily stores the memory signal connection, which is used to store the nonce value and the state value of 0 in the corresponding memory section according to the initial position value, execute the update process, and find out according to the DAG index from the position update circuit. A corresponding memory segment, and returns all nonce values and corresponding status values in the foregoing memory segment. The accelerated calculus architecture described in item 1 of the scope of patent application, wherein the threshold for the number of calculus times is 63. The accelerated calculus architecture according to item 1 of the scope of patent application, wherein the first workload proof circuit further comprises: a first SHA-3 arithmetic unit for sequentially hashing the header with a different nonce value A SHA-3 operation is performed; and a first mixed operation unit is used to mix the results of the SHA-3 operation and perform the FNV operation to obtain different initial position values. The accelerated calculus architecture according to item 1 of the scope of patent application, wherein the first workload proof circuit further comprises: a second SHA-3 arithmetic unit for performing a hash of the header with a different nonce value. SHA-3 operation; and a second hybrid operation unit, which is used to mix the SHA-3 operation result with the DAG page data and perform FNV operation to obtain different update position values. The accelerated calculus architecture described in item 1 of the scope of patent application, wherein the corresponding relationship between the DAG index and the memory segment is a one-to-one correspondence. The accelerated calculus architecture described in item 1 of the scope of the patent application, wherein the DAG index has the same numerical form as the initial position value or the updated position value. The accelerated calculus architecture described in item 1 of the patent application scope, wherein the data storage circuit complies with the Advanced eXtensible Interface (AXI) protocol architecture specification. The accelerated calculation architecture described in item 1 of the scope of the patent application, further comprising a comparison circuit connected to the judgment circuit signal, and receiving a nonce value corresponding to a state value from the judgment circuit that is greater than the threshold value of the calculation times and the update. Position value, execute a post-execution function to obtain a mixed digest (Mix Digest), compare the mixed digest with a target threshold, and set the nonce value when the mixed digest is less than the target threshold Submit. The accelerated calculus architecture described in item 1 of the scope of patent application, wherein the DAG page data acquisition circuit temporarily stores the number of DAG pages and DAG indicators, and provides DAG pages according to the First In, First Out (FIFO) method Data and DAG indicators. The accelerated calculus architecture according to item 1 of the scope of patent application, wherein the nonce value temporary storage memory is a Synchronous Dynamic Random Access Memory (SDRAM).