TWI666638B - Memory circuit and data bit status detector thereof - Google Patents

Abstract

A memory circuit and a data bit state detector are proposed. The data bit state detector includes a sense amplifier circuit, a data receiving circuit, and a reference circuit. The sensing amplifier circuit has a first sensing input terminal and a second sensing input terminal. The sense amplifier circuit senses and amplifies the difference between the first impedance on the first sensing input terminal and the second impedance on the second sensing input terminal to generate a sensing output signal. The data receiving circuit receives a plurality of bits of the data signal and provides a first impedance between the first sensing input terminal and the reference ground terminal according to the bits of the data signal. The reference circuit receives a plurality of bias voltages, and provides a second impedance between the second sensing input terminal and the reference ground terminal according to the bias voltages.

Description

Memory circuit and data bit state detector

The invention relates to a memory circuit and a data bit state detector thereof, and more particularly to a data bit state detector in the form of an analog circuit.

In the technical field of flash memory, when a data signal is written to the flash memory, the number of bits in the data signal that is at the logic level 0 can be determined, and according to the data signal, the logic The number of bits of level 0 is used to set the stylized ability and perform the stylized action. In the conventional technical field, a data signal can be read out from a static random access memory, and a bit counter in the form of a logic circuit is used to calculate the number of bits of the logic level 0 in the data signal. In addition, according to the calculated number of logic level 0 bits, the conventional flash memory can effectively complete the data signal program by adjusting the driving capacity of the drain voltage generated by the drain boost circuit. (Write) operation.

The conventional technology proposes another type of flash memory. By reading two data signals from the static random access memory, for example, two 8-bit data signals are combined into a 16-bit data signal. . Then, the number of logic zeros in the 16-bit data signal is counted as the execution basis for subsequent programmatic actions.

In any case, in the conventional flash memory, a bit counting circuit for calculating the number of bits in the data signal that is at the logical level 0 is necessary. To accurately calculate the number of bits of the logic level 0, the conventional technology often constructs a bit counting circuit through complex logic circuit designs, and requires a large circuit area.

The invention provides a memory circuit and a data bit state detector. The data bit state detector in the memory circuit is constructed by using an analog circuit to effectively reduce the required circuit area.

The data bit state detector of the present invention includes a sensing amplifier circuit, a data receiving circuit, and a reference circuit. The sensing amplifier circuit has a first sensing input terminal and a second sensing input terminal. The sense amplifier circuit senses and amplifies the difference between the first impedance on the first sensing input terminal and the second impedance on the second sensing input terminal to generate a sensing output signal. The data receiving circuit receives a plurality of bits of the data signal and provides a first impedance between the first sensing input terminal and the reference ground terminal according to the bits of the data signal. The reference circuit receives a plurality of bias voltages, and provides a second impedance between the second sensing input terminal and the reference ground terminal according to the bias voltages.

The memory circuit of the present invention includes the data bit state detector and a multiplexer circuit as described above. The multiplexing circuit is coupled to a plurality of memory cell arrays and a data bit state detector, and is used to sequentially select the memory cell arrays according to the sensed output signal, or to simultaneously select the memory cell arrays to perform the programmed operation.

Based on the above, the present invention uses a data bit state detector in the form of an analog circuit, provides a first impedance according to a data signal through a data receiving circuit, and judges by comparing the first impedance with a second impedance as a reference value. The state of the logic level of the data signal is obtained, and a sensing output signal is generated accordingly. In this way, the present invention can simplify the complexity of circuit setting and effectively reduce the required circuit area.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of a data bit state detector according to an embodiment of the present invention. Referring to FIG. 1, the data bit state detector 100 includes a sense amplifier circuit 110, a data receiving circuit 120, and a reference circuit 130. The sense amplifier circuit 110 has a first sense input terminal ST1 and a second sense input terminal ST2. The sense amplifier circuit 110 is configured to sense and amplify the difference between the first impedance on the first sensing input terminal ST1 and the second impedance on the second sensing input terminal ST2 to generate a sensing output signal SAOUT. The data receiving circuit 120 is coupled between the first sensing input terminal ST1 and the reference ground terminal GND. The data receiving circuit 120 receives the data signal DATA and provides a first impedance between the first sensing input terminal ST1 and the reference ground terminal GND according to a plurality of bits of the data signal DATA. The reference circuit 130 is coupled between the second sensing input terminal ST2 and the reference ground terminal GND. The reference circuit 130 receives a plurality of bias voltages and provides a second impedance between the second sensing input terminal ST2 and the reference ground terminal GND according to the bias voltages.

Specifically, the data receiving circuit 120 may provide the first impedance according to the number of bits of the logic level 0 among the plurality of bits of the received data signal DATA. On the other hand, the reference circuit 130 provides a second impedance according to a plurality of preset bias voltages. In this way, the sensing amplifier circuit 110 can compare the first impedance provided by the data receiving circuit 120 and the second impedance provided by the reference circuit 130 to know that the data receiving circuit 120 can be a logic level according to the data signal DATA. Whether the number of 0 bits is greater than a reference value, and the above reference value can be set by setting the size of the second impedance.

Taking the data signal DATA having 16 bits as an example, in the embodiment of the present invention, if the data signal DATA has less than or equal to 8 bits as the logic level 0, the first impedance value provided by the data receiving circuit 120 Is R1, and if more than 8 bits in the data signal DATA are logic level 0, the first impedance value provided by the data receiving circuit 120 is R2. On the other hand, the reference circuit 130 can be set to provide a second impedance having an impedance value between R1 and R2 according to the received bias voltage. In this way, the data bit state detector 100 can detect whether the number of bits included in the received data signal DATA equal to the logic level 0 is greater than 8, and when the data signal DATA includes an equal logic When there are more than eight bits of level 0, a sensing output signal SAOUT equal to the first logic level is generated. The data bit state detector 100 can also generate a sensing output signal SAOUT equal to the second logic level when the data signal DATA includes less than or equal to 8 bits equal to the logic level 0. The first logic level is different from the second logic level.

FIG. 2 is a schematic diagram of a data bit state detector according to another embodiment of the present invention. Referring to FIG. 2, the data bit state detector 200 includes a sense amplifier circuit 210, a data receiving circuit 220, and a reference circuit 230. The sense amplifier circuit 210 has a first sense input terminal ST1 and a second sense input terminal ST2. The sense amplifier circuit 210 includes inverters IV1 and IV2. An input terminal of the inverter IV1 is coupled to the second sensing input terminal ST2, and an output terminal of the inverter IV1 is coupled to the first sensing input terminal ST1. An input terminal of the inverter IV2 is coupled to the first sensing input terminal ST1, and an output terminal of the inverter IV2 is coupled to the second sensing input terminal ST2. In addition, the inverter IV1 is composed of transistors MP1 and MN5, and the inverter IV2 is composed of transistors MP0 and MN4.

The sense amplifier circuit 210 further includes an enabling switch composed of a transistor MP3 and a MN6. The transistor MP3 is controlled by the upper end enable signal PL_EN to be turned on or off. The inverters IV1 and IV2 receive the power supply voltage VDD through the transistor MP3. The transistor MN6 is controlled by the lower-end enable signal NL_EN to be turned on or off. The inverters IV1 and IV2 pass through the transistor MN6 to be coupled to the reference ground terminal GND and receive the reference ground voltage.

The data receiving circuit 220 is coupled to the first sensing input terminal ST1 of the sensing amplifier circuit 210. The data receiving circuit 220 includes a plurality of transistors MI0 to MI15. The transistors MI0 to MI15 are coupled in parallel with each other, and are coupled between the first sensing input terminal ST1 and the reference ground terminal GND. The control terminals of the transistors MI0 ~ MI15 are respectively controlled by the multiple bits DATA [0:15] of the data signal, and according to the multiple bits DATA [0:15] of the data signal, the first sensing input terminal ST1 Provide a first impedance with the reference ground terminal GND.

On the other hand, the data receiving circuit 220 further includes a pull-down switch composed of the transistor MN1. Transistor MN1 is connected in series between the paths where transistors MI0 ~ MI15 are coupled to the reference ground terminal GND. The transistor MN1 is controlled by the enable signal Cell_EN to be turned on or off.

The reference circuit 230 is coupled to the second sensing input terminal ST2 of the sense amplifier circuit 210. The reference circuit 230 includes a plurality of transistors MR1 to MR2. The transistors MR1 to MR2 are coupled in parallel with each other, and are coupled between the second sensing input terminal ST2 and the reference ground terminal GND. The control terminals of transistors MR1 to MR2 receive different bias voltages respectively (the control terminal of transistor MR1 receives the power supply voltage VDD as the bias voltage, and the control terminal of transistor MR2 is coupled to the reference ground terminal GND to receive the reference ground voltage GND is used as a bias voltage), and a second impedance is provided between the second sensing input terminal ST2 and the reference ground terminal GND. In the embodiment of the present invention, the reference circuit 230 includes another transistor M_MISC. The transistor M_MISC is coupled in parallel with a plurality of transistors MR1 to MR2, and its control terminal receives the power supply voltage VDD as a bias voltage.

On the other hand, the reference circuit 230 further includes a pull-down switch composed of the transistor MN0. Transistor MN0 is connected in series between multiple transistors MR1 to MR2 that are coupled to a reference ground terminal GND. The transistor MN0 is also controlled by the enable signal Cell_EN to be turned on or off.

In this embodiment, the number of the transistors MR1 and MR2 may be one or more each, and the total number of the transistors MR1 and MR2 may be the same as the number of the transistors MI0 to MI15. The on and off states of the transistors MN0 and MN1 are the same.

In the embodiment of the present invention, the data bit state detector 200 further includes capacitors Mcap1, Mcap2, a discharge switch constructed by the transistors MN2, MN3, and output buffers BUF1, BUF2. The capacitors Mcap1 and Mcap2 may be transistor capacitors, and are respectively coupled to the first sensing input terminal ST1 and the second sensing input terminal ST2. The discharge switch constructed by the transistor MN3 is connected in series between the first sensing input terminal ST1 and the reference ground terminal GND, and is turned on or off according to the discharge enable signal DISC. The discharge switch constructed by the transistor MN2 is connected in series between the second sensing input terminal ST2 and the reference ground terminal GND, and is turned on or off according to the discharge enable signal DISC. When the transistors MN3 and MN2 are turned on, the capacitors Mcap1 and Mcap2 perform a discharging operation and pull down the voltage values on the first sensing input terminal ST1 and the second sensing input terminal ST2.

The output buffers BUF1 and BUF2 are respectively coupled to the first sensing input terminal ST1 and the second sensing input terminal ST2. The output buffers BUF1 and BUF2 are inverters, and the output buffers BUF1 and BUF2 are used to invert the logic levels on the first sensing input terminal ST1 and the second sensing input terminal ST2. The output buffer BUF1 is used to generate a sensing output signal SAOUT. The output buffer BUF2 can maintain a floating NC.

FIG. 3A and FIG. 3B respectively illustrate operation waveform diagrams of different operation states of a data bit state detector according to an embodiment of the present invention. The following describes the details of the operation of the data bit state detector 200. Please refer to FIG. 2 and FIG. 3A simultaneously. In the time interval TA1, the upper end enable signal PL_EN is pulled up to a logic high level, and the lower end enable signal NL_EN is pulled down to The logic low level corresponds to this. The transistor MP3 as an enable switch is turned on and the transistor MN6 is turned off. Also in the time interval TA1, the enable signal Cell_EN is pulled up to a logic high level, the transistors MN0 and MN1 are turned on, and the path of the reference circuit 230 and the data receiving circuit 220 connected to the reference ground voltage GND is turned on. In addition, the discharge enable signal DISC is pulled up to a logic high level in the time interval TA1, and the transistors MN2 and MN3 are turned on, and the voltages SAIN, STAIN, and ST1 of the first and second sensing input terminals ST1 and ST2 are turned on. SAIN_R is pulled low.

In the embodiment of the present invention, the reference circuit 230 includes eight transistors MR1 and eight transistors MR2. Transistor MR1 receives a bias voltage equal to the power supply voltage VDD, and transistor MR2 receives a bias voltage equal to a reference ground voltage. The data receiving circuit 220 receives a data signal having 16 bits of DATA [0:15].

In the time interval TA2 after the time interval TA1, the upper enable signal PL_EN and the discharge enable signal DISC are pulled down to a logic low level, and the enable signal Cell_EN is maintained to a logic high level. At the same time, if the first impedance provided by the data receiving circuit 220 is greater than the second impedance provided by the reference circuit 230 (that is, the number of bits of the logic level 0 among the bits DATA [0:15] of the data signal) Greater than 8), the sense amplifier circuit 210 starts the sense amplification action, and according to the magnitude relationship between the first impedance and the second impedance, pulls down the voltage SAIN_R on the second sense input terminal ST2, and simultaneously pulls up the first sense Measure the voltage SAIN on input ST1.

In time interval TA3 after time interval TA2, the upper end enable signal PL_EN is maintained at a logic low level (transistor MP3 is turned on), and the lower end enable signal NL_EN is pulled high to a logic high level, so that transistor MN6 is turned on, and thereby Increasing the rising rate of the voltage SAIN also accelerates the falling rate of the voltage SAIN_R.

In the time interval TA4 after the time interval TA3, the voltage value of the voltage SAIN rises above the threshold voltage of the inverter IV2. Therefore, the voltage SAIN is quickly pulled up to the logic high level in the time interval TA4, and the voltage SAIN_R is quickly pulled to the logic low level in the time interval TA4.

In the time interval TA4, the voltage SAIN_R equal to the logic low level and the voltage SAIN equal to the logic high level are latched in the sense amplifier circuit 210 and pass through the output buffer BUF1 to output a sensing output signal SAOUT.

In FIG. 3B, the action in the time interval TA1 is the same as that described in FIG. 3A. In the time interval TA2 after the time interval TA1, the upper enable signal PL_EN and the discharge enable signal DISC are pulled down to a logic low level, and the enable signal Cell_EN is maintained to a logic high level. At the same time, if the first impedance provided by the data receiving circuit 220 is smaller than the second impedance provided by the reference circuit 230 (that is, the number of bits of the logic level 0 among the bits DATA [0:15] of the data signal) When it is less than or equal to 8), the sense amplifier circuit 210 starts the sense amplification action, and according to the magnitude relationship between the first impedance and the second impedance, pulls up the voltage SAIN_R on the second sensing input terminal ST2, and simultaneously pulls down the first A sensing voltage SAIN on the input terminal ST1.

In time interval TA3 after time interval TA2, the upper end enable signal PL_EN is pulled up to a logic low level (transistor MP3 is turned on), and the lower end enable signal NL_EN is pulled up to a logic high level, so that transistor MN6 is turned on. It also increases the falling rate of the voltage SAIN, and also accelerates the rising rate of the voltage SAIN_R.

In the time interval TA4 after the time interval TA3, the voltage value of the voltage SAIN_R rises above the threshold voltage of the inverter IV1. Therefore, the voltage SAIN_R is quickly pulled up to the logic high level in the time interval TA4. In contrast, the voltage SAIN is quickly pulled to the logic low level in the time interval TA4.

Please refer to FIG. 4 below, which illustrates a schematic diagram of a memory circuit according to an embodiment of the present invention. The memory circuit 400 includes memory cell arrays 431 and 432, a multiplexing circuit 420, and a data bit state detector 410. The data bit state detector 410 is coupled to the multiplexing circuit 420. The data bit state detector 410 receives the data signal DATA to be programmed (written), and determines the logic level states of multiple bits of the data signal DATA to generate a sensing output signal SAOUT. The multiplexer circuit 420 includes multiplexers 421 and 422. The multiplexers 421 and 422 are coupled to the memory cell arrays 431 and 432, respectively. The multiplexing circuit 420 receives the sensing output signal SAOUT, and decides to turn on the memory cell arrays 431 and 432 at the same time according to the sensing output signal SAOUT, or sequentially turns on the memory cell arrays 431 and 432 to target the memory cells in the memory cell array 431. MC10 ~ MC17 and memory cells MC20 ~ MC27 in memory cell array 432 perform programmed operations.

It is worth mentioning that when the data bit state detector 410 determines that the number of bits in the data signal DATA that are at the logic level 0 is greater than 8, it means that there are more data bits to be written and it requires consumption. Go for more battery. Therefore, the multiplexers 421 and 422 are sequentially turned on (one at a time), and the memory cell arrays 431 and 432 are sequentially programmed. In contrast, when the data bit state detector 410 determines that the number of bits in the data signal DATA that are at the logic level 0 is less than or equal to 8, it means that there are fewer data bits to be written and it needs to be consumed. Less power. Therefore, the multiplexers 421 and 422 can be turned on at the same time, and the memory cell arrays 431 and 432 can be programmed at the same time.

In the embodiment of the present invention, the gates of the memory cells MC10 to MC27 are coupled to the word line WL, and a memory cell to be programmed is selected according to the word line signal on the word line WL to perform an access operation.

In summary, the present invention uses a data bit state detector in the form of an analog circuit to generate a first impedance according to the bit states of a plurality of bits of a data signal, and compares the first impedance with a reference impedance. To sense the bit status of multiple bits of the data signal. In this way, it can effectively reduce the complexity of circuit design, reduce the area required for the circuit, reduce the cost required for the memory circuit, and increase its product competitiveness.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

100, 200, 410‧‧‧ Data Bit Status Detector

110, 210‧‧‧sense amplifier circuit

120, 220‧‧‧ data receiving circuit

130, 230‧‧‧Reference circuit

400‧‧‧Memory circuit

431, 432‧‧‧ memory cell array

420‧‧‧Multiplex Circuit

421, 422‧‧‧ Multiplexer

BUF1, BUF2‧‧‧‧ output buffer

Cell_EN‧‧‧ enable signal

DATA‧‧‧ Data Signal

DATA [0:15] ‧‧‧Multiple bits of data signal

DISC‧‧‧Discharge enable signal

GND‧‧‧reference ground

IV1, IV2‧‧‧ Inverter

MC10 ~ MC27‧‧‧Memory Cell

Mcap1, Mcap2‧‧‧Capacitors

MP0 ~ MP3, MN0 ~ MN6, MI0 ~ MI15, MR1 ~ MR2, M_MISC‧‧‧Transistor

NC‧‧‧Floating

NL_EN‧‧‧ Lower end enable signal

PL_EN‧‧‧ Upper end enable signal

SAIN, SAIN_R‧‧‧Voltage

SAOUT‧‧‧sensing output signal

ST1‧‧‧first sensing input

ST2‧‧‧Second sensing input

TA1 ~ TA4‧‧‧Time zone

VDD‧‧‧ supply voltage

WL‧‧‧Character Line

FIG. 1 is a schematic diagram of a data bit state detector according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a data bit state detector according to another embodiment of the present invention. FIG. 3A and FIG. 3B respectively illustrate operation waveform diagrams of different operation states of a data bit state detector according to an embodiment of the present invention. FIG. 4 is a schematic diagram of a memory circuit according to an embodiment of the present invention.

Claims (11)

A data bit state detector includes: a sensing amplifier circuit having a first sensing input terminal and a second sensing input terminal, and sensing and amplifying a first on the first sensing input terminal The difference between the impedance and a second impedance on the second sensing input to generate a sensing output signal; a data receiving circuit receiving a plurality of bits of a data signal, and according to the data signals The bit provides the first impedance between the first sensing input terminal and a reference ground terminal; and a reference circuit receives a plurality of bias voltages, and according to the bias voltages, the second sensing input terminal and The second impedance is provided between the reference ground terminals, wherein the data receiving circuit includes a plurality of first transistors, the first transistors are coupled in parallel with each other between the first sensing input terminal and the reference ground terminal, the The control terminals of the first transistors respectively receive the bits of the data signal. The data bit state detector according to item 1 of the patent application scope, wherein the reference circuit includes a plurality of second transistors, and the second transistors are coupled in parallel with each other at the second sensing input terminal and the Between the reference ground terminals, the control terminals of the second transistors respectively receive the bias voltages, wherein each of the bias voltages is a power supply voltage or a reference ground voltage. The data bit state detector according to item 2 of the scope of the patent application, wherein the number of the second transistors is the same as the number of the first transistors. The data bit state detector according to item 2 of the scope of patent application, wherein the reference circuit further includes: a third transistor, which is coupled in parallel with each of the second transistors, and a control terminal of the third transistor Receive this power supply voltage. The data bit state detector as described in the second item of the patent application scope, wherein the data receiving circuit further includes: a first pull-down switch coupled between the data receiving circuit and the reference ground terminal, according to a consistent performance The signal can be turned on or off. The reference circuit further includes a second pull-down switch coupled between the reference circuit and the reference ground terminal, and can be turned on or off according to the enable signal. A data bit state detector includes: a sensing amplifier circuit having a first sensing input terminal and a second sensing input terminal, and sensing and amplifying a first on the first sensing input terminal The difference between the impedance and a second impedance on the second sensing input to generate a sensing output signal; a data receiving circuit receiving a plurality of bits of a data signal, and according to the data signals The bit provides the first impedance between the first sensing input terminal and a reference ground terminal; a reference circuit receives a plurality of bias voltages, and according to the bias voltages, the second sensing input terminal and the The second impedance is provided between a reference ground terminal; a first capacitor is connected in series between the first sensing input terminal and the reference ground terminal; and a second capacitor is connected in series between the second sensing input terminal and the Refer to ground. A data bit state detector includes: a sensing amplifier circuit having a first sensing input terminal and a second sensing input terminal, and sensing and amplifying a first on the first sensing input terminal The difference between the impedance and a second impedance on the second sensing input to generate a sensing output signal; a data receiving circuit receiving a plurality of bits of a data signal, and according to the data signals The bit provides the first impedance between the first sensing input terminal and a reference ground terminal; a reference circuit receives a plurality of bias voltages, and according to the bias voltages, the second sensing input terminal and the The second impedance is provided between reference ground terminals; a first discharge switch is connected in series between the first sensing input terminal and the reference ground terminal, and is turned on or off according to a discharge enable signal; and a second The discharge switch is connected in series between the second sensing input terminal and the reference ground terminal, and is turned on or off according to the discharge enable signal. A data bit state detector includes: a sensing amplifier circuit having a first sensing input terminal and a second sensing input terminal, and sensing and amplifying a first on the first sensing input terminal The difference between the impedance and a second impedance on the second sensing input to generate a sensing output signal; a data receiving circuit receiving a plurality of bits of a data signal, and according to the data signals The bit provides the first impedance between the first sensing input terminal and a reference ground terminal; a reference circuit receives a plurality of bias voltages, and according to the bias voltages, the second sensing input terminal and the The second impedance is provided between reference ground terminals; a first inverter has an input terminal coupled to the second sensing input terminal, and an output terminal of the first inverter is coupled to the first sensing input terminal And a second inverter having an input terminal coupled to the first sensing input terminal, and an output terminal of the second inverter being coupled to the second sensing input terminal. The data bit state detector according to item 8 of the patent application scope, wherein the sensing amplifier circuit further includes: a first enabling switch controlled by an upper enabling signal to be turned on or off, wherein The first inverter and the second inverter receive a power voltage through the first enabling switch; and a second enabling switch, which is controlled by a lower enabling signal to be turned on or off, wherein the The first inverter and the second inverter receive a reference ground voltage through the second enable switch. A data bit state detector includes: a sensing amplifier circuit having a first sensing input terminal and a second sensing input terminal, and sensing and amplifying a first on the first sensing input terminal The difference between the impedance and a second impedance on the second sensing input to generate a sensing output signal; a data receiving circuit receiving a plurality of bits of a data signal, and according to the data signals The bit provides the first impedance between the first sensing input terminal and a reference ground terminal; a reference circuit receives a plurality of bias voltages, and according to the bias voltages, the second sensing input terminal and the The second impedance is provided between reference ground terminals; a first output buffer whose input terminal is coupled to the first sensing input terminal, an output terminal of the first output buffer generates the sensing output signal; and a first An input terminal of the two output buffers is coupled to the second sensing input terminal, and an output terminal of the second output buffer is floating. A memory circuit includes: a data bit state detector as described in item 1 of the scope of patent application; and a multiplexing circuit coupled to a plurality of memory cell arrays and the data bit state detector for Each of the memory cell arrays is sequentially selected according to the sensing output signal, or the memory cell arrays are selected at the same time to perform a programmed action.