TWI664531B - Controller and control method of flash memory - Google Patents

Abstract

The invention relates to a flash memory controller and control method. The controller includes a scramble circuit and a control circuit. The scramble circuit disturbs at least one input data to generate at least one valid data. The control circuit receives at least one invalid data and a scramble circuit. Generated at least one valid data, the at least one invalid data is not a fixed constant, the control circuit writes the at least one valid data to at least one valid storage area of the flash memory, and writes the at least one invalid data to the flash memory At least one invalid storage area of the body. By writing invalid data that is not a fixed constant to the invalid storage area of the flash memory, the interference of the invalid storage area on the effective storage area can be reduced, so that the reliability of the flash memory and the available storage space can be improved.

Description

Controller and control method of flash memory

The invention relates to a flash memory, in particular to a controller and a control method for controlling the flash memory.

According to the booming electronics, consumer demand for storage media is increasing. Because rewritable non-volatile memory (rewritable non-volatile memory) has the characteristics of rewritable data, fast reading and writing data, non-volatile data, power saving and small size, etc., rewritable non-volatile memory Sex memory is most suitable as a storage medium for electronic products, especially flash memory.

Generally speaking, some flash memory storage areas are damaged at the factory. Although data can still be written to the damaged storage areas, the data read from the damaged storage areas is different from the original data. , It means that the damaged storage areas cannot store data normally. Therefore, when writing data to the flash memory, it is of course necessary to write data to the undamaged storage area of the flash memory and not to write data to the damaged storage area. In the prior art, when writing data to the undamaged storage area of the flash memory, a fixed constant is also written to the damaged storage area, which means that the same value is written to each damaged storage area. These fixed constants Is invalid data, and data written to undamaged storage area is valid data.

Writing data to the flash memory changes the storage state of the storage elements of the flash memory by voltage. This voltage is generated by charging the charging circuit. Depending on the data written, the voltage generated by the charging circuit will be different. different. In the prior art, when a constant is written to the damaged storage area by charging with a charging circuit, the charging process of the charging circuit will interfere with the storage elements in the undamaged storage area adjacent to the damaged storage area due to the coupling effect, and this interference may affect The storage state of the storage elements in the undamaged storage area indicates that the valid data stored in the undamaged storage area may be incorrect, which reduces the reliability of the flash memory. In other words, during the charging period when the fixed constant is repeatedly written to the multiple damaged storage areas, if the charging process corresponding to writing the fixed constant has a large coupling interference to the storage elements of the adjacent undamaged storage area, so When this fixed constant is written multiple times to the complex damaged storage area, the storage voltage of the adjacent undamaged storage area is prone to voltage offset due to multiple large coupling interferences. Data may be changed to non-original stored data.

In addition, if the undamaged storage area is located between two damaged storage areas, since the two damaged storage areas are written with a fixed constant (invalid data), the charging process of the charging circuits of the two damaged storage areas will affect the location of the The storage components in the undamaged storage area between the two, and increase the error rate of the valid data stored in this undamaged storage area. In this case, this undamaged storage area will be listed as a damaged storage area, so that is Will reduce the available storage space in flash memory.

In addition, based on certain requirements, such as the need to facilitate the management of flash memory, the flash memory has some unused storage areas, and this unused storage area does not store valid data. In the prior art, when valid data is written to the flash memory, the valid data is not written to the unused storage area, but the system writes a fixed constant invalid data to the unused storage area. In general, unused storage areas are adjacent to available storage areas. When the available storage area adjacent to the unused storage area is not damaged, valid data is written to this available storage area. However, when charging with a charging circuit and writing a fixed constant (invalid data) to an unused storage area, the charging process of the charging circuit will interfere with the storage elements of the adjacent available storage area, and this interference may affect the available storage area The storage state of the storage element indicates that the valid data stored in the available storage area may be wrong, which reduces the reliability of the flash memory.

Based on the above problems, the present invention provides a flash memory controller and control method, which can reduce the interference of damaged storage areas to undamaged storage areas, and reduce the interference of unused storage areas to undamaged storage areas, which can improve Reliability of flash memory and increase the available storage space of flash memory.

One of the objectives of the present invention is to provide a flash memory controller and control method, which can write invalid data that is not a fixed constant to the damaged storage area, so as to reduce the interference of the damaged storage area to the undamaged storage area. , Which improves the reliability of the flash memory and the available storage space.

One of the objectives of the present invention is to provide a flash memory controller and control method, which can write invalid data that is not a fixed constant to the unused storage area, so as to reduce the unused storage area to the undamaged storage area. This can increase the reliability of flash memory.

The invention discloses a flash memory controller, which includes a scramble circuit and a control circuit. The disturbance circuit receives at least one input data and disturbs the input data to generate at least one valid data; the control circuit receives at least one invalid data and the at least one valid data generated by the disturbance circuit, the at least one invalid data is not a fixed constant, the control circuit Write the at least one valid data to at least one valid storage area of the flash memory, and write the at least one invalid data to at least one invalid storage area of the flash memory.

The invention discloses a flash memory control method, which includes receiving at least one input data; disturbing the at least one input data to generate at least one valid data; providing at least one invalid data, the at least one invalid data is not a fixed constant; Write the at least one valid data to at least one valid storage area of the flash memory; and write the at least one invalid data to at least one invalid storage area of the flash memory.

In the specification and subsequent patent applications, certain terms are used to refer to specific elements. It should be understood by those having ordinary knowledge in the technical field of the present invention that hardware manufacturers may use different terms to refer to the same component. The scope of this specification and subsequent patent applications does not use the difference in names as a way to distinguish components, but rather uses the difference in functions of components as a criterion for distinguishing components. "Inclusion" mentioned throughout the specification and the scope of subsequent patent applications is an open-ended term and should be interpreted as "including but not limited to." In addition, the term "coupling" includes any direct and indirect means of electrical connection. Therefore, if a first device is coupled to a second device is described herein, it means that the first device can be electrically connected directly to the second device, or can be indirectly electrically connected to the second device through other devices or other connection means.

In order to make the reviewing committee members have a better understanding and understanding of the features of the present invention and the effects achieved, I would like to provide detailed descriptions with examples and cooperation, as follows:

Please refer to the first figure, which is a block diagram of an embodiment of a flash memory controller according to the present invention. As shown in the figure, the present invention discloses a controller 20 coupled to a flash memory 10 to control the flash memory 10. The controller 20 is further coupled to a host 5, and the controller 20 can receive the transmission from the host 5. The data can be written into the flash memory 10 to store the data transmitted by the host 5 in the flash memory 10, and the controller 20 can also read the data from the flash memory 10 and transfer the read data. Information to the host 5. The host 5 described above is any electronic device that can cooperate with the controller 20 to store data in the flash memory 10, such as a computer system, a mobile phone, a digital camera, an audio player, or a video player. The data transmitted from the host 5 to the controller 20 and stored in the flash memory 10 is input data.

When the controller 20 of the present invention wants to store at least one input data to the flash memory 10, the controller 20 disturbs the at least one input data to generate at least one valid data, and writes the at least one valid data to the flash memory 10 Available at least one undamaged storage area, and write at least one invalid data to at least one damaged storage area and at least one unused storage area of the flash memory 10 respectively, the invalid data is not a fixed constant, non-fixed constant indicates The invalid data written to each damaged storage area is different from each unused storage area. Since the valid data is stored in the available undamaged storage area, but not in the damaged storage area and the unused storage area, the available undamaged storage area is a valid storage area, and the damaged storage area and the unused storage area are Invalid storage area. Because the controller 20 writes valid data to the valid storage area, the controller 20 also writes invalid data with non-constant constants to the invalid storage area. This can reduce the coupling interference (capacitive coupling) of the invalid storage area to the adjacent valid storage area. Effect or signal conduction interference), thereby improving the reliability of the flash memory 10 and the available storage space. The structure and operation of the controller 20 are described in detail below.

As shown in the first figure, the controller 20 of the present invention includes a host interface 21, a buffer 22, a control circuit 23, a selection circuit 24, a scramble circuit 25, and a flash memory interface 26. The host interface 21 is coupled to the host 5, and the host 5 sends input data and commands to the host interface 21. The host 5 transmits input data to the controller 20 through the host interface 21. The purpose is to store the input data in the flash memory 10 through the controller 20. The host interface 21 is further coupled to the buffer 22 and the control circuit 23. The host interface 21 transmits commands to the control circuit 23. In this embodiment, the command may be a write command or a read command. The control circuit 23 can know that the host 5 wants to write input data to the flash memory 10 or read data from the flash memory 10 according to the command. In addition, the host interface 21 sends input data to the buffer 22, and the buffer 22 is used to buffer the input data. The buffer 22 is further coupled to the selection circuit 24 and transmits input data to the selection circuit 24. It can be known from the above that the host interface 21 transmits a command from the host 5 to the control circuit 23 and provides input data transmitted by the host 5 to the selection circuit 24. In addition, the selection circuit 24 further receives a reference material, the selection circuit 24 is further coupled to the control circuit 23, and the control circuit 23 controls the selection circuit 24 to select the reference material or the input material of the host 5 and output the reference material or the input material. In one embodiment of the present invention, the selection circuit 24 may be a multiplexer, and the reference data may be fixed constant data. For example, a reference data may be FF or AA (in hexadecimal terms), which means that Each byte (Byte) of the reference data is a constant data with a fixed F or A. In other words, the fixed constant in the embodiment may indicate that the value of each byte in each piece of data is the same.

Referring again to the first figure, the scramble circuit 25 is coupled to the selection circuit 24, and receives the input data and reference data output by the selection circuit 24, and disturbs the input data to generate valid data, and can further disturb the reference data to generate invalid data. The reference data is invalid data with non-fixed constants after being scrambled. For example, the non-fixed constants can be F1 or A2; similarly, each input data is scrambled by the scramble circuit 25 to become valid data with different values (non-fixed constants) In this way, the mutual coupling interference of each valid data during the charging period written in the flash memory 10 can be reduced. In one embodiment of the present invention, the scramble circuit 25 has at least one preset scramble parameter. The scramble circuit 25 uses the scramble parameter to perform logical operations on the input data to scramble the input data to generate valid data. In addition, the scramble circuit 25 may have a complex scramble parameter, so that the value of the invalid data other than the fixed constant is different from the value of the valid data, or is completely different from the value of the valid data. It can be known from the above description that the buffer 22 buffers the input data so that the input data can be provided to the disturbance circuit 25 through the selection circuit 24.

In one embodiment of the present invention, the above-mentioned logical operation may be a mutually exclusive (XOR) operation or other algorithms, but it is not limited that the scramble circuit 25 can only perform mutually exclusive operations to disturb the input data to generate valid data. In another embodiment of the present invention, the scramble circuit 25 may be a random number generating circuit. In addition, the scramble circuit 25 scrambles the reference data in the manner described above to generate invalid data. In one embodiment of the present invention, the scrambling circuit 25 may have a plurality of scrambling parameters, and the scrambling parameters are not the same. Therefore, the scrambling circuit 25 may use different scrambling parameters to scramble the reference data to generate invalid data that is not a fixed constant. The disturbance circuit 25 is further coupled to the control circuit 23 and transmits valid data and invalid data to the control circuit 23.

Referring again to the first figure, the flash memory interface 26 is coupled between the control circuit 23 and the flash memory 10. The control circuit 23 receives valid data and invalid data generated by the disturbance circuit 25, and transmits the valid data and invalid data to the flash memory interface 26 to write valid data to the valid storage area and write invalid data to the invalid storage area. . When the controller 20 stores the input data in the flash memory 10, the control circuit 23 writes data into the storage area from an address of the flash memory 10, and this address can be set in the controller 20 in advance. The control circuit 23 writes valid data to the valid storage area. If the storage area adjacent to the valid storage area is an invalid storage area (damaged storage area or unused storage area), the control circuit 23 writes non-fixed constant invalid data to invalid. The storage area can reduce the coupling interference of the invalid storage area to the adjacent effective storage area, thereby improving the reliability of the flash memory and the available storage space.

In one embodiment of the present invention, the flash memory 10 may be detected in advance to know the status of each storage area of the flash memory 10, and to know which storage areas are damaged storage areas, the controller 20 may record in advance The location information of the damaged storage area and the location information of the unused storage area, so the control circuit 23 can know the location information of the invalid storage area in advance, and can know in advance whether the valid storage area is adjacent to the invalid storage area. The control circuit 23 can control the selection circuit 24 to select reference data according to the position information of the invalid storage area, and output the reference data to the disturbance circuit 25 to generate invalid data and provide it to the control circuit 23 to write invalid data (non-constant constant) To invalid storage. Similarly, the controller 20 can record the position information of the effective storage area in advance, and the control circuit 23 can select the input data according to the position information of the effective storage area, and output the input data to the disturbance circuit 25 to generate effective data. It is provided to the control circuit 23 to write valid data to the valid storage area.

In this embodiment, the controller 20 may further include a storage unit 27 that can store the position information of the invalid storage area, the position information of the valid storage area, and reference data. The storage unit 27 is coupled to the selection circuit 24 to provide reference data to the selection circuit 24. In addition, the storage unit 27 is coupled to the control circuit 23 to provide the position information of the invalid storage area or the position information of the effective storage area to the control circuit 23.

Referring again to the first figure, the controller 20 may further include a data screening unit 28 and a descrambling circuit 29. The data screening unit 28 is coupled to the control circuit 23 and the descrambling circuit 29. The descrambling circuit 29 is further coupled to the buffer 22. When the control circuit 23 receives the read command from the host 5, the control circuit 23 reads a data sequence from the flash memory 10 through the flash memory interface 26. Since the flash memory 10 includes a valid storage area and an invalid storage area, the data sequence contains valid data and invalid data. The valid data is data that the user wants to store, and the invalid data is not data that the user wants to store. The control circuit 23 transmits the data sequence to the data screening unit 28. The data screening unit 28 receives the data sequence and filters out valid data from the data sequence to transmit the valid data to the descrambling circuit 29. In one embodiment of the present invention, the data screening unit 28 filters out invalid data from the data sequence according to the location information of the invalid storage area, and then screens out valid data. The data screening unit 28 can be further coupled to the storage unit 27 to obtain the location information of the invalid storage area. In addition, the data filtering unit 28 may filter valid data from the data sequence according to the location information of the valid storage area. The data screening unit 28 can learn the location information of the effective storage area from the storage unit 27. The descrambling circuit 29 receives valid data output by the data screening unit 28 and descrambles the valid data to generate an output data. In an embodiment of the present invention, the descrambling circuit 29 has a descrambling parameter. The descrambling parameter is the same as the descrambling parameter of the scramble circuit 25 to perform operations on valid data and generate output data by descrambling valid data. The data can be the same as the input data. The descrambling circuit 29 transmits output data to the buffer 22, and the buffer 22 buffers the output data and provides the output data to the host interface 21 to transmit the output data to the host 5.

Please refer to the second figure, which is a schematic diagram of a flash memory according to an embodiment of the present invention. As shown, the flash memory 10 having at least one storage block (Block) 101, the storage block 101 having a plurality of stored pages _{(Page) P 1 ~ P N} . Each of the storage pages P ₁ to P _N has a plurality of storage columns, as shown in the third figure. The first storage page P ₁ has a plurality of storage columns C ₁₁ to C _1M . In one embodiment of the present invention, the minimum unit for writing data to the flash memory 10 by the control circuit 23 is a storage column, but it is not limited thereto. In addition, the storage space of a storage column has at least one byte. The control circuit 23 writes data to the flash memory 10, substantially, the control circuit 23 a write data sequentially from the start address to the flash memory 10, for example of the control page from the first storage _circuit 23 of P A storage column C ₁₁ starts writing data to the flash memory 10 sequentially. In one embodiment of the present invention, each storage column is a storage area. If the status of the storage bar is damaged or unused, it means that the storage bar is an invalid storage area; if the status of the storage bar is not damaged and available, it means that the storage bar is a valid storage area.

The following example illustrates the rules for the controller 20 to write data to the flash memory 10. Please refer to FIG. 4A, which is a schematic diagram of an embodiment in which the storage page of the flash memory 10 of the present invention has not been written with data. As shown in the figure, the first storage page P ₁ has five storage columns C ₁₁ to C ₁₅ , of which the third storage column C ₁₃ and the fifth storage column C ₁₅ are damaged and become damaged storage areas (invalid storage areas), and the rest The storage columns C ₁₁ , C ₁₂ and C _{14 are} not damaged but are undamaged storage areas (effective storage areas). When the first storage controller 20 page P C of the first storage column ₁₁₁ beginning to write valid data to the first storage page _{P. 1,} since the C ₁₁ column is not the first storage storage area to be invalid, the control circuit 23 controls the The selection circuit 24 selects the input data of the host 5, and the selection circuit 24 outputs the input data to the scramble circuit 25 to generate valid data. As shown in the fourth diagram B, the control circuit 23 writes valid data into the first storage column C ₁₁ . Subsequently, since the second storage column C ₁₂ is also a valid storage area, as shown in the fourth diagram B, the control circuit 23 continues to write the next valid data to the second storage column C ₁₂ . Then, since the third storage column C ₁₃ is a damaged storage area (invalid storage area), the control circuit 23 controls the selection circuit 24 to select reference data, and outputs the reference data to the disturbance circuit 25 to generate invalid data (non-constant constants). As shown in FIG. 4B, the control circuit 23 writes invalid data to the third storage column C ₁₃ . Then, because the fourth storage column C ₁₄ is an effective storage area, the control circuit 23 controls the selection circuit 24 to output the input data of the host 5 to the disturbance circuit 25 to generate valid data. As shown in the fourth diagram B, the control circuit 23 writes Enter valid data into the fourth storage column C ₁₄ . Since the fifth storage column C ₁₅ is a damaged storage area (invalid storage area), the control circuit 23 controls the selection circuit 24 to output reference data to the disturbance circuit 25 to generate invalid data. As shown in the fourth diagram B, the control circuit 23 writes Enter invalid data into the fifth storage column C ₁₅ .

It can be known from the above description that the control circuit 23 controls the selection circuit 24 to select input data or reference data according to the state of the storage area, which indicates that the selection circuit 24 outputs the input data or reference data to the disturbance circuit 25 according to the state of the storage area to generate valid data Or the invalid data, so that the control circuit 23 can store the valid data in the valid storage area according to the state of the storage area, and store the invalid data in the invalid storage area adjacent to the valid storage area. Since the invalid data generated by the disturbance circuit 25 is not a fixed constant, the invalid data written in the third storage column C ₁₃ is different from the invalid data written in the fifth storage column C ₁₅ . In this way, the coupling of the charging circuits corresponding to the third storage column C ₁₃ and the fifth storage column C ₁₅ to the adjacent first storage column C ₁₁ , the second storage column C ₁₂ and the fourth storage column C ₁₄ can be reduced. Interference, thereby improving the reliability of the first storage column C ₁₁ , the second storage column C ₁₂ and the fourth storage column C ₁₄ in the storage state.

For example, the voltage levels corresponding to writing FF and 00 data in hexadecimal to flash memory 10 are the lowest voltage level and the highest voltage level, respectively, and the effective storage area (such as the first storage column C ₁₁ ) The original valid data is AA. In the prior art, during the charging process of writing invalid data with a fixed value multiple times into a plurality of invalid storage areas (such as the third storage column C ₁₃ and the fifth storage column C ₁₅ ), if the invalid data is FF, the fixed value is invalid. The voltage corresponding to the data FF will continuously lower the voltage of the adjacent effective storage area; if the invalid data is 00, the voltage corresponding to the fixed value 00 of the invalid data will continue to increase the voltage of the adjacent effective storage area. Since the controller 20 of the present invention writes invalid data with different values to each invalid storage area, the degree of coupling interference of the charging corresponding to writing invalid data to the invalid storage area on the storage elements adjacent to the valid storage area can be reduced. Similarly, when different valid data is written in each valid storage area, the coupling interference between the valid storage areas can also be reduced, and so on, the coupling interference between each storage page P ₁ -P _N can also be obtained. improve.

In addition, since the interference of the third storage column C ₁₃ and the fifth storage column C ₁₅ on the fourth storage column C ₁₄ is reduced, the error rate of the data stored in the fourth storage column C ₁₄ can be reduced, so the fourth storage column C ₁₄ can be used to store valid data. It means that the flash memory 10 is controlled by using the controller 20 and the control method of the present invention. The undamaged storage area (C ₁₄ ) located between the two damaged storage areas (C ₁₃ , C ₁₅ ) can be used as an effective storage area for storage. The effective data is different from the conventional technology. The undamaged area located between two damaged storage areas is regarded as an invalid storage area without valid data. Therefore, the controller 20 and the control method of the present invention are compared with the conventional technology. The controller 20 and the control method can increase the available storage space of the flash memory 10.

Please refer to FIG. 5A, which is a schematic diagram of another embodiment in which the storage page of the flash memory 10 of the present invention has not been written with data. As shown in the figure, the second storage page P ₂ has five storage columns C ₂₁ to C ₂₅ , and the third storage page P ₃ also has five storage columns C ₃₁ to C ₃₅ , where the storage columns C ₂₂ , C ₂₄ , C ₃₂ , C ₃₃ , and C ₃₄ are damaged and are damaged storage areas (invalid storage areas), and storage columns C ₂₁ , C ₂₃ , C ₃₁ , and C _{35 are} not damaged but are undamaged storage areas (effective storage areas). In this embodiment, the third storage field to store only the page P ₃ C _31, C ₃₅ is not damaged storage areas which store the page P ₃ represents a third active only two data storage areas can be stored efficiently. In order to facilitate the management of the storage space of the flash memory 10, the administrator will set the effective storage capacity of two adjacent storage pages to be the same. In this embodiment, the fifth storage column C ₂₅ of the second storage page P _{2 is} preset as an unused storage area (invalid storage area) without storing valid data, so that the adjacent second storage page P ₂ and The third storage page P ₃ has the same number of effective storage areas (2 effective storage areas), that is, the effective storage capacity of the second storage page P _{2 is} the same as the effective storage capacity of the third storage page P ₃ . As shown in the fifth figure B, since the storage columns C ₂₂ , C ₂₄ , C ₂₅ , C ₃₂ , C ₃₃ , and C ₃₄ are invalid storage areas without storing valid data, the control circuit 23 writes invalid data to the storages. Columns _C22 , _C24 , _C25 , _C32 , _C33 , _C34 , and write valid data to the storage columns _C21 , _C23 , _C31 , _C35 .

Referring again to the first figure, in an embodiment of the present invention, the controller 20 may store at least one invalid data in advance, and the at least one invalid data is not a fixed constant, and is provided to the control circuit 23, for example, the invalid data is stored. In the storage unit 27, the controller 20 may not need the selection circuit 24 to select the reference data, the control circuit 23 may write the invalid data provided by the storage unit 27 to the invalid storage area, and the buffer 22 may directly provide the at least one input data to Disruption circuit 25.

In summary, the flash memory controller and control method of the present invention provide at least one invalid data. The at least one invalid data is not a fixed constant. When writing at least one input data transmitted from the host to the flash memory, During operation, the at least one input data is disturbed to generate at least one valid data, and the at least one valid data is written to at least one valid storage area of the flash memory, and the at least one invalid data is written to a vicinity of the valid storage area. At least one invalid storage area. This can reduce the interference of the invalid storage area to the effective storage area, and can improve the reliability of the flash memory and the available storage space.

As can be seen from the above, the present invention has indeed reached a groundbreaking structure, with improved content of the invention, and at the same time, it can achieve industrial applicability and progress. When it complies with the provisions of the Patent Law, it will file an application for an invention patent in accordance with the law. The examiner of the Office granted the legal patent right.

5‧‧‧host

10‧‧‧Flash memory

101‧‧‧Storage block

20‧‧‧ Controller

21‧‧‧Host Interface

22‧‧‧Buffer

23‧‧‧Control circuit

24‧‧‧Selection circuit

25‧‧‧ Disturb Circuit

26‧‧‧Flash Memory Interface

27‧‧‧Storage unit

28‧‧‧ Data Screening Unit

29‧‧‧Descramble Circuit

P ₁ ~ P _N ‧‧‧Save page

C ₁₁ ~ C _1M ‧‧‧Storage column

C ₂₁ ~ C ₂₅ ‧‧‧Storage column

C ₃₁ ~ C ₃₅ ‧‧‧Storage column

The first diagram is a block diagram of an embodiment of a flash memory controller of the present invention; the second diagram is a schematic diagram of an embodiment of a flash memory of the present invention; the third diagram is a flash memory of the present invention A schematic diagram of an embodiment of a storage page of a bank; FIG. 4A is a schematic diagram of an embodiment of a storage page of the flash memory of the present invention that has not yet been written with data; FIG. 4B is a storage of a fourth A diagram Schematic diagram of data being written into a page; FIG. 5A is a schematic diagram of another embodiment of a flash memory storage page that has not yet been written with data; and FIG. 5B is a storing page of a fifth A Schematic diagram of writing data.

Claims (12)

A flash memory controller for controlling a flash memory. The controller includes: a scramble circuit that receives at least one input data and disturbs the at least one input data to generate at least one valid data; and a control circuit Is coupled to the disturbance circuit, the control circuit receives at least one invalid data and the at least one valid data generated by the disturbance circuit, the at least one invalid data is not a fixed constant, and writes the at least one valid data to the fast At least one valid storage area of the flash memory, and writing the at least one invalid data to the at least one invalid storage area of the flash memory. The flash memory controller described in item 1 of the patent application scope further includes: a data screening unit coupled to the control circuit to receive at least one read by the control circuit from the flash memory Data sequence, the at least one data sequence includes the at least one valid data and the at least one invalid data, the data filtering unit filters out the at least one invalid data from the at least one data sequence according to the location information of the at least one invalid storage area, and Screen out the at least one valid data; and a descrambling circuit coupled to the data screening unit to receive the at least one valid data output by the data screening unit and descramble the at least one valid data to generate at least one output data. According to the flash memory controller described in item 2 of the scope of the patent application, the controller further includes a storage unit coupled to the data screening unit and the control circuit, and the storage unit stores position information of the at least one invalid storage area. According to the flash memory controller described in item 1 of the patent application scope, it further includes a selection circuit that receives the at least one input data and at least one reference data, the selection circuit is respectively coupled to the control circuit and the scramble circuit. , The control circuit controls the selection circuit to select the at least one input data or the at least one reference data according to the position information of the at least one valid storage area or the at least one invalid storage area, and outputs the at least one input data or the at least one reference Data, the scramble circuit receives the at least one reference data output by the selection circuit, and disturbs the at least one reference data to generate the at least one invalid data. According to the flash memory controller described in item 4 of the scope of the patent application, the controller further includes a storage unit coupled to the selection circuit and the control circuit. The storage unit stores position information of the at least one invalid storage area, the storage unit, The location information of the at least one valid storage area and the at least one reference data. According to the flash memory controller described in item 1 of the patent application scope, the controller further includes a storage unit coupled to the control circuit, and the storage unit stores the at least one invalid data. The flash memory controller according to item 1 of the scope of the patent application, wherein the at least one invalid storage area includes at least one damaged storage area or / and at least one unused storage area of the flash memory. The flash memory controller according to item 1 of the scope of patent application, further comprising: a host interface coupled to a host, the host transmitting the at least one input data to the host interface; a buffer, coupled to The host interface, the host interface transmitting the at least one input data to the buffer, the buffer providing the at least one input data to the scramble circuit; and a flash memory interface coupled to the control circuit and the flash Between memories. A flash memory control method for controlling a flash memory. The method includes: receiving at least one input data; disturbing the at least one input data to generate at least one valid data; providing at least one invalid data, the at least one invalid The data is not a fixed constant; writing the at least one valid data into at least one valid storage area of the flash memory; and writing the at least one invalid data into at least one invalid storage area of the flash memory. According to the flash memory control method described in item 9 of the scope of patent application, the method further includes: providing at least one reference material; and disturbing the at least one reference material to generate the at least one invalid material. The flash memory control method according to item 9 of the scope of patent application, further comprising: reading at least one data sequence from the flash memory, the at least one data sequence including the at least one valid data and the at least one invalid Data; filtering out the at least one invalid data from the at least one data sequence according to the location information of the at least one invalid storage area, and filtering out the at least one valid data; and descrambling the at least one valid data to generate at least one output data . The flash memory control method according to item 9 of the scope of the patent application, wherein the at least one invalid storage area includes at least one damaged storage area or / and at least one unused storage area of the flash memory.