TWI662555B - Data reading device and data reading method for design-for-testing - Google Patents

Abstract

A data reading device and a data reading method for testability design. The data reading device includes a buffer and a data serialization circuit. The data serialization circuit receives a clock positive edge trigger signal, a clock negative edge trigger signal, a trigger mask signal, and data to be measured. The data serialization circuit masks one of the clock positive edge trigger signal and the clock negative edge trigger signal according to the trigger mask signal, and uses the clock positive edge trigger signal or the clock negative edge trigger signal to be uncovered to The data to be tested is provided to the output of the data serialization circuit as an output signal of the data reading device. With this, the data valid window of the data to be measured can be enlarged.

Description

Data reading device and method for testability design

The invention relates to a design for testing (DFT) technology, and in particular, to a data reading device and a data reading method for testability design.

In Design for Testing (DFT) technology, in order to facilitate the testing or verification of the function of a chip or a circuit, a related test circuit is usually implanted during the design phase of the circuit so that it can be performed after the circuit design is completed. test.

When the test machine uses signal measurement on the chip or circuit, the signal transmission speed of each pin in the test circuit is different due to the pin impedance, trace length, and logic gate response time. In the case of delayed enabling / disabling, this phenomenon can be called data skew. In the case of technological progress based on semiconductor processes and communication specifications that gradually increase its transmission capacity, the signal transmission speed of the circuit will be expected to be faster and faster, but it will also lead to effective data availability. The data valid window will also get smaller and smaller. In addition, when the pin is close to the power line, the data in this pin may be skewed due to the power transmission of the power line.

As a result, it is becoming increasingly difficult to accurately obtain the signal to be measured from the data valid window at high speeds. Therefore, how to more easily obtain and test the signal under test is one of the problems that has existed in the signal testing field for many years.

The invention provides a data reading device and a data reading method for testability design, which are used to increase the effective window of data available in the signal to be tested.

The data reading device for testability design according to the embodiment of the present invention includes a buffer and a data serialization circuit. The buffer is used to temporarily store the data to be tested. The data serialization circuit is coupled to the buffer. The data serialization circuit receives a clock positive edge trigger signal, a clock negative edge trigger signal, a trigger mask signal, and data to be measured. The data serialization circuit masks one of the clock positive edge trigger signal and the clock negative edge trigger signal according to the trigger mask signal, and according to the unmasked clock positive edge trigger signal or clock negative edge trigger signal A part of the data to be tested is provided to the output end of the data serialization circuit as an output signal of the data reading device.

The data reading method for testability design according to the embodiment of the present invention is applicable to a data reading device including a data serialization circuit. The data reading method includes the following steps: obtaining a clock positive edge trigger signal, a clock negative edge trigger signal, a trigger mask signal, and the data to be measured; and shielding the data according to the trigger mask signal. Said one of the clock positive edge trigger signal and the clock negative edge trigger signal, and according to the unmasked clock positive edge trigger signal or clock negative edge trigger signal to provide part of the data to be tested to the data The output end of the serialization circuit is used as an output signal of the data reading device.

Based on the above, the data reading device and data reading method according to the embodiments of the present invention can use an additional trigger mask signal to block or mask the clock positive edge trigger signal and the clock negative edge when reading the signal to be measured. One of the trigger signals, and another trigger signal that is not masked is used to obtain the corresponding part of the data to be tested. As a result, the output time of the data to be measured will increase from half of a clock cycle of the original clock to a clock cycle. In this way, the available data valid window can be increased without adjusting the internal data type in the chip using this data reading device, without changing the clock or related configuration, and making the external test machine easier. To judge the correctness of the data to be tested obtained by the data reading device.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

100‧‧‧Data reading circuit

110‧‧‧Buffer

112‧‧‧ FIFO buffer

114‧‧‧ Parallel to Serial Buffer

120‧‧‧Data serialization circuit

130‧‧‧ Off-chip driver

140‧‧‧ cushion

RWD‧‧‧Data to be tested

D + ‧‧‧Positive data to be tested

D-‧‧‧ Negative margins to be tested data

D <3: 0, D0 ~ D3‧‧‧ Data

CLKOUT_T‧‧‧ Clock positive edge trigger signal

CLKOUT_C‧‧‧ Clock negative edge trigger signal

DMASK‧‧‧Trigger mask signal

tCK‧‧‧clock cycle

DVW1, DVW2, DVW3‧‧‧Data valid window

t1‧‧‧time

FIG. 1 is a block diagram of a data reading device according to an embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining the clock signal DQS, the clock positive edge trigger signal CLKOUT_T, the clock negative edge trigger signal CLKOUT_C, and the data to be measured D0 ~ D3 and D <3: 0.

FIG. 3 illustrates a clock signal DQS, a clock positive edge trigger signal CLKOUT_T, a clock negative edge trigger signal CLKOUT_C, a trigger mask signal DMASK, and data to be measured D0 ~ D3 and D <3: 0 according to an embodiment of the present invention. > Wave pattern.

FIG. 4 is a block diagram of the data serialization circuit 120 in FIG. 1.

FIG. 5 is a flowchart of a data reading method for testability design according to an embodiment of the present invention.

As shown in FIG. 1, the data reading circuit 100 can be applied to a dynamic data random access memory (DRAM) device, and particularly to a low power dynamic random access memory device. In order to reduce power consumption, the low power dynamic random access memory device removes a delay lock loop (DLL) from the original DRAM architecture, thereby reducing the stability of data transmission in the DRAM device. The data reading circuit 100 of this embodiment may be disposed in a chip, and a test machine located outside the chip may use the data reading circuit 100 to read the relevant signals or data to be measured.

The data reading circuit 100 in FIG. 1 mainly includes a buffer 110 and a data serialization circuit 120. The buffer 110 is configured to temporarily store the data to be tested RWD obtained from the memory array. In detail, the memory cell array can be located according to the memory address, and the data corresponding to the memory address in the memory cell array can be read out through the read-write data line to become the RWD, and the data to be tested The RWD is temporarily stored in the buffer 110.

The buffer 110 in this embodiment includes a first-in-first-out (FIFO) buffer 112 and a parallel-to-serial buffer 114. The first-in-first-out buffer 112 provides the data obtained earlier to its output end, and the data obtained later will be output after all the previous data has been output for subsequent components. The parallel-to-serial buffer 114 is coupled to the first-in-first-out buffer 112 and converts the data to be tested transmitted in parallel to the data to be tested transmitted in serial. Those applying this embodiment can adjust the structure of the buffer 110 according to the data format inside the DRAM device and the data format output externally by the DRAM device.

The data serialization circuit 120 receives a clock positive edge trigger signal CLKOUT_T, a clock negative edge trigger signal CLKOUT_C, a trigger mask signal DMASK, and data under test obtained from the buffer 110. In this embodiment, the data to be tested includes a positive edge data D + corresponding to the clock positive edge trigger signal CLKOUT_T and a negative edge data D- corresponding to the clock negative edge trigger signal CLKOUT_C. The positive data to be measured D + and the negative data to be measured D- are both part of the data to be tested. In other words, the data serialization circuit 120 uses the enabled clock positive edge trigger signal CLKOUT_T to output the positive edge data D + to the pad 140, and the data serialization circuit 120 also uses the enabled clock negative edge trigger signal. CLKOUT_C and output the negative edge data D- to the pad 140.

The data serialization circuit 120 masks one of the clock positive edge trigger signal CLKOUT_T and the clock negative edge trigger signal CLKOUT_C according to the trigger mask signal DMASK, and according to the clock positive edge trigger signal CLKOUT_T or clock negative Edge trigger signal CLKOUT_C provides part of the data to be tested to the data sequence The output terminal of the conversion circuit 120 is used as an output signal of the data reading device 100. The detailed braking manner of the data serialization circuit 120 will be described in detail in the following embodiments.

The data reading circuit 100 in FIG. 1 further includes an off-chip driver (OCD) 130 and a pad 140. The data reading circuit 100 utilizes the off-chip driver 130 and the pad 140 to output the output signal of the data reading device 100 through the pad 140 to a device electrically coupled to the pad 140, such as a test machine. The off-chip driver 130 is coupled to the data serialization circuit 120 to receive an output signal of the data reading device 100. The pad 140 is electrically connected to the off-chip driver 130. The off-chip driver 130 provides part of the data to be tested to the pad 140 according to an output signal provided by an output terminal of the data serialization circuit 120.

See Figure 2. When the clock signal DQS transitions from the negative edge to the positive edge, the clock positive edge trigger signal CLKOUT_T will be enabled. When the clock signal DQS transitions from the positive edge to the negative edge, the negative clock edge will trigger. The signal CLKOUT_C will be enabled. It is assumed here that the data serialization circuit 120 of FIG. 1 does not use a trigger mask signal to implement the embodiment of the present invention. In order to output the data to be tested as soon as possible, the data serialization circuit 120 usually transmits a piece of data when the clock positive edge trigger signal CLKOUT_T is enabled (for example, the positive edge data to be tested D + is transmitted, and The data valid window DVW1 corresponds to the positive edge data to be measured D +), and another data is transmitted when the clock negative edge trigger signal CLKOUT_C is enabled (for example, the negative edge data to be measured D- is transmitted, and the data D <3: 0> The data valid window DVW2 corresponds to the negative edge data D-). In this embodiment, the data to be tested transmitted after the positive edge trigger signal CLKOUT_T is enabled is called positive data to be tested D +; the data to be tested transmitted after the negative edge trigger signal CLKOUT_C is enabled This is called negative data D-. In this embodiment, the output time of the positive edge data to be measured D + or the negative edge data to be measured D- is half of a complete clock cycle tCK in the clock signal QDS. For the convenience of explanation, the part of data D <3: 0> that corresponds to the data D + for the positive edge is [0,1,0,1], and the part of data D <3: 0> that corresponds to the data D- for the negative edge is D- It is [1,0,1,0].

However, the transmission rate of protocols used by low-power dynamic random access memory devices has gradually increased. For example, from the previous first-generation double data rate synchronous dynamic random access memory (DDR SDRAM), it has developed to the fourth The generation of double data rate synchronous dynamic random access memory (DDR4 SDRAM) has caused the data D <3: 0> to change faster. When the external test machine uses the data reading circuit 100 to obtain the data to be tested in the chip, the clock signal DQS and its rate located in the chip may not be known, which may result in the failure to find the data D <3: 0>. Data valid window. For example, in Figure 2, the data valid window DVW1 corresponding to the positive edge data to be tested D + and the data valid window DVW2 corresponding to the negative data to be tested D- will be difficult to be known by the testing machine. In other words, when the speed of data transmission is faster, the tester cannot find the proper timing from the change of data D <3: 0> to find the time point for signal acquisition (also known as strobe) (Dot), that is, the desired information cannot be effectively retrieved in the data valid window of the data D <3: 0>.

Therefore, in this embodiment, additional pins and related circuits are added to the data serialization circuit 120 in FIG. 1 to use the trigger mask signal DMASK to mask one of the clock positive edge trigger signal CLKOUT_T and clock negative edge trigger signal CLKOUT_C. Thereby increasing the data valid window of some of the data to be tested. Test machine can pass The trigger mask signal DMASK is adjusted to selectively mask one of the clock positive edge trigger signal CLKOUT_T and the clock negative edge trigger signal CLKOUT_C. This is described below with reference to FIG. 3.

The embodiment of FIG. 3 uses the enabled (ie, logic “1”) trigger mask signal DMASK to select to mask the negative clock trigger signal CLKOUT_C and not to mask the positive clock trigger signal CLKOUT_T to serialize the data. The circuit 120 normally outputs the positive edge data D + when the positive clock edge trigger signal CLKOUT_T is enabled, and does not output the negative edge data D- due to the enable of the negative clock edge trigger signal CLKOUT_C. In this way, the data valid window DVW3 of the positive edge data D + to be measured will increase the time t1 than the data valid window DVW1 in FIG. 2. The output time of the positive edge data D + will increase from half of a complete clock period tCK in the clock signal QDS to a complete clock period tCK, which will increase the data valid window DVW3 of the positive edge data D +. .

The embodiment in FIG. 3 has masked the clock negative edge trigger signal CLKOUT_C, so that only part of the data to be tested (ie, the positive edge to be tested data D +) is output to the pad 140 in FIG. Therefore, in order to obtain complete data under test, the external test machine needs to adjust the trigger mask signal DMASK from enabled (that is, logic "1") to disabled to allow the clock positive edge trigger signal CLKOUT_T It is masked and cannot output the positive edge data to be measured D +, so the negative edge data to be measured D- corresponding to the clock negative edge trigger signal CLKOUT_C is output to the pad 140 in FIG. 1. In other words, the external test machine can obtain the positive edge data to be measured D + and the negative edge data to be measured D- by adjusting the trigger mask signal DMASK in a longer time.

This embodiment uses FIG. 4 as an example to illustrate the implementation circuit of the data serialization circuit 120. Those applying this embodiment should be able to use other circuits in accordance with the spirit of the embodiment of the present invention to implement the data serialization circuit 120 according to their needs, and should not be limited to the content of this embodiment.

Referring to FIG. 4, the data serialization circuit 120 mainly includes a first switch 410, a second switch 420, a first combination logic 415, and a second combination logic 425. The first combination logic 415 receives the clock positive edge trigger signal CLKOUT_T and the trigger mask signal DMASK, and generates a first switch signal SW1. The second combination logic 425 receives the clock negative edge trigger signal CLKOUT_C and the trigger mask signal DMASK, and generates a second switch signal SW2. The control terminal of the first switch 410 receives a first switching signal SW1. The receiving end of the first switch 410 receives the positive edge data D + to be tested. The output terminal of the first switch 410 is coupled to the output terminal OUT of the data serialization circuit 120. The control terminal of the second switch 420 receives the second switching signal SW2. The receiving end of the second switch 420 receives the negative edge test data D-. An output terminal of the second switch 420 is also coupled to an output terminal OUT of the data serialization circuit 120. Therefore, when the trigger mask signal DMASK is enabled (ie, logic “1”), the first combination logic 415 enables the first switch signal SW1 according to the trigger mask signal DMASK and the positive edge trigger signal CLKOUT_T. The second combination logic 425 continuously disables the second switch signal SW2 according to the trigger mask signal DMASK and the negative edge trigger signal CLKOUT_C. Therefore, the receiving end of the first switch 410 is coupled to the output end of the first switch 410 due to the enabling of the first switch signal SW1, so as to output positive edge data D + to be tested.

In contrast, when the trigger mask signal DMASK is disabled (ie, logic "0"), The first combination logic 415 continuously disables the first switch signal SW1 according to the trigger mask signal DMASK and the positive edge trigger signal CLKOUT_T. The second combination logic 455 enables the second switch signal SW2 according to the trigger mask signal DMASK and the negative edge trigger signal CLKOUT_C. Therefore, the receiving end of the second switch 420 is coupled to the output terminal of the second switch 420 due to the enabling of the second switch signal SW2, so as to output the negative edge data D- to be measured.

FIG. 5 is a flowchart of a data reading method for testability design according to an embodiment of the present invention. The data reading method in FIG. 5 is applicable to the data reading device 100 including the data serialization circuit 120 in FIG. 1. Please refer to FIG. 5. In step S510, the data serialization circuit 120 of the data reading device 100 obtains a clock positive edge trigger signal CLKOUT_T, a clock negative edge trigger signal CLKOUT_C, a trigger mask signal DMASK, and the data to be measured. In step S520, the data serialization circuit 120 masks one of the clock positive edge trigger signal CLKOUT_T and the clock negative edge trigger signal CLKOUT_C according to the trigger mask signal DMASK, and according to the clock positive edge trigger signal that is not masked. The CLKOUT_T or clock negative edge trigger signal CLKOUT_C provides a part of the data to be tested to the output terminal of the data serialization circuit 120 as an output signal of the data reading device 100.

Step S520 may also be implemented in the following steps. When the clock positive edge trigger signal CLKOUT_T is masked according to the trigger mask signal DMASK, the data serialization circuit 120 outputs the negative edge test data D-. When the negative clock trigger signal CLKOUT_C is masked according to the trigger mask signal DMASK, the data serialization circuit 120 outputs the positive data D + to be tested. The implementation of the above steps has been disclosed in various implementations of the present invention. Example.

In summary, the data reading device and data reading method according to the embodiments of the present invention can use an additional trigger mask signal to block or mask the clock positive edge trigger signal and clock when reading the signal to be measured. One of the negative edge trigger signals, and another trigger signal that is not masked is used to obtain the corresponding part of the data to be tested. As a result, the output time of the data to be measured will increase from half of a clock cycle of the original clock to a clock cycle. In this way, the available data valid window can be increased without adjusting the internal data type in the chip using this data reading device, without changing the clock or related configuration, and making the external test machine easier. To judge the correctness of the data to be tested obtained by the data reading device.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims (10)

A data reading device for testability design includes a buffer to temporarily store data to be tested and output serialized data to be tested; and a data serialization circuit coupled to the buffer, wherein The data serialization circuit receives a clock positive edge trigger signal, a clock negative edge trigger signal, and a trigger mask signal, and receives the serialized data to be tested from the buffer, wherein the data serialization circuit is based on The trigger mask signal is used to mask one of the positive clock edge trigger signal and the negative clock edge trigger signal, and is based on the positive clock edge trigger signal or the negative clock edge that is not masked. An edge trigger signal is used to provide a part of the serialized data to be tested to an output end of the data serialization circuit as an output signal of the data reading device. The data reading device according to item 1 of the scope of patent application, wherein the serialized data to be tested includes positive data to be tested corresponding to the clock positive edge trigger signal and corresponding to the negative clock edge The negative edge of the trigger signal is the data to be tested, and the data serialization circuit includes a first switch whose control end receives a first switch signal generated by the clock positive edge trigger signal and the trigger mask signal, A receiving end of the first switch receives the positive edge data to be tested, an output end of the first switch is coupled to the output end of the data serialization circuit; and a second switch, a control end of which receives The clock negative edge trigger signal and the second switch signal generated by the trigger mask signal, the receiving end of the second switch receives the negative edge test data, and the output end of the second switch is coupled to the The output terminal of the data serialization circuit, wherein when the clock positive edge trigger signal is masked according to the trigger mask signal, the second switch signal is enabled to enable the second switch The receiving end is coupled to the first The output ends of the two switches, so as to output the data of the negative edge to be measured. When the clock negative edge trigger signal is masked according to the trigger mask signal, the first switch signal is enabled to enable the The receiving end of the first switch is coupled to the output end of the first switch, so as to output the positive edge data to be tested. The data reading device according to item 1 of the patent application scope, wherein the data reading device further comprises: an off-chip driver, coupled to the data serialization circuit to receive the output signal of the data reading device And a pad, which is electrically connected to the off-chip driver, wherein the off-chip driver provides a portion of the serialized test data to the pad according to the output signal. The data reading device according to item 1 of the patent application scope further includes a memory array, wherein the serialized data to be tested is stored or generated by the memory array. The data reading device according to item 1 of the scope of patent application, wherein the data serialization circuit covers one of the clock positive edge trigger signal and the clock negative edge trigger signal according to the trigger mask signal. One, thereby increasing the data valid window of the serialized test data of the part, wherein the serialized test data of the part corresponds to the clock positive edge trigger signal that is not masked And the other of the clock negative trigger signal. The data reading device according to item 1 of the scope of patent application, wherein the data reading device is applied to a dynamic data random access memory (DRAM) device. The data reading device according to item 1 of the patent application scope, wherein the clock positive edge trigger signal is enabled when the clock is switched from the negative edge to the positive edge, and the clock negative edge trigger signal is Enable when positive edge transitions to negative edge. A data reading method for testability design is applicable to a data reading device including a data serialization circuit. The data reading method includes: obtaining a clock positive edge trigger signal, a clock negative edge trigger signal, and a trigger. Mask signal, and serialize the data to be tested from the buffer; and according to the trigger mask signal to mask one of the clock positive edge trigger signal and the clock negative edge trigger signal, and The unmasked positive clock edge trigger signal or the negative clock edge trigger signal is used to provide a part of the serialized data to be tested to the output of the data serialization circuit as the data read Take the output signal of the device. The data reading method according to item 8 of the scope of patent application, wherein the serialized data to be tested includes the data to be tested corresponding to the positive edge trigger signal of the clock and the negative edge to the clock The negative edge of the trigger signal is the data to be measured, and one of the positive clock edge trigger signal and the negative clock edge trigger signal is masked, and the negative clock edge trigger signal or the negative clock edge trigger signal is not masked. The step of triggering the negative edge trigger signal to provide a part of the serialized data to be tested to the output end of the data serialization circuit as the output signal of the data reading device includes: When the positive clock edge trigger signal is masked according to the trigger mask signal, output the negative edge test data; and when the negative clock edge trigger signal is masked according to the trigger mask signal, output The positive edge data to be tested. The data reading method according to item 8 of the patent application scope, wherein the data serialization circuit masks one of the clock positive edge trigger signal and the clock negative edge trigger signal according to the trigger mask signal. , Thereby increasing the data valid window of the serialized test data of the part, wherein the serialized test data of the part corresponds to the positive clock edge trigger signal and The clock negative edge trigger signal is the other.