TWI659324B - Method and system for generating circuit planning results - Google Patents

Abstract

A storage unit of a circuit planning result generating system stores a plurality of neuron arrays, and each neuron array includes a plurality of weight values corresponding to a multiplication operation. When a processing unit of the circuit planning result generating system allocates each neuron array to one of a plurality of array groups according to a similar condition, and generates corresponding circuit data according to all the neuron arrays of each array group and Number of logic gates, each circuit data includes a plurality of arithmetic logic circuits corresponding to the multiplication operations, and then, the processing unit selects the least number of corresponding logic gates or the first allocated nerve according to all circuit data of each array group The circuit data of the meta array is used as a common circuit data of the array group, and a circuit planning result including the common circuit data is generated.

Description

Method and system for generating circuit planning results

The invention relates to a method for generating a circuit planning result, in particular to a method for generating a circuit planning result involving automatic optimization. The invention also relates to a circuit planning result generating system capable of implementing the circuit planning result generating method.

Artificial Neural Network (ANN), also known as neural network or artificial neural network, is a network system made up of a large number of neurons. The trained neural network can use complex mathematical models for complex information processing. For example, image recognition, natural language analysis, human behavior or natural phenomenon prediction or statistics are all applications of neural network.

Referring to FIG. 1, FIG. 1 is a neuron operation model common in the existing neural network technology. In the neuron operation model, X ₀ to X _N respectively represent a plurality of input variables that are input to the neuron operation model. W ₀ to W _N respectively represent multiple weight variables in the neuron operation model. f (u) represents a transfer function of the neuron operation model, and the transfer function can also be called an activation function. u represents the result of multiplying the variables (X ₀ ~ X _N ) by the corresponding preset weights (W ₀ ~ W _N ). y represents the result obtained by inserting u into the conversion function. y and u can be expressed by the following mathematical formulas:

In the training process of a class of neural networks, a large amount of sample data is converted into multiple input matrices composed of the input variables (ie, X ₀ to X _N ), and the input matrices Input to the neural network for learning. In the learning process, this type of neural network performs multiplication operations on the input matrices and multiple weight matrices composed of the weight variables (that is, W ₀ to W _N ), and performs a multiplication operation on the output results after the operations. The original weighting matrices are optimized.

It is worth noting that the multiplication of each input variable and each weight variable requires a corresponding multiplier to execute, and each multiplier contains two input terminals for the input variable and the weight variable respectively, And an output terminal for outputting the operation result of the input variable and the weight variable.

If this type of neural network defines a total of 10,000 weight matrices after training, and assuming that each weight matrix has a size of three by three and contains nine weight variables, if you want to use this type of neural network Commercialized and implemented as a type of neural network chip, which means that when there is no memory in this type of neural network chip, 90,000 multipliers need to be built in order to fully implement the multiplication operations represented by these weight matrices. Or build a large amount of memory in the neural network chip to reduce the number of multipliers, in order to fully implement the multiplication operations represented by these weight matrices. However, a large number of multipliers or memory requirements will make this type of neural network chip have higher wiring complexity and circuit area, and it will also make it difficult to reduce the manufacturing cost of this type of neural network chip. If this type of neural network is to be commercialized and implemented as a type of neural network system program for a central processing unit (Central Processing Unit) or a graphic processing unit (Graphic Processing Unit) or a digital signal processor (Digital Signal Processor), a large number of The multiplication operations and memory read and write requirements will make this type of neural network require higher speed processors and memory. Therefore, how to optimize the circuit planning of the neural network chip has become the subject to be solved in this case.

Therefore, one object of the present invention is to provide a circuit planning result generation method capable of performing circuit optimization for a neural-like chip.

Therefore, the circuit planning result generating method of the present invention is implemented by a circuit planning result generating system. The circuit planning result generating system includes a storage unit and a processing unit electrically connected to the storage unit. The storage unit stores a plurality of neuron arrays in advance. Each neuron array contains multiple weight values, and each weight value corresponds to a multiplication operation. The circuit planning result generating method includes the following steps: (A) the processing unit assigns each neuron array to one of a plurality of array groups, and the neuron array first assigned to each array group is used as the A reference neuron array of the array group, the reference neuron array and each of the other neuron arrays in the array group meet a similar condition related to the weight values. (B) The processing unit generates a corresponding circuit data and a number of logic gates according to the weight values of each neuron array of the array groups, and each circuit data includes the weights corresponding to the neuron array The number of logic circuits of the multiplication operation of the value, the number of the logic gates corresponding to each neuron array is the total number of the plurality of logic gates of the logic circuits corresponding to the circuit data of the neuron array. (C) The processing unit uses the circuit data corresponding to the least number of logic gates in each array group as a common circuit data of the array group, and generates an operation logic including the common circuit data Circuit planning results for the circuit.

In some implementation aspects of the method for generating a circuit planning result of the present invention, in step (A), the processing unit first calculates the reference neuron array and each neuron array that has not been assigned to any array group. A total weight difference between the total weight difference equal to the sum of each weight value of the reference neuron array and the absolute value of the difference between each weight value corresponding to the neuron array, the processing unit and When it is determined that the reference neuron array and the neuron array meet the similar condition, the neuron array is allocated to the array group to which the reference neuron array belongs, and the similar condition is that the total weight difference is less than a predetermined Threshold.

In some implementation aspects of the method for generating a circuit planning result of the present invention, in step (B), each operation logic circuit further includes a single input for a variable to perform the corresponding multiplication corresponding to the corresponding weight value. An input terminal of the operation, and a single output terminal for outputting the operation result of the multiplication operation.

In some implementation aspects of the method for generating a circuit planning result of the present invention, the method for generating a circuit planning result further includes a step (E) before step (B): the processing unit stores at least one of the neuron arrays. At least one of the weight values included is updated with an approximate value, where the approximate value is equal to the power of x and x is an integer.

Another circuit planning result generating method provided by the present invention is implemented by a circuit planning result generating system. The circuit planning result generating system includes a storage unit and a processing unit electrically connected to the storage unit. The storage unit stores a plurality of storage units in advance. Neuron array, each neuron array contains multiple weight values, each weight value corresponds to a multiplication operation, the circuit planning result generation method includes the following steps: (A) the processing unit allocates each neuron array to multiple One of the array groups, the neuron array first assigned to each array group serves as a reference neuron array of the array group, the reference neuron array and other neurons in the array group Each of the arrays meets a similar condition related to the weight values. (B) The processing unit generates a pair of common circuit data corresponding to the array group according to the weight values of the reference neuron array of each array group, and the common circuit data includes a plurality of arithmetic logic circuits. The logic circuits are respectively related to the multiplication operations corresponding to the weight values of the reference neuron array, and each operation logic circuit includes at least one logic gate. (C) The processing unit generates a circuit planning result of the arithmetic logic circuits including the shared circuit data.

In some implementation aspects of another method for generating a circuit planning result of the present invention, in step (A), the processing unit first calculates the reference neuron array and each nerve that has not been assigned to any array group. A total weight difference between the element arrays, the total weight difference being equal to the sum of each weight value of the reference neuron array and the absolute value of the difference between each weight value corresponding to the neuron array, the process When determining that the reference neuron array and the neuron array meet the similar conditions, the unit assigns the neuron array to the array group to which the reference neuron array belongs. The similarity condition is that the total weight difference is less than A predetermined threshold.

In some implementation forms of another method for generating a circuit planning result according to the present invention, in step (B), each operation logic circuit further includes a single input for a variable to correspond to the corresponding weight value execution. An input terminal of the multiplication operation and a single output terminal for outputting an operation result of the multiplication operation.

In some implementation aspects of another method for generating a circuit planning result of the present invention, the method for generating a circuit planning result further includes a step (E) before step (B): the processing unit includes at least one of the neuron arrays. At least one of the weights included in the method is updated with an approximate value, where the approximate value is equal to the power of x and x is an integer.

Another object of the present invention is to provide a circuit planning result generating system capable of implementing the circuit planning result generating method.

The circuit planning result generating system of the present invention includes a storage unit and a processing unit electrically connected to the storage unit. The storage unit stores a plurality of neuron arrays in advance, and each neuron array includes a plurality of weight values, and each weight value corresponds to a multiplication operation. When the processing unit receives a circuit planning result generating instruction, each neuron array is assigned to one of a plurality of array groups, and the neuron array first assigned to each array group is used as the array group. A reference neuron array of the group meets a similar condition with respect to the weight values between each of the reference neuron array and each of the other neuron arrays in the array group. Then, the processing unit generates a corresponding circuit data and a number of logic gates according to the weight values of each neuron array of the array groups, and each circuit data includes the weight values corresponding to the neuron array. The number of logic circuits of the multiplication operation of the corresponding logic circuit is the total number of logic gates included in the logic circuits corresponding to the circuit data of the neuron array. Then, the processing unit uses the circuit data corresponding to the least number of logic gates in each array group as a common circuit data of the array group, and generates an arithmetic logic circuit including the common circuit data. Circuit planning results.

In some implementation aspects of the circuit planning result generation system of the present invention, the processing unit first calculates a total weight difference between the reference neuron array and each neuron array that has not been assigned to any array group. The total weight difference is equal to the sum of each weight value of the reference neuron array and the absolute value of the difference between each weight value corresponding to the neuron array, and the processing unit determines the reference neuron When the array and the neuron array meet the similar condition, the neuron array is allocated to the array group to which the reference neuron array belongs, and the similar condition is that the total weight difference is less than a predetermined threshold.

In some implementation forms of the circuit planning result generation system of the present invention, each operation logic circuit further includes a single input terminal for a variable input to perform the multiplication operation corresponding to the corresponding weight value, and a single An output terminal for outputting the operation result of the multiplication operation.

In some implementation forms of the circuit planning result generation system of the present invention, before generating the circuit data, the processing unit updates at least one weight value included in at least one of the neuron arrays with an approximate value, wherein , The approximate value is equal to the power of x, and x is an integer.

Another circuit planning result generating system provided by the present invention includes a storage unit and a processing unit electrically connected to the storage unit. The storage unit stores a plurality of neuron arrays in advance, and each neuron array includes a plurality of weight values, and each weight value corresponds to a multiplication operation. When the processing unit receives a circuit planning result generating instruction, each neuron array is assigned to one of a plurality of array groups, and the neuron array first assigned to each array group is used as the array group. A reference neuron array of the group meets a similar condition with respect to the weight values between each of the reference neuron array and each of the other neuron arrays in the array group. Then, the processing unit generates a pair of common circuit data corresponding to the array group according to the weight values of the reference neuron array of each array group, and the common circuit data includes a plurality of operation logic circuits, and the operation logic The circuits are respectively related to the multiplication operations corresponding to the weight values of the reference neuron array, and each operation logic circuit includes at least one logic gate. Then, the processing unit generates a circuit planning result of the operation logic circuits including the shared circuit data.

In some implementation aspects of another circuit planning result generation system of the present invention, the processing unit first calculates a total between the reference neuron array and each neuron array that has not been assigned to any array group. Weight difference, the total weight difference is equal to the sum of each weight value of the reference neuron array and the absolute value of the difference between each weight value corresponding to the neuron array, and the processing unit determines the reference When the neuron array and the neuron array meet the similar condition, the neuron array is allocated to the array group to which the reference neuron array belongs, and the similar condition is that the total weight difference is less than a predetermined threshold.

In some implementation forms of another circuit planning result generating system of the present invention, each operation logic circuit further includes a single input terminal for a variable input to perform the multiplication operation corresponding to the corresponding weight value, And a single output terminal for outputting the operation result of the multiplication operation.

In some implementation forms of another circuit planning result generation system of the present invention, before generating the circuit data, the processing unit updates at least one weight value included in at least one of the neuron arrays with an approximate value. , Where the approximate value is equal to the power of x and x is an integer.

The effect of the present invention is that, by implementing the method for generating a circuit planning result of the present invention, the processing unit can first allocate each neuron array to one of the array groups, and then generate corresponding array groups respectively. The shared circuit data, and the circuit planning result containing the shared circuit data, the circuit planning result can be used to implement the neural network into the neural network chip, and can effectively reduce the neural network The number of logic gates of the network chip optimizes the circuit of this type of neural network chip, so it can indeed achieve the purpose of cost invention.

Before the present invention is described in detail, it should be noted that in the following description, similar elements are represented by the same numbers.

Referring to FIG. 2, a first embodiment of a circuit planning result generating system 1 of the present invention is used to generate a circuit planning result corresponding to a trained neural network or the like. More specifically, the circuit planning result is used for The trained neural network is implemented as a physical neural network chip. And the circuit planning result is related to a logic operation circuit in this type of neural network chip that is used to multiply a plurality of variables with a plurality of preset weights, respectively.

The circuit planning result generating system 1 includes a storage unit 11 and a processing unit 12 electrically connected to the storage unit 11. The storage unit 11 may be, for example, a hard disk or a hard disk array composed of multiple hard disks. The processing unit 12 may be, for example, a central processing unit or a module processed in parallel by multiple central processing units. The processing unit 12 is, for example, disposed on a motherboard (not shown), and is electrically connected to the storage unit 11 through the motherboard, but is not limited thereto.

The storage unit 11 stores a plurality of neuron arrays M arranged in a predetermined order in advance. Each neuron array M includes a plurality of weight values, and each weight value corresponds to a multiplication operation. For example, if one of the weight values is "15", the multiplication operation corresponding to the weight value is "multiply by 15". In this embodiment, since this type of neural network has been trained, each weight value is set to a fixed constant, and each neuron array M is, for example, a 3 by 3 matrix, and contains nine weights. Value, but not limited to this.

For example, this type of neural network chip can be used in the field of image recognition, for example, to identify whether a bird exists in an image, and each neuron array M is used as a feature filter, for example. , And is used by the neural network to identify whether there are corresponding features represented by the neuron array M (such as a bird's mouth, eyes, or wings) in the image according to the neuron array M, but it is not based on this. Limited.

Referring to FIG. 2 and FIG. 3 at the same time, how to implement a circuit planning result generation method in the circuit planning result generation system 1 of this embodiment is exemplarily described in detail below.

First, in step S1, when the processing unit 12 receives a circuit planning result generation instruction, the processing unit 12 performs a classification procedure on the neuron arrays M according to the similarity of the neuron arrays M to Each neuron array M is assigned to one of a plurality of array groups. The circuit planning result generating instruction is generated, for example, by a user operating an input device (such as a keyboard or a mouse), but is not limited thereto.

In the classification procedure, for example, the processing unit 12 first assigns one of the order of the neuron arrays M as a reference neuron array M ′, and assigns the reference neuron array M ′ to a new definition. Out of the array group. Next, the processing unit 12 calculates a total weight difference between the reference neuron array M ′ and each other neuron array M, and judges the reference neuron array M ′ and each other neuron according to each weight difference. Whether the arrays M meet a similar condition. In this embodiment, the total weight difference is equal to the sum of the absolute values of the differences between each weight value of the reference neuron array M ′ and each weight value corresponding to each other neuron array M. A similar condition is that the total weight difference is less than a predetermined threshold, and the predetermined threshold may be, for example, 5 but is not limited thereto. Once the processing unit 12 determines that any one of the neuron arrays M and the reference neuron array M ′ meet the similar conditions and serves as a similar neuron array M *, the processing unit 12 processes the similar neurons The array M * is allocated to the array group to which the reference neuron array M 'belongs.

For the convenience of explanation, the nine weight values included in each neuron array M are defined as the first weight value to the ninth weight value arranged from left to right and top to bottom, respectively. For example, a neuron array M1 and a neuron array M2 shown below. For example, the first weight value of the neuron array M1 is "9", and the first weight value of the neuron array M2 is "8". Therefore, a first weight difference between the neuron array M1 and the neuron array M2 is "1". Similarly, the second weight value of the neuron array M1 and the neuron array M2 are both "36". Therefore, a second weight difference between the neuron array M1 and the neuron array M2 is "0" . By analogy, the third to ninth weight difference between the neuron array M1 and the neuron array M2 is "0", "0", "0", "2", "1", "0", "0". The total weight difference between the neuron array M1 and the neuron array M2 is equal to the sum of the first weight difference to the ninth weight difference, and is equal to "4". Neuron array M1 9 36 27 7 97 35 36 1 77 Neuron Array M2 8 36 27 7 97 33 37 1 77

It is particularly noted that, in this embodiment, the processing unit 12 performs the classification procedure on the neuron arrays M in an exhaustive search manner, for example, but is not limited thereto. For example, if the number of the neurons is one thousand and they are numbered in the order of neuron array M1 to neuron array M1000, the processing unit 12 first uses the neuron array M1 as the reference, for example. The neuron array M 'is assigned to a first array group. Then, the processing unit 12 sequentially assigns each of the neuron array M2 to the neuron array M1000 and the neuron array M1 that meet the similar conditions to the first array group. Next, the processing unit 12 assigns the highest priority order among all the neuron arrays M that have not been assigned to any array group as a new reference neuron array M ′, and assigns it to a second array group. And perform the determination of the similar condition with all other neuron arrays M that have not been assigned to any array group until each of the neuron array M1 to the neuron array M1000 is assigned to the array group. So far. In this way, a reference neuron array M ′ corresponding to the array group and assigned to the array group first exists in each array group, and the reference neuron in each array group The similar condition is met between the array M 'and all other neuron arrays M in the same array group. It should be noted that each array group may also include only the reference neuron array M ', but not other neuron arrays M similar to the reference neuron array M'.

After the processing unit 12 allocates each neuron array M to one of the array groups, step S2 is then performed.

In step S2, the processing unit 12 generates a pair of circuit data corresponding to the array group and the neuron array M according to the weight values of each neuron array M of each array group, and a pair of corresponding Number of logic gates for circuit data.

For example, if the foregoing first array group includes the neuron array M1, the neuron array M2, and the neuron array M100, then in step S2, the processing unit 12 will perform the calculation according to the first array group. A circuit data D1, a circuit data D2, and a circuit data D100 are generated, and a corresponding number of logic gates N1, a number of logic gates N2, and a number of logic gates N100 are generated.

In this embodiment, each circuit data includes nine operation logic circuits, and the operation logic circuits are respectively related to nine multiplication operations corresponding to the weight values of the corresponding neuron array M, and each operation logic The circuit is, for example, a logic gate combination, including at least one logic gate, a single input terminal for a variable input to perform the multiplication operation corresponding to the corresponding weight value, and a single output terminal for the multiplication operation. The output of the operation result. The number of logic gates indicates the total number of all logic gates included in the operational logic circuits of the circuit data. It is specifically stated that, because the weight values are constant in this embodiment, each arithmetic logic circuit only needs a single input terminal for a variable input.

It is added that the corresponding operation logic circuit is generated according to each weight value, which is the general knowledge about the design of arithmetic operation circuits in the discipline of digital logic design, such as multipliers, adders, shifters, or registers, etc. Different logic circuits implement the same multiplication operation, which makes the number of logic gates of the logic circuit different, so I won't go into details here.

Taking the aforementioned neuron array M1 as an example, the first to ninth weight values of the neuron array M1 are "9", "36", "27", "7", "97", "97" "35", "36", "1", and "77" are those arithmetic logic circuits corresponding to the circuit data of the neuron array M1, such as "multiply by 9", "multiply by 36", Nine multiplier circuits of "multiply by 27", "multiply by 7", "multiply by 97", "multiply by 35", "multiply by 36", "multiply by 1" and "multiply by 77". The number N1 of logic gates corresponding to the circuit data D1 of the neuron array M1 is equal to the total number of all logic gates included in the nine multiplier circuits.

After the processing unit 12 generates the circuit data and the corresponding number of the logic gates, it proceeds to step S3.

In step S3, the processing unit 12 selects a pair of circuit data corresponding to the array group and serving as a common circuit data from all the circuit data corresponding to each array group. Specifically, the shared circuit data corresponding to each array group is the circuit data corresponding to the least number of logic gates among all the circuit data corresponding to the array group. In other words, the logic gates used by the operational logic circuits included in the shared circuit data are the least among all the circuit data corresponding to the same array group.

Following the previous example, it is assumed that the first array group includes the neuron array M1, the neuron array M2, and the neuron array M100, and the neuron array M1, the neuron array M2, and the neuron array M100. The corresponding circuit information and the number of these logic gates are shown in the table below. Assuming that among the number of logic gates N1, the number of logic gates N2, and the number of logic gates N100, the value of the number of logic gates N2 is the smallest of the three, then in step S3, the processing unit 12 will change the logic The circuit data M2 corresponding to the gate number N2 is used as the common circuit data corresponding to the first array group. First array group Neuron array M1 Circuit Information M1 Number of logic gates N1 Neuron Array M2 Circuit Information M2 Number of logic gates N2 Neuron Array M100 Circuit Information M100 Number of logic gates N100

After the processing unit 12 selects the shared circuit data corresponding to each array group, it proceeds to step S4.

In step S4, the processing unit 12 generates the circuit planning result for implementing the neural network as the neural network chip, and the circuit planning result includes the operational logic circuits of the shared circuit data. It is added that, in this embodiment, the circuit planning result is, for example, an electronic file that can be accessed and transmitted by computer equipment, and the operation logic circuits included in the circuit planning result may be, for example, multiple different It is presented in a manner such as a schematic diagram, a layout, or a code for describing such an operation logic circuit, but is not limited thereto.

The effect of manufacturing the neural network chip based on the circuit planning result is that it can effectively reduce the number of logic gates of the neural network chip. Taking the previous example, although the first array group includes the neuron array M1, the neuron array M2, and the neuron array M100, the circuit planning result only includes the circuit data M2 corresponding to the neuron array M2. Without including the circuit data M1 and the circuit data M100. Because the neuron array M1, the neuron array M2, and the neuron array M100 have a high similarity with each other, when multiplication is required to be performed with the neuron array M1 or the neuron array M100, even if the The arithmetic logic circuits included in the circuit data M2 replace the circuit data M1 and the circuit data M100 without causing much error. In this way, it is possible to achieve the effect that the three neuron arrays M share a single piece of circuit data and greatly save the number of logic gates.

To further illustrate, if the storage unit 11 stores ten thousand neuron arrays M, and if an arithmetic logic circuit for the circuit data of each neuron array M is to be built in this type of neural network chip, this processing The unit 12 needs to generate a total of 10,000 circuit data corresponding to the neuron arrays M, and the 10,000 circuit data contains a total of 90,000 operation logic circuits. In this way, this type of neural network chip The number of circuits in it is quite large.

However, if the neural network chip is manufactured by using the circuit planning result of this embodiment, the neuron arrays M in each array group can effectively share the shared circuit data corresponding to the array group. First, assuming that in step S1, the processing unit 12 defines a total of three thousand array groups, the circuit planning result of step S4 will only include three thousand operation logic circuits of circuit data, and a percentage is saved. Number of logic gates around seventy.

Furthermore, in this embodiment, the processing unit 12 uses the circuit data with the least number of logic gates in each array group as the shared circuit data, so the number of logic gates can be further saved.

The hardware of the second embodiment of the circuit planning result generation system 1 of the present invention is the same as the first embodiment, however, the method of generating the circuit planning result implemented by the second embodiment is different from the first embodiment. , The differences are explained below.

In the method for generating a circuit planning result implemented in the second embodiment, step S1 is the same as the first embodiment and will not be repeated here, but in step S2 of this embodiment, the processing unit 12 is only based on each The reference neuron array M ′ of an array group generates the circuit data corresponding to the reference neuron array M ′, and does not generate circuit data for the other neuron arrays M other than the reference neuron array M ′. Moreover, the processing unit 12 directly uses the circuit data corresponding to the reference neuron array M 'as the common circuit data corresponding to the array group, and further generates the circuit planning result including all such common circuit data.

The hardware of the third embodiment of the circuit planning result generation system 1 of the present invention is the same as the first embodiment, however, the method for generating the circuit planning result implemented by the third embodiment is different from the first embodiment. , The differences are explained below.

In the method for generating a circuit planning result implemented in the third embodiment, step S1 is the same as that in the first embodiment, and will not be repeated here, but in step S2 of this embodiment, the processing unit 12 further Some of the weight values contained in the isoneuron array M are updated with an approximate value. In this embodiment, the approximate value is equal to the power of x, and x is an integer. Specifically, the processing unit 12 may, for example, change the weight value of the number “7” or “9” to 8 “that is, 2 Update the value of "3 to the power of 3", update the value of the value of "15" or "17" to 16 "that is, the power of 4 to the 2", update the value of the value to "31" or "33" to 32 That is, the power of 2 "is updated, and the rest can be deduced by analogy. After the partial weight values included in some of these neuron arrays M are updated to the power of 2 x, the processing unit 12 generates corresponding values based on the weight values of each of the updated neuron arrays M. Column of the circuit information. The effect of replacing part of the weight value with the power of 2 is that the arithmetic logic circuit using the power of 2 as a multiplier can be implemented using a simple shifter, compared to other than powers other than 2 This can further save the number of logic gates.

In summary, by implementing the circuit planning result generating method 1 of the present invention, the circuit planning result generating system 1 can allocate each neuron array M to one of the array groups, and then generate corresponding responses. And other common circuit data of the array group, and the circuit planning result containing the common circuit data, the circuit planning result can be used to implement the neural network into the neural network chip, and can effectively The number of logic gates of this type of neural network chip is reduced, and the circuit of this type of neural network chip is optimized, so it can indeed achieve the purpose of cost invention.

However, the above are only examples of the present invention. When the scope of implementation of the present invention cannot be limited in this way, any simple equivalent changes and modifications made in accordance with the scope of the patent application and the content of the patent specification of the present invention are still Within the scope of the invention patent.

1‧‧‧Circuit planning result generation system

11‧‧‧Storage Unit

12‧‧‧ processing unit

M‧‧‧ Neuron Array

Steps S1 ~ S4‧‧‧‧

Other features and effects of the present invention will be clearly presented in the embodiment with reference to the drawings, wherein: FIG. 1 is a schematic diagram showing a neuron operation model of the existing neural network-like technology; FIG. 2 is the present invention A block diagram of a first embodiment of a circuit planning result generating system; and FIG. 3 is a flowchart illustrating how the first embodiment implements a method of generating a circuit planning result.

Claims (16)

A circuit planning result generating method is implemented by a circuit planning result generating system. The circuit planning result generating system includes a storage unit and a processing unit electrically connected to the storage unit. The storage unit stores a plurality of neuron arrays in advance. A neuron array includes multiple weight values, and each weight value corresponds to a multiplication operation. The circuit planning result generation method includes the following steps: (A) the processing unit assigns each neuron array to one of a plurality of array groups Or, the neuron array first assigned to each array group serves as a reference neuron array of the array group, and each of the reference neuron array and each of the other neuron arrays in the array group (B) The processing unit generates a corresponding circuit data and a number of logic gates according to the weight values of each neuron array of the array groups. A circuit data includes a plurality of operation logic circuits corresponding to the multiplication operations of the weight values of the neuron array, corresponding to each neuron array The number of logic gates is the total number of logic gates included in the operational logic circuits corresponding to the circuit data of the neuron array; and (C) the processing unit corresponds to the logic in each array group. The circuit data with the smallest number of gates is used as a common circuit data of the array group, and a circuit planning result of the operation logic circuits including the common circuit data is generated. The method for generating a circuit planning result according to claim 1, wherein in step (A), the processing unit first calculates the reference neuron array and each neuron array that has not been assigned to any array group. A total weight difference between the total weight difference equal to the sum of each weight value of the reference neuron array and the absolute value of the difference between each weight value corresponding to the neuron array, the processing unit and When it is determined that the reference neuron array and the neuron array meet the similar condition, the neuron array is allocated to the array group to which the reference neuron array belongs, and the similar condition is that the total weight difference is less than a predetermined Threshold. The method for generating a circuit planning result according to claim 1, wherein in step (B), each operation logic circuit further includes a single input for a variable to perform the corresponding multiplication corresponding to the corresponding weight value An input terminal of the operation, and a single output terminal for outputting the operation result of the multiplication operation. The method for generating a circuit planning result according to claim 1, further comprising a step (D) before step (B): the processing unit converts at least one weight value included in at least one of the neuron arrays to An approximation update, where the approximation is equal to the power of x and x is an integer. A circuit planning result generating method is implemented by a circuit planning result generating system. The circuit planning result generating system includes a storage unit and a processing unit electrically connected to the storage unit. The storage unit stores a plurality of neuron arrays in advance. Each neuron array includes multiple weight values, and each weight value corresponds to a multiplication operation. The circuit planning result generation method includes the following steps: (A) the processing unit assigns each neuron array to a plurality of array groups. One, the neuron array first assigned to each array group serves as a reference neuron array for the array group, and each of the reference neuron array and other neuron arrays in the array group A similar condition related to the weight values is met between them; (B) the processing unit generates a pair of common circuit data corresponding to the array group according to the weight values of the reference neuron array of each array group, The common circuit data includes a plurality of operation logic circuits, and the operation logic circuits are respectively related to the weight values of the reference neuron array. Corresponding to these multiplication operations, and each arithmetic logic circuit includes at least one logic gate; and (C) the result of the processing unit generates a programming circuit comprises an arithmetic logic circuit such those of the common circuit data. The method for generating a circuit planning result according to claim 5, wherein in step (A), the processing unit first calculates the reference neuron array and each neuron array that has not been assigned to any array group. A total weight difference between the total weight difference equal to the sum of each weight value of the reference neuron array and the absolute value of the difference between each weight value corresponding to the neuron array, the processing unit and When it is determined that the reference neuron array and the neuron array meet the similar condition, the neuron array is allocated to the array group to which the reference neuron array belongs, and the similar condition is that the total weight difference is less than a predetermined Threshold. The method for generating a circuit planning result according to claim 5, wherein in step (B), each arithmetic logic circuit further includes a single input for a variable to perform the corresponding multiplication corresponding to the corresponding weight value An input terminal of the operation, and a single output terminal for outputting the operation result of the multiplication operation. The method for generating a circuit planning result according to claim 5, further comprising a step (D) before step (B): the processing unit converts at least one weight value included in at least one of the neuron arrays to An approximation update, where the approximation is equal to the power of x and x is an integer. A circuit planning result generation system includes: a storage unit that stores a plurality of neuron arrays in advance, each neuron array includes a plurality of weight values, each weight value corresponding to a multiplication operation; and a processing unit electrically connected to the storage A unit, wherein when the processing unit receives a circuit planning result generating instruction, each neuron array is assigned to one of a plurality of array groups, and the neuron array is first assigned to each array group As a reference neuron array of the array group, the reference neuron array and each of the other neuron arrays in the array group meet a similar condition related to the weight values; then, the processing The unit generates a corresponding circuit data and a number of logic gates according to the weight values of each neuron array of the array groups. Each circuit data includes the multiplications corresponding to the weight values of the neuron array. A plurality of operation logic circuits for operation, the number of the logic gates corresponding to each neuron array is the operation logic corresponding to the circuit data of the neuron array The total number of multiple logic gates included in the circuit; then, the processing unit uses the circuit data corresponding to the least number of logic gates in each array group as a common circuit data of the array group, and generates a The circuit planning results of the operational logic circuits containing the shared circuit data. The circuit planning result generating system according to claim 9, wherein the processing unit first calculates a total weight difference between the reference neuron array and each neuron array that has not been assigned to any array group. The total weight difference is equal to the sum of each weight value of the reference neuron array and the absolute value of the difference between each weight value corresponding to the neuron array, and the processing unit determines the reference neuron When the array and the neuron array meet the similar condition, the neuron array is allocated to the array group to which the reference neuron array belongs, and the similar condition is that the total weight difference is less than a predetermined threshold. The circuit planning result generation system according to claim 9, wherein each operation logic circuit further includes a single input terminal for a variable input to perform the multiplication operation corresponding to the corresponding weight value, and a single An output terminal for outputting the operation result of the multiplication operation. The circuit planning result generating system according to claim 9, wherein before generating the circuit data, the processing unit updates at least one weight value included in at least one of the neuron arrays with an approximate value, wherein , The approximate value is equal to the power of x, and x is an integer. A circuit planning result generation system includes: a storage unit that stores a plurality of neuron arrays in advance, each neuron array includes a plurality of weight values, each weight value corresponding to a multiplication operation; and a processing unit electrically connected to the storage A unit, wherein when the processing unit receives a circuit planning result generating instruction, each neuron array is assigned to one of a plurality of array groups, and the neuron array is first assigned to each array group As a reference neuron array of the array group, the reference neuron array and each of the other neuron arrays in the array group meet a similar condition related to the weight values; then, the processing The unit generates a pair of common circuit data corresponding to the array group according to the weight values of the reference neuron array of each array group. The common circuit data includes a plurality of operation logic circuits, and the operation logic circuits are respectively related to The multiplication operations corresponding to the weight values of the reference neuron array, and each operation logic circuit includes at least one logic gate; The processing unit generates a programming circuit comprising such a common result of such operation of the logic circuit information. The circuit planning result generation system according to claim 13, wherein the processing unit first calculates a total weight difference between the reference neuron array and each neuron array that has not been assigned to any array group. The total weight difference is equal to the sum of each weight value of the reference neuron array and the absolute value of the difference between each weight value corresponding to the neuron array, and the processing unit determines the reference neuron When the array and the neuron array meet the similar condition, the neuron array is allocated to the array group to which the reference neuron array belongs, and the similar condition is that the total weight difference is less than a predetermined threshold. The circuit planning result generation system according to claim 13, wherein each operation logic circuit further includes a single input terminal for a variable input to perform the multiplication operation corresponding to the corresponding weight value, and a single An output terminal for outputting the operation result of the multiplication operation. The circuit planning result generation system according to claim 13, wherein before the processing unit generates the circuit data, at least one weight value included in at least one of the neuron arrays is updated with an approximate value, wherein , The approximate value is equal to the power of x, and x is an integer.