TWI657690B - Image processing device - Google Patents

Abstract

The image processing device includes an input value receiving unit, a correction value calculating unit, an output value calculating unit, and an output value specifying unit. The receiving unit receives the input values of the first pixel and the second pixel adjacent to the first pixel, respectively. The correction value calculation unit calculates a correction value of the first pixel according to the plurality of component error values of the plurality of first adjacent pixels adjacent to the first pixel and the input number of the first pixel, and according to the adjacent second pixel A plurality of component error values of the plurality of second adjacent pixels and an input value of the second pixel are used to calculate a correction value of the second pixel. The output value calculation unit calculates the output values of the first pixel and the second pixel, respectively, based on the correction values of the first pixel and the second pixel. The output value specifying unit specifies the output values of the first pixel and the second pixel to the first pixel and the second pixel, respectively.

Description

Image processing device

The present disclosure relates to an image processing apparatus, and more particularly to an image processing apparatus based on error diffusion.

The quantization of pixel values of images is a common technique in image processing. However, quantization processing usually causes quantization errors of pixel values of images. In order to make the image not noticeable difference due to these quantization errors, error diffusion processing technology is a common halftone image processing technology, and error diffusion processing technology is used in the image. The quantization error of the pixel is distributed to adjacent pixels, thereby dispersing the quantization error. Compared with other halftone image processing technologies, error diffusion processing technology has considerable advantages in harmonizing halftone image quality and image processing efficiency.

For example, one of the conventional methods of error diffusion processing is to spread the error to the right pixel (horizontal direction diffusion) and the lower pixel (vertical direction diffusion). However, the horizontal diffusion method is disadvantageous for the hardware, such as high hardware design cost, limited output processing capacity, and fast transfer timing. Therefore, there is still room for improvement in the conventional error diffusion processing method.

The purpose of the present disclosure is to provide an image processing apparatus based on error diffusion and improved to improve the drawbacks of the conventional error diffusion processing method.

According to the above object of the present disclosure, an image processing apparatus includes an input value receiving unit, a correction value calculating unit, an output value calculating unit, and an output value specifying unit. The input value receiving unit is configured to receive an input value of the first pixel of the image and an input value of the second pixel, wherein the first pixel is adjacent to the second pixel, wherein the first pixel and the second pixel system are respectively located at the first position (x , y) and the second position (x+1, y). The correction value calculation unit is configured to calculate a correction value of the first pixel according to the plurality of component error values of the plurality of first adjacent pixels adjacent to the first pixel and the input value of the first pixel, and according to the second adjacent Calculating a correction value of the second pixel by using a plurality of component error values of the plurality of second adjacent pixels of the pixel and an input value of the second pixel, wherein the plurality of first adjacent pixel systems are respectively located at the third position (x-1, y), fourth position (x-1, y-1), fifth position (x, y-1) and sixth position (x+1, y-1), wherein the plurality of second adjacent pixel systems respectively It is located at the fifth position (x, y-1), the sixth position (x+1, y-1), and the seventh position (x+2, y-1). The output value calculation unit is configured to calculate an output value of the first pixel according to the correction value of the first pixel, and calculate an output value of the second pixel according to the correction value of the second pixel. The output value specifying unit is configured to specify an output value of the first pixel to the first pixel, and specify an output value of the second pixel to the second pixel.

In some embodiments, the correction value of the first pixel is a plurality of component error values of the plurality of first adjacent pixels and an input value of the first pixel. And a correction value of the second pixel is a sum of a plurality of component error values of the plurality of second adjacent pixels and an input value of the second pixel.

In some embodiments, the output value of the first pixel is the most significant bit (MSB) value of the correction value of the first pixel, and the output value of the second pixel is the highest correction value of the second pixel. Valid bit value.

In some embodiments, the image processing apparatus further includes an error value calculation unit configured to calculate an error value of the first pixel according to the correction value of the first pixel, and calculate an error of the second pixel according to the correction value of the second pixel. value.

In some embodiments, the error value of the first pixel is a least significant bit (LSB) value of the correction value of the first pixel, and the error value of the second pixel is the lowest correction value of the second pixel. Valid bit value.

In some embodiments, the component error value of the first neighboring pixel located at the third position (x-1, y) is A of the error value of the first neighboring pixel located at the third position (x-1, y) /Z; the component error value of the first adjacent pixel located at the fourth position (x-1, y-1) is the error value of the first adjacent pixel located at the fourth position (x-1, y-1) B/Z; the component error value of the first adjacent pixel located at the fifth position (x, y-1) is C/Z of the error value of the first adjacent pixel located at the fifth position (x, y-1) The component error value of the first adjacent pixel located at the sixth position (x+1, y-1) is D/ of the error value of the first adjacent pixel located at the sixth position (x+1, y-1) Z; a component error value of the second adjacent pixel located at the fifth position (x, y-1) is an error value of the second adjacent pixel located at the fifth position (x, y-1) E/Z; the component error value of the second adjacent pixel located at the sixth position (x+1, y-1) is the error value of the second adjacent pixel located at the sixth position (x+1, y-1) F/Z; the component error value of the second adjacent pixel located at the seventh position (x+2, y-1) is the error of the second adjacent pixel located at the seventh position (x+2, y-1) The value of G/Z; where A, B, C, D, E, F, G, Z are positive integers, and A+B+C+D+E+F+G=2*Z.

In some embodiments, A=7, B=3, C=6, D=1, E=F=G=5.

In some embodiments, the error value of the first adjacent pixel is a least significant bit (LSB) value of a correction value of the first adjacent pixel, and the error value of the second adjacent pixel is a second value. The least significant bit value of the correction value of the adjacent pixel.

In some embodiments, the first adjacent pixel located at the fifth position (x, y-1) is the same pixel as the second adjacent pixel located at the fifth position (x, y-1), and is located at the sixth position ( The first adjacent pixel of x+1, y-1) is the same pixel as the second adjacent pixel located at the sixth position (x+1, y-1).

The above described features and advantages of the present invention will be more apparent from the following description.

100‧‧‧Image processing device

110‧‧‧Input value receiving unit

120‧‧‧correction value calculation unit

130‧‧‧Output value calculation unit

140‧‧‧Output value designation unit

150‧‧‧Error value calculation unit

E ₃ , E ₄ , E ₅ , E ₆ , E ₇ ‧ ‧ error values

I ₁ , I ₂ ‧‧‧ input values

P(x,y)‧‧‧first pixel

P(x+1,y)‧‧‧second pixel

P(x-1, y), P(x-1, y-1) ‧‧‧ first adjacent pixels

P(x+2, y-1)‧‧‧ second adjacent pixel

P(x,y-1), P(x+1,y-1)‧‧‧first adjacent pixel/second adjacent pixel

A better understanding of the aspects of the present disclosure can be obtained from the following detailed description taken in conjunction with the drawings. It should be noted that, according to industry standard practices, the features are not drawn to scale. In fact, in order to make the discussion clearer, the dimensions of each feature can be arbitrarily increased or decreased.

1 is a system block diagram of an image processing apparatus according to an embodiment of the present disclosure.

FIG. 2 is a schematic diagram of a pixel configuration according to an embodiment of the present disclosure.

FIG. 3 is a schematic diagram of diffusion of component error values of first adjacent pixels according to an embodiment of the present disclosure.

FIG. 4 is a schematic diagram of diffusion of component error values of second adjacent pixels according to an embodiment of the present disclosure.

Embodiments of the invention are discussed in detail below. However, it will be appreciated that the embodiments provide many applicable concepts that can be implemented in a wide variety of specific content. The examples discussed and disclosed are illustrative only and are not intended to limit the scope of the invention.

1 is a system block diagram of an image processing apparatus 100 in accordance with an embodiment of the present disclosure. 2 is a schematic diagram of a pixel configuration in accordance with an embodiment of the present disclosure. Here, the meaning represented by the symbol in FIG. 2 is first defined, for example, the pixel at the position (x, y) is represented by P(x, y), and so on. Referring to FIG. 1 and FIG. 2 together, the image processing apparatus 100 includes a step input value receiving unit 110, a correction value calculating unit 120, an output value calculating unit 130, an output value specifying unit 140, and an error value calculating unit 150. The first pixel P 110 receives an input value of an image receiving unit (x, y) of the input value I ₁ and the second pixel P (x + 1, y) of the input value I _2. For example, the input value I ₁ of the first pixel P(x, y) is the pixel data of the first pixel P(x, y) in the received image, and the second pixel P(x+1, y) The input value I ₂ is the pixel data of the second pixel P(x+1, y) in the received image.

Correction value calculation unit 120 according to a first adjacent pixel adjacent to the first pixel P P (x, y) of (x-1, y) component of the error value of EC _11, adjacent the first pixel P (x , y) a component error value EC ₁₂ of the first adjacent pixel P(x-1, y-1), and a first adjacent pixel P (x, y- adjacent to the first pixel P(x, y) 1) the error component EC _13, a first adjacent pixel adjacent to the first pixel P (x, y) of P (x + 1, y- 1) component of the first error value and the EC ₁₄ pixel P (x The input value I _{1 of} y) is used to calculate the correction value D _{1 of the} first pixel P(x, y).

In the embodiment of the present disclosure, the correction value D ₁ of the first pixel P(x, y) is the first adjacent pixel P(x-1, y), P(x-1, y-1), P ( I, y-1), P(x+1, y-1), multiple component error values EC ₁₁ , EC ₁₂ , EC ₁₃ , EC ₁₄ and I ₁ of the input value of the first pixel P(x, y) The sum is D ₁ =I ₁ +(EC ₁₁ +EC ₁₂ +EC ₁₃ +EC ₁₄ ).

The correction value calculation unit 120 is also configured to be adjacent to the second pixel according to the component error value EC ₂₁ of the second adjacent pixel P(x, y-1) adjacent to the second pixel P(x+1, y). a component error value EC ₂₂ of the second adjacent pixel P(x+1, y-1) of P(x+1, y), and a second adjacent neighboring second pixel P(x+1, y) Calculating the correction value of the second pixel P(x+1, y) by the component error value EC _{23 of the} pixel P(x+2, y-1) and the input value I ₂ of the second pixel P(x+1, y) D ₂ .

In the embodiment of the present disclosure, the correction value D ₂ of the second pixel P(x+1, y) is the second adjacent pixel P(x, y-1), P(x+1, y-1), The sum of the I ₂ of the input values of the multiple component error values EC ₂₁ , EC ₂₂ , EC ₂₃ and the second pixel P(x+1, y) of P(x+2, y-1), ie D ₂ = I ₂ + (EC ₂₁ +EC ₂₂ +EC ₂₃ ).

In the embodiment of the present disclosure, the component error value EC ₁₁ of the first adjacent pixel P(x-1, y) is the A/Z of the error value E ₃ of the first adjacent pixel P(x-1, y). , which is The component error value EC ₁₂ of the first adjacent pixel P(x-1, y-1) is B/Z of the error value E ₄ of the first adjacent pixel P(x-1, y-1), that is, The component error value EC ₁₃ of the first adjacent pixel P(x, y-1) is C/Z of the error value E ₅ of the first adjacent pixel P(x, y-1), that is, The component error value EC ₁₄ of the first adjacent pixel P(x+1, y-1) is the D/Z of the error value E ₆ of the first adjacent pixel P(x+1, y-1), that is, The component error value EC ₂₁ of the second adjacent pixel P(x, y-1) is the E/Z of the error value E ₅ of the second adjacent pixel P(x, y-1), that is, The component error value EC ₂₂ of the second adjacent pixel P(x+1, y-1) is the F/Z of the error value E ₆ of the second adjacent pixel P(x+1, y-1), that is, The component error value EC ₂₃ of the second adjacent pixel P(x+2, y-1) is the G/Z of the error value E ₇ of the second adjacent pixel P(x+2, y-1), that is, . Wherein A, B, C, D, E, F, G, and Z are positive integers, and A+B+C+D+E+F+G=2*Z.

FIG. 3 is a schematic diagram of diffusion of component error values of first adjacent pixels of a first pixel P(x, y) according to an embodiment of the present disclosure. In an embodiment of the present disclosure, A=7, B=3, C=6, D=1, and Z=16. in particular, ; ; ; . However, the disclosure is not limited thereto.

4 is a schematic diagram of diffusion of component error values of second adjacent pixels of a second pixel P(x+1, y) according to an embodiment of the present disclosure. In an embodiment of the present disclosure, E = F = G = 5, Z = 16. in particular, ; ; . However, the disclosure is not limited thereto.

The output value calculation unit 130 is configured to calculate an output value O _{1 of the} first pixel P(x, y) according to the correction value D ₁ of the first pixel P(x, y), and according to the second pixel P(x+1, The correction value D _{2 of} y) is used to calculate the output value O _{2 of the} second pixel P(x+1, y). In the embodiment of the present disclosure, the output value O ₁ of the first pixel P(x, y) is the most significant bit (MSB) value of the correction value D ₁ of the first pixel P(x, y). , ie, O ₁ =MSB(D ₁ ). In the embodiment of the present disclosure, the output value O ₂ of the second pixel P(x+1, y) is the most significant bit value of the correction value D ₂ of the second pixel P(x+1, y), that is, O ₂ = MSB (D ₂ ).

The error value calculation unit 150 is configured to calculate an error value E _{1 of the} first pixel P(x, y) according to the correction value D ₁ of the first pixel P(x, y), and according to the second pixel P(x+1, The correction value D _{2 of} y) is used to calculate the error value E _{2 of the} second pixel P(x+1, y). In the embodiment of the present disclosure, the error value E ₁ of the first pixel P(x, y) is the least significant bit (LSB) value of the correction value D ₁ of the first pixel P(x, y). , that is, E ₁ =LSB(D ₁ ). In the embodiment of the present disclosure, the error value E ₂ of the second pixel P(x+1, y) is the least significant bit value of the correction value D ₂ of the second pixel P(x+1, y), that is, E ₂ = LSB (D ₂ ). It is worth mentioning that the first pixel P (x, y) of the error value calculation unit 150 calculates the error value E ₁ and the second pixel P (x + 1, y) of the same error value E ₂ will be according to the above The way to spread to its neighboring pixels.

In the embodiment of the present disclosure, the error value E ₃ of the first adjacent pixel P(x-1, y) is the least significant bit of the correction value D ₃ of the first adjacent pixel P(x-1, y). The value, that is, E ₃ =LSB(D ₃ ); the error value E ₄ of the first adjacent pixel P(x-1, y-1) is the correction of the first adjacent pixel P(x-1, y-1) The least significant bit value of the value D ₄ , that is, E ₄ =LSB(D ₄ ); the error value E ₅ of the first adjacent pixel (or the second adjacent pixel) P(x, y-1) is the first phase The least significant bit value of the correction value D ₅ of the adjacent pixel P(x, y-1), that is, E ₅ = LSB (D ₅ ); the first adjacent pixel (or the second adjacent pixel) P (x+1) The error value E ₆ of y-1) is the least significant bit value of the correction value D ₆ of the first adjacent pixel P(x+1, y-1), that is, E ₆ =LSB(D ₆ ); The error value E ₇ of the adjacent pixel P(x+2, y-1) is the least significant bit value of the correction value D ₇ of the second adjacent pixel P(x+2, y-1), that is, E ₇ = LSB (D ₇ ). It is worth mentioning that, since the correction value calculation unit 120 calculates the correction value of the first pixel according to the plurality of component error values of the plurality of first adjacent pixels and the input value of the first pixel, for example, FIG. 1 In the system block diagram shown, the error value calculated by the error value calculation unit 150 is sent back to the correction value calculation unit 120 to calculate the correction value.

The output value specifying unit 140 is configured to specify the output value O _{1 of} the first pixel P(x, y) to the first pixel P(x, y), and specify the output value of the second pixel P(x+1, y). ₂ to the second pixel P(x+1, y). For example, the output value O ₁ of the first pixel P(x, y) is the pixel data of the first pixel P(x, y) in the output image, and the second pixel P(x+1, y) The output value O ₂ is the pixel data of the second pixel P(x+1, y) in the output image.

It is worth mentioning that in the embodiment of the present disclosure, when at least one of the first pixel P(x, y) and the second pixel P(x+1, y) is at the edge of the image, a In a case where at least one of the adjacent pixels and the second adjacent pixels are substantially absent, if in this case, the original pixel data of the most adjacent and substantially existing pixels is designated as the first phase that does not exist. Neighbor The original pixel data of the prime or second adjacent pixel. For example, when the first pixel P (x, y) is at the leftmost side of the image, the first adjacent pixel P(x-1, y) does not substantially exist, so the first adjacent pixel will be closest to P(x-1, y) and the original pixel data of the substantially existing pixel (ie, the first pixel P(x, y)) is designated as the original pixel data of the first adjacent pixel P(x-1, y), In this case, the rest of the situation (for example, the leftmost pixel of the second pixel P (x+1, y) position) is the same, and will not be described here.

It should be noted that for the first adjacent pixel of the embodiment of the present disclosure, horizontal diffusion and vertical diffusion are included, and for the second adjacent pixel of the disclosed embodiment, only the vertical direction is diffused. Specifically, for the image processing apparatus 100 of the embodiment of the present disclosure, only half of the pixels will diffuse their component error values horizontally and vertically, and the other half of the pixels will only have component errors. The value is diffused vertically. Therefore, compared with the conventional error diffusion processing method, the image processing apparatus 100 of the embodiment of the present disclosure has the following advantages: the hardware design cost can be reduced, the information processing amount of the output can be increased, the transmission timing can be accelerated, and the like.

In summary, the present disclosure proposes an image processing apparatus based on error diffusion and improved to improve the drawbacks of the conventional error diffusion processing method.

The features of several embodiments are summarized above, and those skilled in the art will be able to understand the aspects of the disclosure. Those skilled in the art will appreciate that the present disclosure can be readily utilized as a basis for designing or modifying other processes and structures, thereby achieving the same objectives and/or achieving the same advantages as the embodiments described herein. . Those skilled in the art should also understand that these equivalents are built. The spirit and scope of the present disclosure are not to be construed as being limited, and various changes, substitutions and changes can be made without departing from the spirit and scope of the disclosure.

Claims (9)

An image processing device includes: an input value receiving unit, configured to receive an input value of one of a first pixel and an input value of a second pixel, wherein the first pixel is adjacent to the second pixel, The first pixel and the second pixel are respectively located at a first position (x, y) and a second position (x+1, y); a correction value calculation unit is configured to be adjacent to the first Calculating a correction value of the first pixel by a plurality of component error values of the plurality of first adjacent pixels of the pixel and the input value of the first pixel, and according to a plurality of second phases adjacent to the second pixel Calculating a correction value of the second pixel by using a plurality of component error values of the adjacent pixels and the input value of the second pixel, wherein the first adjacent pixel systems are respectively located at a third position (x-1, y) a fourth position (x-1, y-1), a fifth position (x, y-1), and a sixth position (x+1, y-1), wherein the second adjacent pixel systems Located at the fifth position (x, y-1), the sixth position (x+1, y-1), and a seventh position (x+2, y-1), respectively; an output value calculation unit for According to the first pixel of the school And calculating an output value of the first pixel, and calculating an output value of the second pixel according to the correction value of the second pixel; and an output value specifying unit for specifying the output of the first pixel The value is given to the first pixel, and the output value of the second pixel is specified to the second pixel. The image processing device of claim 1, wherein the correction value of the first pixel is a sum of the component error values of the first adjacent pixels and the input value of the first pixel, wherein The correction value of the second pixel is a sum of the component error values of the second adjacent pixels and the input value of the second pixel. The image processing device of claim 1, wherein the output value of the first pixel is a most significant bit (MSB) value of the correction value of the first pixel, wherein the The output value of the two pixels is the most significant bit value of the correction value of the second pixel. The image processing device of claim 1, further comprising: an error value calculation unit, configured to calculate an error value of the first pixel according to the correction value of the first pixel, and according to the second The correction value of the pixel is used to calculate an error value of one of the second pixels. The image processing device of claim 4, wherein the error value of the first pixel is a least significant bit (LSB) value of the correction value of the first pixel, The error value of the second pixel is a least significant bit value of the correction value of the second pixel. The image processing device of claim 1, wherein the component error value of the first adjacent pixel located at the third position (x-1, y) is located at the third position (x-1, y) A/Z of an error value of one of the first neighboring pixels; wherein the component error value of the first neighboring pixel located at the fourth position (x-1, y-1) is at the fourth B/Z of an error value of one of the first adjacent pixels of position (x-1, y-1); wherein the component error of the first adjacent pixel located at the fifth position (x, y-1) a value of C/Z of an error value of one of the first neighboring pixels located at the fifth position (x, y-1); wherein the first phase located at the sixth position (x+1, y-1) The component error value of the adjacent pixel is D/Z of one of the first adjacent pixels located at the sixth position (x+1, y-1); wherein the fifth position (x, y-1) The component error value of the second adjacent pixel is E/Z of an error value of one of the second neighboring pixels located at the fifth position (x, y-1); wherein the sixth position (x) The component error value of the second adjacent pixel of +1, y-1) is one of the second adjacent pixels located at the sixth position (x+1, y-1) F/Z of the error value; wherein the second adjacent pixel is located at the seventh position (x+2, y-1) The component error value is G/Z of an error value of one of the second neighboring pixels located at the seventh position (x+2, y-1); wherein A, B, C, D, E, F, G, Z is a positive integer, and A+B+C+D+E+F+G=2*Z. The image processing device according to claim 6, wherein A=7, B=3, C=6, D=1, and E=F=G=5. The image processing device of claim 6, wherein the error value of the first adjacent pixel is a least significant bit (LSB) value of the correction value of the first adjacent pixel. The error value of the second adjacent pixel is a least significant bit value of the correction value of the second adjacent pixel. The image processing device of claim 1, wherein the first adjacent pixel located at the fifth position (x, y-1) and the first portion located at the fifth position (x, y-1) Two adjacent pixels are the same pixel, wherein the first adjacent pixel located at the sixth position (x+1, y-1) and the second phase located at the sixth position (x+1, y-1) The neighboring pixels are the same pixel.