TWI655546B - Reset circuit of solid state drive and reset method thereof - Google Patents

Abstract

A reset circuit for a solid state storage device includes: a control circuit, a flash memory array and a buffer. The control circuit includes a physical layer circuit and a first input port. The first output port is connected to a first reset end of a host. The flash memory array is coupled to the buffer to the control circuit. When the first reset end of the host acts as a reset signal, the level of the first output port is changed, and then, after a delay time, the level of a second reset end of the physical layer circuit Changed and reset the physical layer circuit.

Description

Reset circuit of solid state storage device and reset method thereof

The present invention relates to a solid state storage device, and more particularly to a reset circuit for a solid state storage device and a reset method thereof.

As is well known, the busbars in the early computer systems include an Advanced Graphic Port (AGP) bus and a Peripheral Component Interconnect (PCI) bus. The AGP bus is mainly connected to a graphic card, and the PCI bus is connected to other peripheral devices, such as an internet card.

Since the Fast Peripheral Component Interconnect (PCI Express) confluence has a faster data transfer rate, it has replaced the traditional AGP bus and PCI bus. That is to say, in today's computer systems, all devices are connected to the PCIe bus.

For example, in today's computer systems, a graphics card and a solid state drive (SSD) are connected to the PCIe bus.

Please refer to FIG. 1 , which is a schematic diagram of the connection of a solid state storage device in a conventional computer system. The solid state storage device 100 is connected to the host 130 using a PCIe bus bar 120.

Furthermore, the solid state storage device 100 includes a control circuit 110 and a flash array 105. The control circuit 110 is connected to the flash memory array 105.

The control circuit 110 includes a PCIe physical layer circuit (PHY circuit) 112, and the host 130 includes a PCIe physical layer circuit 132. The PCIe bus bar 120 is connected to the PCIe physical layer circuit 112 of the control circuit 110 and the PCIe physical layer circuit 132 of the host 130.

Therefore, the host 130 can utilize the PCIe bus bar 120 to issue an access command to the control circuit 110 of the solid state storage device 100. For example, the control circuit 110 stores the write data provided by the host 130 into the flash memory array 105 according to the write command. Alternatively, the control circuit 110 passes the read data in the flash memory array 105 to the host 130 in accordance with the read command.

According to the specifications of the PCIe bus bar 120, a plurality of control signals of the PCIe bus bar 120 include a reset signal. As shown in FIG. 1, the PCIe physical layer circuit 132 of the host 130 has a reset terminal RESET1# for activating the reset signal. Moreover, the reset terminal RESET1# of the PCIe physical layer circuit 132 of the host 130 is directly connected to the reset terminal RESET2# of the PCIe physical layer circuit 112 of the control circuit 110 through a physical wire. Therefore, the PCIe physical layer circuit 132 of the host 130 can be at any time. The signal is reset by the reset terminal RESET1#, and the PCIe physical layer circuit 112 of the control circuit 110 is directly reset.

According to the specifications of the PCIe bus 120, the reset signal of the PCIe bus 120 has the highest priority and needs to be prioritized. In other words, once the reset terminal RESET2# of the PCIe physical layer circuit 112 of the control circuit 110 receives the reset signal, the PCIe physical layer circuit 112 of the control circuit 110 must be immediately reset. Since the PCIe physical layer circuit 132 of the host 130 can actuate the reset signal at any time, if the PCIe physical layer circuit 112 of the control circuit 110 is performing the process of accessing the instruction and the host 130 acts as a reset signal, the control circuit 110 The PCIe physical layer circuit 112 is forced to reset, which may cause data corruption that the control circuit 110 is processing and cause the solid state storage device 100 to be unrecoverable.

The present invention relates to a reset circuit for a solid state storage device. The solid state storage device is connected to a host via a bus bar. The host has a first reset terminal, and the reset circuit of the solid state storage device includes: a control circuit. a physical layer circuit corresponding to the bus bar and a first input port, the physical layer circuit having a second reset end, wherein the first reset end of the host is connected to the first output port, wherein The physical layer circuit resets the physical layer circuit according to the level state of the second reset terminal; a flash memory array is connected to the control circuit; and a buffer is connected to the control circuit; wherein, when the host The first reset end action is reset When the signal is received, the first input port is changed from a first level to a second level, and then, after a delay time, the second reset end of the physical layer circuit is changed by a third level. It is a fourth level and resets the physical layer circuit.

The invention relates to a reset method for a reset circuit of a solid-state storage device, which is connected to a host via a bus bar, the host has a first reset end, and the reset circuit of the solid-state storage device The method includes a control circuit, including a physical layer circuit corresponding to the bus bar and a first input port, the physical layer circuit has a second reset end, the reset method includes: determining whether the first output port is Changing a first level to a second level, wherein the first output port is connected to the first reset end of the host; and a delay after the first output port is changed to the second level Time, the second reset end of the physical layer circuit is changed from a third level to a fourth level; and resetting the physical layer circuit; wherein, when determining that the first output port is changed to the At the second level, the control circuit temporarily refuses to receive an instruction issued by the host, and temporarily stores the data processed by the physical layer circuit to a buffer.

In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

100, 200, 300‧‧‧ solid storage devices

105, 205, 305‧‧‧ flash memory array

110, 210, 310‧‧‧ control circuit

120, 220, 320‧‧‧ PCIe bus

130‧‧‧Host

132, 112, 212, 312‧‧‧ PCIe physical layer circuit

208‧‧‧buffer

330‧‧‧Delay circuit

Figure 1 is a schematic diagram of the connection of a solid state storage device in a conventional computer system.

2A and 2B are diagrams showing a first embodiment of a connection diagram of a solid state storage device in a computer system of the present invention and related signal diagrams.

Figure 3 is a second embodiment of a connection diagram of a solid state storage device in a computer system of the present invention.

Please refer to FIG. 2A and FIG. 2B , which are diagrams showing a first embodiment of a connection diagram of a solid state storage device in a computer system of the present invention and related signal diagrams. The host 130 sends an access command to the solid-state storage device 200 by using the PCIe bus bar 220. The detailed operation principle is not described herein. In addition, the structure of the host 130 is the same as that of FIG. 1, and details are not described herein again.

The solid state storage device 200 includes a control circuit 210, a flash memory array 205, and a buffer 208. Control circuit 210 is coupled to flash memory array 205 and buffer 208. The buffer 208 can be a dynamic random access memory (DRAM).

The control circuit 210 includes a PCIe physical layer circuit (PHY circuit) 212, and the PCIe physical layer circuit 212 includes a reset terminal RESET2#. Furthermore, the control circuit 210 further includes two I/O ports, such as a general purpose I/O port (GPIO) GPIO1 and GPIO2.

According to the first embodiment of the present invention, the general-purpose input port GPIO1 of the control circuit 210 is directly connected to the reset terminal RESET1# of the PCIe physical layer circuit 132 of the host 130 via a physical wire. The general purpose output of the control circuit 210 is the reset terminal of the PCIe physical layer circuit 132 of the GPIO1 and the host 130. RESET1# has the same level. Furthermore, the general-purpose input port GPIO2 of the control circuit 210 is directly connected to the reset terminal RESET2# of the PCIe physical layer circuit 212 of the control circuit 210 through a signal line. The general-purpose output port GPIO2 of the control circuit 210 has the same level as the reset terminal RESET2# of the PCIe physical layer circuit 212 of the control circuit 210.

When the host 130 performs a general operation on the solid-state storage device 200, for example, when performing a data access operation, the general-purpose output of the control circuit 210 is at the same level as the reset terminal RESET1# of the PCIe physical layer circuit 132 of the host 130. For example, the first level; the general-purpose output port GPIO2 of the control circuit 210 and the reset terminal RESET2# of the PCIe physical layer circuit 212 of the control circuit 210 are at the same level, for example, the second level. The first level and the second level may be the same level or different levels.

According to the embodiment of the present invention, when the PCIe physical layer circuit of the host 130 is reset by the reset terminal RESET1#, the general-purpose output port GPIO1 of the control circuit 210 is changed to the third level, wherein the third level is different from the third level. First level. Then, after a delay time, the reset terminal RESET2# of the PCIe physical layer circuit 212 of the control circuit 210 is changed to a fourth level, wherein the fourth level is different from the second level.

The embodiments of the present invention are specifically described below by taking the first level and the second level as high standards as an example.

When the host 130 wants to reset the PCIe physical layer circuit 212 of the control circuit 210, the PCIe physical layer circuit 132 of the host 130 passes the reset end. RESET1# action reset signal. Specifically, the reset terminal RESET1# of the PCIe physical layer circuit 132 of the host 130 is changed from a high level (first level) to a low level (third level), so that the general output of the control circuit 210 is input to the 埠 GPIO1. Changed from high level (first level) to low level (third level). The control circuit 210 determines whether or not the reset signal is received based on the level of the general-purpose input port 埠 GPIO1.

Next, the control circuit 210 operates a control signal on the general-purpose output port GPIO2 after a delay time. Specifically, after a delay time, the control circuit 210 changes the general-purpose output port GPIO2 from a high level (second level) to a low level (fourth level), thereby controlling the circuit 210. The reset terminal RESET2# of the PCIe physical layer circuit 212 is changed from a high level (second level) to a low level (fourth level). The PCIe physical layer circuit 212 resets the PCIe physical layer circuit 212 of the control circuit 210 according to the level state of the reset terminal RESET2#.

In addition, when the general-purpose input/output GPIO1 of the control circuit 210 receives the reset signal, that is, the general-purpose output port GPIO1 of the control circuit 210 is changed from the high level (first level) to the low level (third level). At this time, the control circuit 210 immediately performs a data security operation. For example, control circuit 210 temporarily rejects instructions from host 130. Moreover, the control circuit 210 temporarily stores the data being processed by the PCIe physical layer circuit 212 in the buffer 208.

As shown in FIG. 2B, it is assumed that the host 130 is to reset the PCIe physical layer circuit 212 of the control circuit 210 at the time point ta. Before the time point ta, the host 130 and the solid state storage device 200 are in a normal operation, at this time, the host 130 The reset terminal RESET1# of the PCIe physical layer circuit 132 and the general-purpose output port GPIO2 of the control circuit 210 are located at a high level. At the same time, the general-purpose output port GPIO1 of the control circuit 210 connected thereto and the reset terminal RESET2# of the PCIe physical layer circuit 212 of the control circuit 210 are also located at a high level.

When the host 130 moves the reset signal through the reset terminal RESET1# at the time point ta, that is, the host 130 changes the reset terminal RESET1# of the PCIe physical layer circuit 132 of the host 130 from the high level to the low level at the time point ta. The general-purpose output port GPIO1 of the control circuit 210 connected thereto is also changed from the high level to the low level. At this time, the control circuit 210 determines that the reset signal is received based on the level state of the general-purpose output port GPIO1, and performs a data security operation.

Then, after a delay time Td, at time tb, the control circuit 210 changes the general-purpose output port GPIO2 from the high level to the low level, so that the PCIe physical layer circuit 212 of the control circuit 210 connected thereto is also high. The level becomes a low level. At this time, the PCIe physical layer circuit 212 resets the PCIe physical layer circuit 212 according to the level state of the reset terminal RESET2#.

Since the control circuit 210 has performed the data security action within the delay time Td. When the PCIe physical layer 212 is reset and operates again, the previously processed data can be retrieved from the buffer 208 and processed, so that the solid state storage device 200 will not have the problem of data corruption.

Please refer to FIG. 3, which illustrates a second embodiment of a connection diagram of a solid state storage device in a computer system of the present invention. The host 130 can use the PCIe bus 320 to issue an access command to the solid-state storage device 300, and the detailed operation thereof The principle is not repeated here. In addition, the structure of the host 130 is the same as that of FIG. 1, and details are not described herein again.

The solid state storage device 300 includes a control circuit 310, a flash memory array 305, a buffer 308, and a delay circuit 330. Control circuit 310 is coupled to flash memory array 305 and buffer 308. The buffer 308 can be a dynamic random access memory (DRAM).

The control circuit 310 includes a PCIe physical layer circuit 312, and the PCIe physical layer circuit 312 includes a reset terminal RESET2#. Moreover, the control circuit 310 further includes an input port, such as a general-purpose input port 埠 GPIO1.

According to the second embodiment of the present invention, the general-purpose input port GPIO1 of the control circuit 310 is directly connected to the reset terminal RESET1# of the PCIe physical layer circuit 132 of the host 130 via a physical wire. Furthermore, the delay circuit 330 is connected to the reset terminal RESET2# of the PCIe physical layer circuit 212 of the control circuit 210 and the reset terminal RESET1# of the PCIe physical layer circuit 132 of the host 13.

In this embodiment, when the host 130 performs a general operation on the solid-state storage device 300, for example, when performing a data access operation, the general-purpose output of the control circuit 310 enters the reset terminal RESET1 of the PCIe physical layer circuit 132 of the GPIO1 and the host 130. # is at the same level, for example, the first level; the reset terminal RESET2# of the PCIe physical layer circuit 312 of the control circuit 310 is at the second level. The first level and the second level may be the same level or different levels.

As with the first embodiment, when the PCIe physical layer circuit of the host 130 is reset by the reset terminal RESET1#, the general-purpose output port GPIO1 of the control circuit 310 is changed to the third level, wherein the third level is different from the third level. First level. Then, after a delay time, the reset terminal RESET2# of the PCIe physical layer circuit 312 of the control circuit 310 is changed to a fourth level, wherein the fourth level is different from the second level.

The embodiments of the present invention are specifically described below by taking the first level and the second level as high standards as an example.

When the host 130 wants to reset the PCIe physical layer circuit 312 of the control circuit 310, the PCIe physical layer circuit 132 of the host 130 acts to reset the signal through the reset terminal RESET1#. Specifically, the reset terminal RESET1# of the PCIe physical layer circuit 132 of the host 130 is changed from a high level (first level) to a low level (third level), so that the general output of the control circuit 310 is input to the 埠 GPIO1. Changed from high level (first level) to low level (third level). The control circuit 210 determines whether or not the reset signal is received based on the state of the general-purpose input port 埠 GPIO1, and performs a data security operation accordingly.

In addition, when the PCIe physical layer circuit 132 of the host 130 acts to reset the signal through the reset terminal RESET1#, the delay circuit 330 also receives the reset signal. Then, the delay circuit 330 changes the reset terminal RESET2# of the PCIe physical layer circuit 312 of the control circuit 310 from the high level (second level) to the low level after delaying a delay time (first) Four levels). PCIe real The bulk layer circuit 312 resets the PCIe physical layer circuit 312 of the control circuit 310 according to the level state of the reset terminal RESET2#.

Similarly, when the general-purpose input/output GPIO1 of the control circuit 310 receives the reset signal, the general-purpose output of the control circuit 210 is changed from the high level (first level) to the low level (third level). When the control circuit 210 performs the data security operation immediately. For example, control circuit 310 temporarily rejects instructions from host 130. Moreover, the control circuit 310 temporarily stores the data being processed by the PCIe physical layer circuit 312 in the buffer 308.

Since the control circuit 310 has performed a data security action within the delay time. When the PCIe physical layer 312 is reset and operates again, the previously processed data can be retrieved from the buffer 308 and processing continues, so that the solid state storage device 300 will not have the problem of data corruption.

According to the specification of the PCIe specification, at the time of the action reset signal, at least the level of the reset terminal RESET1# of the PCIe physical layer circuit 132 of the host 130 needs to be changed for a period of Ta, for example, 100 μs. According to an embodiment of the invention, the delay time can be set to Ta/2, that is, 50 μs. Thus, when the control circuit operates at a speed of 500 MHz, the control circuit has sufficient time for data preservation to ensure that the processed data is safely stored in the buffer.

In the embodiment of the present invention, after changing the level of the reset end RESET1# of the PCIe physical layer circuit 132 of the host 130 for a period of Ta, the reset end RESET1# of the PCIe physical layer circuit 132 of the host 130 can be restored to the original Level, which is the level of general operation. And the general output of the control circuits 210, 310 The reset terminal RESET2# of the GPIO1 and the PCIe physical layer circuits 212, 312 of the control circuits 210, 310 can also be restored to the original level, that is, the level at the time of normal operation.

As can be seen from the above description, the present invention provides a reset circuit and a reset method for a solid state storage device. When the host sends a reset signal to reset the physical layer circuit, the control circuit in the solid state storage device determines that the reset signal is received according to the level state of the general-purpose output port, and performs data preservation action correspondingly. Then, after a delay time, the level of the reset terminal of the physical layer circuit of the control circuit is changed to reset the physical layer circuit, so that the physical layer circuit is reset. In this way, the problem of data corruption in the solid state storage device can be prevented. Furthermore, the timing change timing of the reset terminal of the physical layer circuit of the control circuit can be directly controlled by the control circuit or controlled by the delay circuit.

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

Claims (10)

A reset circuit of a solid state storage device, the solid state storage device being connected to a host via a bus bar, the host having a first reset end, the reset circuit of the solid state storage device comprising: a control circuit, including a corresponding sink a physical layer circuit having a second reset end, wherein the physical layer circuit resets the physical layer circuit according to a level state of the second reset end, wherein the control circuit further includes a first An output port is independent of the physical layer circuit, and the first reset end of the host is connected to the first output port; a flash memory array is connected to the control circuit; And a buffer connected to the control circuit; wherein, when the first reset end of the host acts as a reset signal, the physical layer circuit is reset, and the first output is controlled by a first The bit is changed to a second level. Then, after a delay time, the second reset end of the physical layer circuit is changed from a third level to a fourth level, and the physical layer circuit is reset. . The reset circuit of the solid state storage device of claim 1, wherein the control circuit further comprises a second input port connected to the second reset end of the physical layer circuit. After the delay time, the control circuit changes the second reset end of the physical layer circuit from the third level to the fourth level through the second output port. The reset circuit of the solid state storage device of claim 2, wherein the first input port and the second output port are a first general output port and a second common input port. The reset circuit of the solid state storage device of claim 1, further comprising a delay circuit connected to the first reset end of the host and the second reset end of the physical layer circuit, wherein When the first reset end of the host acts on the reset signal, the delay circuit delays the delay time, and the second reset end of the physical layer circuit is changed from the third level to the fourth standard Bit. The reset circuit of the solid state storage device of claim 1, wherein the bus bar is a PCIe bus bar, and the physical layer circuit is a PCIe physical layer circuit. The reset circuit of the solid state storage device of claim 1, wherein the control circuit performs a control when the first output port of the control circuit is changed from the first level to the second level. Data preservation action. The reset circuit of the solid state storage device of claim 6, wherein the data security action comprises the control circuit temporarily refusing to receive an instruction issued by the host, and temporarily storing the data processed by the physical layer circuit to the buffer. Device. The reset circuit of the solid state storage device of claim 6, wherein the control circuit determines whether the reset signal is received according to the level state of the first input port. A reset method for a reset circuit of a solid-state storage device, the solid-state storage device being connected to a host via a bus, the host having a first reset end, the reset circuit of the solid-state storage device including a control circuit a physical layer circuit corresponding to the bus bar, the physical layer circuit having a second reset end, wherein the control circuit further includes a first output port, the first output port is independent of the physical layer circuit The resetting method includes: determining whether the first output port is changed from a first level to a second level, wherein the first reset end of the host is connected to the first output port, wherein the resetting method comprises: determining whether the first output port is changed from a first level to a second level, wherein The first output port is connected to the first reset end of the host; the second reset end of the physical layer circuit is a delay time after the first output port is changed to the second level Changing from the third level to a fourth level; and resetting the physical layer circuit; wherein, when it is determined that the first output port is changed to the second level, the control circuit temporarily refuses to receive the host Issued the order and the entity Data processing circuit is temporarily stored to a buffer. The method for resetting a reset circuit for a solid-state storage device according to claim 9, wherein the bus bar is a PCIe bus bar, and the physical layer circuit is the PCIe physical layer circuit.