TWI651921B - System for improving EMI of flyback switching power supplies - Google Patents

Abstract

The present invention relates to a system for improving the EMI of a flyback switching power supply. The system includes: a logic circuit configured to generate a latch signal based on the first signal; an oscillator (OSC) configured to generate and transmit the first signal to the logic circuit, wherein the feedback proportional voltage-dividing resistor is configured according to the system Output voltage to generate a feedback signal; a jitter generator configured to generate a second signal and transmit the second signal to a comparator; a comparator to generate a comparison signal based on the feedback signal and the second signal; an RS latch based on the comparison Signals and latch signals to generate a third signal gate driver; the gate driver is configured to receive a third signal and generate a driving signal based on the third signal to control the on and off of a power transistor connected to the gate driver; And a jitter controller that receives a reference signal and generates a control signal based on the reference signal, wherein the first signal is generated by the oscillator based on the control signal.

Description

System for improving EMI of flyback switching power supply

The present invention relates to a switching power supply, and more particularly, to a system for improving electromagnetic interference (EMI) of a flyback switching power supply.

In switching power supplies, the general switching frequency ranges from tens of kHz to hundreds of kHz. Parasitic capacitance and inductance exist on the system board, and EMI is inevitable. In order to avoid severe interference with other electrical appliances, the EMI generated by the switching power supply needs to be strictly limited.

In order to reduce the size of the switching power supply, the switching frequency needs to be increased, which will cause EMI problems and increase switching losses. Using Quasi-Resonant (QR) technology, the parasitic capacitance Cf of the drain side of the power MOSFET and the leakage inductance Lm of the transformer are used to resonate to achieve valley conduction, thereby improving system efficiency. Compared with the traditional fixed-frequency hardware switching system, the QR system can significantly improve radiated EMI.

However, traditional fixed-frequency systems can easily achieve switching frequency jitter, and conducting EMI can disperse the originally concentrated spectral energy through switching frequency jitter. Because the switching frequency of the QR system is determined by the system and the load, that is, when the output load is constant at a certain input voltage, the switching frequency of the system is basically constant, so that the conduction EMI is more concentrated at low frequencies, resulting in conduction EMI Difficult to resolve.

FIG. 1 is a schematic block diagram showing a flyback switching power supply system, and a conventional fixed-frequency PWM controller 100. The primary-side fixed-frequency PWM controller 100 (shown as a dotted line) may be externally connected with a current source (for example, an AC current source). The PWM controller 100 includes an oscillator 110, a feedback proportional voltage dividing resistor 120, a PWM comparator 130, an RS latch 140, and a gate driver 150. The switching frequency is completely controlled by the oscillator 110. The connection relationship is shown in Figure 1. The PWM controller 100 external and feedback isolator The output phase connection system of the device implements a transformer including a primary winding and a secondary winding to isolate the AC input voltage on the primary side from the output voltage on the secondary side. The feedback isolation element processes the information about the output voltage and generates a feedback signal, and controls the energy transmission by controlling the PWM signal, thereby achieving closed-loop control of the system. For example, the isolated feedback element may include an error amplifier, a compensation network, and an optocoupler (not shown).

FIG. 2 is a diagram showing a dither signal of the fixed-frequency PWM controller shown in FIG. 1. To improve EMI, a frequency dithering function is usually added to the oscillator 110. In the frequency dithering mode of the oscillator 110, as shown in FIG. 2, the switching frequency climbs from a low slope to high, and then decreases from a high slope to low. In addition, a pseudo-random generator can also be used, which has the same effect on EMI improvement. Generally, the frequency jitter amplitude can be controlled within a certain range, which can ensure that the EMI improvement does not cause noise problems because the frequency change amplitude is too large. For example, for a fixed frequency system of 60K, ± 4% jitter range can be adopted, that is, the system switching frequency is 60K ± 2.4K, and the frequency range of the n-th harmonic energy distribution is ± 2.4nK, compared with the total harmonic energy of the fixed-frequency system. It is unchanged, but the energy amplitude at each harmonic frequency point is significantly reduced, thereby improving the conduction EMI.

FIG. 3 is a diagram showing the relationship between the switching frequency Fs, the gate voltage Vcs, and the feedback signal FB of the fixed-frequency PWM controller shown in FIG. 1. In the traditional fixed-frequency PWM flyback system, the switching frequency is not controlled by FB when the system is under heavy load. The frequency can be changed periodically by superimposing a fixed-cycle jitter signal on the OSC (Oscillator, Oscillator). Usually the period will be much larger than two. Bandwidth on the secondary side. However, in the frequency reduction area, the secondary-side error amplifier feedback signal FB will control the OSC to achieve light-load frequency reduction. In this way, the original OSC periodic jitter amplitude will be controlled by the FB feedback. Actually, the frequency jitter on the system generally uses the periodic climbing method. It is easy to be affected by the modulation of the feedback signal FB, and the final jitter amplitude will be much smaller than the design value. As a result, the EMI conduction deviation will be caused by the small switching frequency difference in the frequency reduction area.

FIG. 4 is a diagram showing the relationship between the switching frequency Fs, the feedback signal FB, and time in the reduced frequency band of the fixed-frequency PWM controller shown in FIG. 1. As shown in Figure 4, in the down-frequency region, Fs_ jitter is the frequency variation (open loop, FB remains unchanged) of the OSC frequency during the jitter period in the down-frequency region. But in the actual system, the feedback signal FB of the secondary error amplifier will Control the OSC frequency inverse modulation, so that the original design OSC periodic jitter amplitude will be controlled by FB feedback, and the final system switching frequency Fs will be much smaller than the OSC jitter amplitude.

Therefore, a system for improving the EMI of a flyback switching power supply is needed.

In view of the above problems, the present invention proposes a system for improving the EMI of a flyback switching power supply. Therefore, in the system frequency reduction, EMI is improved by adopting a switching frequency jittering method.

According to an aspect of the present disclosure, there is provided a system for improving electromagnetic interference EMI of a flyback switching power supply, comprising: a logic circuit configured to generate a latch signal based at least in part on a first signal; an oscillator OSC, The input of the OSC is connected to the feedback proportional voltage dividing resistor and the output is connected to the logic circuit, and is configured to generate and transmit the first signal to the logic circuit, wherein the feedback proportional voltage dividing resistor is configured to generate a feedback signal according to the output voltage of the system ; Jitter generator, the jitter generator is configured to generate a second signal and transmit the second signal to the comparator; the comparator, the non-inverting input of the comparator is connected to the feedback proportional voltage dividing resistor, and the inverting input is connected to the jitter generating element, The output is connected to the R terminal of the RS latch, thereby generating a comparison signal based on the feedback signal and the second signal; RS latch, the R terminal of the RS latch is connected to the output of the comparator, and the S terminal is connected to the output of the logic circuit And the Q terminal is connected to the input of the gate driver to generate a third signal gate driver based on the comparison signal and the latch signal The gate driver is configured to receive a third signal and generate a driving signal based at least in part on the third signal to control the on and off of the power transistor connected to the gate driver; and a jitter controller, the jitter controller is configured A control signal is generated for receiving a reference signal and based at least in part on the reference signal, wherein the first signal is generated by the OSC based on the control signal.

According to another aspect of the present disclosure, a power converter including an undervoltage and an overvoltage protection system according to the present disclosure is provided.

The system according to the embodiment of the present application provides an improvement in EMI for a flyback switching power supply. Depending on the embodiment, one or more benefits may also be obtained. These benefits, as well as various additional objects, features, and advantages of the present invention can be fully understood with reference to the following detailed description and accompanying drawings.

R1, R2‧‧‧ resistors

Q1‧‧‧Power Transistor

R _sense ‧‧‧ resistance

CS‧‧‧Terminal

Fs‧‧‧Switching frequency

Vcs‧‧‧Gate voltage

Fs_fix‧‧‧ fixed value

V _CS _ Jitter ‧‧‧ Periodically changing signal

dem‧‧‧winding

OSC‧‧‧Oscillator

Va‧‧‧ Foldback mode feedback signal

Fs_jitter‧‧‧ Frequency jitter change amplitude

Vcs_md1‧‧‧Median gate voltage 1

Vcs_md2‧‧‧Gate of intermediate gate voltage 2

Vin‧‧‧System input voltage

Vo‧‧‧ system output voltage

Vcs_max‧‧‧Maximum gate voltage

Vcs_min‧‧‧Minimum gate voltage

110, 510, 810, 1010‧‧‧ oscillator

120, 520, 820, 1020‧‧‧‧ feedback proportional voltage dividing resistor

130, 530, 830, 1030‧‧‧PWM comparator

140, 540, 840, 1040‧‧‧RS latches

150, 550, 850, 1050‧‧‧Gate drivers

Fs_max, Fs_max1‧‧‧System maximum frequency

Fs_min, Fs_min1‧‧‧System minimum frequency

T, t, T0, T1, T2

Clk_ref‧‧‧ Internal reference clock

860, 1060‧‧‧Logic circuit

870, 1070‧‧‧ Demagnetization sensing element

1080‧‧‧ Jitter Control Element

1090‧‧‧Jitter generating element

Ip‧‧‧ primary coil inductor current

Fs_Jitter‧‧‧Frequency change

LPF‧‧‧Low-pass filter

gate‧‧‧Gate drive output terminal

100, 500‧‧‧ fixed frequency PWM controller

800, 1000‧‧‧ Quasi-Resonant (QR) Controller

FB‧‧‧Secondary error amplifier feedback signal

Vfb_burst‧‧‧Burst mode feedback signal threshold voltage

Vfb_1‧‧‧Threshold voltage of feedback signal 1

Vfb_2‧‧‧Feedback signal threshold voltage 2

Vfb_3‧‧‧Threshold voltage of feedback signal 3

FB_max1‧‧‧Maximum frequency jitter cycle feedback signal 1

FB_min1‧‧‧Minimum frequency feedback signal 1

Fs_va‧‧‧System switching frequency when the feedback signal is va

Ip_max1‧‧‧Maximum primary coil inductor current 1

Ip_min1‧‧‧Minimum primary coil inductor current 1

Hereinafter, the features, advantages, and technical effects of the exemplary embodiments of the present invention will be described with reference to the accompanying drawings. Similar reference numerals in the drawings represent similar elements, wherein: FIG. 1 shows a conventional fixed-frequency PWM Simplified block diagram of the controller.

FIG. 2 is a diagram showing a dither signal of the fixed-frequency PWM controller shown in FIG. 1.

FIG. 3 is a diagram showing the relationship between the switching frequency Fs, the gate voltage Vcs, and the feedback signal FB of the fixed-frequency PWM controller shown in FIG. 1.

FIG. 4 is a diagram showing the relationship between the switching frequency Fs, the feedback signal FB, and time in the reduced frequency band of the fixed-frequency PWM controller shown in FIG. 1.

FIG. 5 is a simplified block diagram illustrating a fixed-frequency PWM controller according to an embodiment of the present disclosure.

FIG. 6 is a diagram showing the corresponding relationship between the switching frequency Fs and the primary VCS value of the flyback power system and the feedback signal FB.

FIG. 7 is a diagram showing the Fs jitter and Ip jitter of the flyback power system in the frequency reduction region over time.

FIG. 8 is a simplified block diagram illustrating a quasi-resonant QR controller according to an embodiment of the present disclosure.

FIG. 9 is a diagram showing the relationship between the switching frequency Fs, the gate voltage Vcs, and the feedback signal FB of the QR controller.

FIG. 10 shows a schematic block diagram of an implementation manner of jitter control of a QR system according to an embodiment of the present disclosure.

FIG. 11 shows a schematic block diagram of another implementation of jitter control of a QR system according to an embodiment of the present disclosure.

FIG. 12 shows a schematic block diagram of still another implementation manner of jitter control of a QR system according to an embodiment of the present disclosure.

Features and exemplary embodiments of various aspects of the invention will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it is obvious to a person skilled in the art that the present invention can be implemented without the need for some of these specific details. The following description of the embodiments is merely for providing a better understanding of the present invention by showing examples of the present invention. The invention is by no means limited to any specific configuration and algorithm proposed below, but covers any modification, replacement and improvement of elements, components and algorithms without departing from the spirit of the invention. In the drawings and the following description, well-known structures and techniques are not shown in order to avoid unnecessarily obscuring the present invention.

FIG. 5 shows a simplified block diagram of a fixed-frequency PWM controller according to an embodiment of the present disclosure. This figure is only an example, and it should not unduly limit the scope of patent applications. Those of ordinary skill in the art should understand many variations, substitutions, and modifications.

The fixed-frequency PWM controller 500 (shown as a dotted line) includes an oscillator (OSC) 510, a feedback proportional voltage dividing resistor 520, a PWM comparator 530, an RS latch 540, and a gate driver 550. FIG. 5 also shows a current source, a feedback isolation element, and the like to which the PWM controller 500 is connected. The PWM controller is connected to external devices such as primary windings, secondary windings, electromagnetic interference (EMI) filters, rectifier bridges, isolated feedback components, and the like. The isolated feedback element may include, for example, a plurality of resistors, capacitors, three-terminal regulators, and optocouplers.

As shown in FIG. 5, an alternating current (Alternate Current, AC) input is processed by an EMI filter, and the rectifier bridge provides an input voltage for operation of the PWM controller 500. A transformer including a primary winding and a secondary winding isolates the primary and secondary sides of the PWM controller 500. Information related to the output voltage on the secondary side can be extracted by a feedback proportional voltage dividing resistor 520 including resistors R1 and R2.

The isolated feedback element generates a feedback signal based on information associated with the output voltage. The controller's information receives the feedback signal and generates a drive signal to turn the switch on and off to regulate the output voltage. If the power switch is closed (eg, turned on), energy is stored in a transformer including a primary winding and a secondary winding. A closed power switch allows current to flow through the winding once. The current is sensed by a resistor and converted into a current sensing signal (for example, V _CS ) through a terminal (for example, terminal _CS ). Subsequently, if the power switch is turned off (eg, turned off), the stored energy is released to the output and the system enters a demagnetization process.

In one example, the power transistor is a bipolar junction transistor. In another example, the power transistor is a field effect transistor (eg, a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET)). In yet another example, the power transistor is an Insulated Gate Bipolar Transistor (IGBT). The collector of the power transistor (for example, Q1 in Fig. 1) is connected to the input voltage via the primary winding of the transformer, and is connected to the ground via the sampling resistor. In various examples, the resistance values of the feedback voltage-dividing resistors R1 and R2 can be set by those skilled in the art as needed.

FIG. 6 is a diagram showing the corresponding relationship between the switching frequency Fs and the primary VCS value of the flyback power system and the feedback signal FB. As shown in FIG. 6, when FB> Vfb_2, the switching frequency Fs is a fixed value (for example, Fs_fix) has nothing to do with the FB voltage. At this time, the oscillator OSC (for example, OSC 510 in FIG. 5) directly controls the switching frequency fs, The switching frequency Fs can be adjusted by adjusting the frequency on the OSC to improve EMI conduction.

As the output load decreases, when Vfb_3 <FB <Vfb_2, the FB signal will control the OSC frequency at this time, and it will decrease as the FB voltage decreases. At FB = Va, by increasing the modulation frequency mode on the OSC, Fs = Fs_va ± △ fs. Because the output load is unchanged, the system loop adjustment FB voltage will change with the superimposed jitter amplitude △ fs on the OSC. In other words, as the superimposed jitter on the OSC increases (+ △ fs), that is, the system switching frequency will increase, and the control of the FB voltage through the secondary-side feedback loop will decrease, that is, FB = Va- △ fb. The period will be larger, and the secondary-side feedback loop ratio is faster. In the end, the periodic change of the switching frequency on the system will be much smaller than the designed modulation amplitude Δfs on the OSC. Among them, the output power P _{out (1)} can be expressed as follows: Where L _p is the inductance value of the inductor, I _p is the primary output current of the system, and Δfs is the modulation amplitude designed on the OSC.

In Equation 1, under the condition that the FB feedback signal is unchanged, after the OSC frequency in the down-frequency region increases jitter, it can be seen that the output power at this time is proportional to the system switching frequency P _{Out (1)} n ( F _s + △ Fs ).

In the actual system, the secondary control error amplifier feedback FB signal is output. When the OSC jitter amplitude increases to △ fs, the FB signal decreases by △ fb, and the output power P _{out (1) is} as follows:

In Equation 2, the actual OSC jitter amplitude will be controlled by FB loops and the final amplitude will be Δfs-Fs △ fb. Finally, the periodic change amplitude of the switching frequency on the system will be much smaller than the designed modulation amplitude Δfs on OSC.

FIG. 7 is a diagram showing the Fs jitter and Ip jitter of the flyback power system in the frequency reduction region over time. As shown in Figure 7, the periodic jitter amplitude Δfs is increased at the OSC frequency, and the same-direction signal △ Vcs is superimposed on the CS signal, and the jitter period is consistent with the frequency period on the OSC. The CS signal Vcs, which reflects the strength of the primary coil inductor current signal when the switch is on, can be expressed as follows: Vcs = I _p R _sence (Equation 3) where I _p is the primary coil inductor current and R _sence is the resistance of the sensing resistor value.

In one embodiment, the output power P _out can be expressed as follows: Where L _p is the inductance value of the inductor, I _p is the primary inductance current of the system, and Fs is the switching frequency.

When the system works in the frequency reduction area, keeping the output load constant (that is, P _{out is} constant), the OSC frequency jitter increases by Δfs, and the signal amplitude on CS decreases by ΔVcs (where ΔVcs is the change of the primary coil inductor current sensing signal ) Can be obtained:

Among them, P _{out ( T0 )} is the output power at T0 ; P _{out ( T1 )} is the output power at T0 ; and △ Ip = △ Vcs / Rsense, △ Vcs is the voltage change at the terminal CS and Rsense is the sensing resistance Resistor value.

By controlling the superimposed jitter amplitude △ fs on Fs and the superimposed jitter amplitude on the Vcs signal, P _{out ( T0 )} can be kept substantially equal to P _{out ( T1 )} . At this time, the secondary-side feedback control signal FB remains basically unchanged. It is found that the switching frequency amplitude Δfs is generally consistent with the actual test frequency variation on the system.

FIG. 8 is a simplified block diagram illustrating a quasi-resonant QR controller according to an embodiment of the present disclosure. This figure is only an example, and it should not unduly limit the scope of patent applications. Those of ordinary skill in the art should understand many variations, substitutions, and modifications.

As shown in FIG. 8, the quasi-resonant (QR) controller 800 (shown as a dotted line) includes an oscillator (OSC) 810, a feedback proportional voltage dividing resistor 820, a PWM comparator 830, an RS latch 840, and a gate driver. 850, a logic circuit 860, and a demagnetization sensing element 870. FIG. 8 also shows a current source, a feedback isolation element, and the like to which the PWM controller 800 is connected. The PWM controller is connected to external devices such as primary windings, secondary windings, electromagnetic interference (EMI) filters, rectifier bridges, isolated feedback components, and the like. The isolated feedback element may include, for example, a plurality of resistors, capacitors, three-terminal regulators, and optocouplers.

As shown in FIG. 8, a transformer including a primary winding and a secondary winding isolates the primary side and the secondary side of the QR controller 800. Information related to the output voltage on the secondary side can be extracted by a feedback proportional voltage dividing resistor 820 including resistors R1 and R2. The isolated feedback element generates a feedback signal based on information associated with the output voltage. The controller's information receives the feedback signal and generates a drive signal to turn the switch on and off to regulate the output voltage. If the power switch is closed (eg, turned on), energy is stored in a transformer including a primary winding and a secondary winding. A closed power switch allows current to flow through the winding once. The current is sensed by a resistor and converted into a current sensing signal (for example, VCS) through a terminal (for example, terminal CS). Subsequently, if the power switch is turned off (eg, turned off), the stored energy is released to the output and the system enters a demagnetization process.

The output voltage passes through the negative feedback error amplifier control input FB, and FB enters the PWM comparator through the resistor divider and CS signal. The feedback error amplifier output FB controls the peak current of CS to achieve output voltage adjustment. In order for the entire system to work stably, the feedback error amplifier needs to be compensated, and usually the bandwidth needs to be controlled below 1 / 10-1 / 15 of the switching frequency.

FIG. 9 is a diagram showing the relationship between the switching frequency Fs, the gate voltage Vcs, and the feedback signal FB of the QR controller. Among them, the system frequency and Vcs correspond to the FB relationship. When FB> Vfb_1, the system is in the QR mode, that is, the demagnetization is sensed by the winding DEM pin, and the crystal is turned on. In the interval of Vfb_2 <FB <Vfb_1, as the load decreases, the switching frequency of the system increases to reach the maximum frequency Fs_max of the system. In order to prevent the switching frequency from exceeding the maximum frequency limit, the system will delay the conduction at the second valley bottom and the third valley bottom in turn. As the output load continues to decrease, Vfb_3 <FB <Vfb_2, in order to reduce the switching loss of the system, the maximum frequency of the system decreases as the FB signal decreases.

In the light-load drop-down frequency band Vfb_3 <FB <Vfb_2, in order to improve the conduction mode EMI, it is hoped that the switching frequency of the system should not be too concentrated. It can achieve frequency jitter like a fixed frequency system, thereby improving EMI. The periodic jitter control is added to the frequency reduction curve of the FB signal control, and the reverse jitter signal is superimposed on the CS signal, so that the switching frequency of the system can be spread out.

FIG. 10 shows a schematic block diagram of an implementation manner of jitter control of a QR system according to an embodiment of the present disclosure. This figure is only an example, and it should not unduly limit the scope of patent applications. Those of ordinary skill in the art should understand many variations, substitutions, and modifications. As shown in FIG. 10, the QR controller 1000 includes an oscillator (OSC) 1010, a feedback proportional voltage dividing resistor 1020, a PWM comparator 1030, an RS latch 1040, a gate driver 1050, a logic circuit 1060, and a demagnetization sensing element. 1070, and a jitter control element 1080 and a jitter generating element 1090.

As shown in FIG. 10, the input of the OSC 1010 is connected to the feedback proportional voltage dividing resistor 1020 and the output is connected to the logic circuit 1060. The non-inverting input of the PWM comparator 1030 is connected to the feedback proportional voltage dividing resistor 1020, the inverting input is connected to the jitter generating element 1090, and the output is connected to the R terminal of the RS latch 1040. The R terminal of the RS latch 1040 is connected to the PWM ratio The output of the comparator 1030, the S terminal is connected to the logic circuit output, and the Q terminal is connected to the input of the gate driver 1050. The output of the gate driver 1050 is coupled to the base of a power transistor (eg, Q1). The base of the power transistor is coupled to the output of the gate driver 1050, the collector is coupled to one end of the primary winding inductance of a transformer (not shown), and the emitter is coupled to one end of the sampling resistor Rs ( The other end of the resistor Rs is coupled to the ground signal).

As shown in Figure 10, the frequency of the OSC in the light-load down-conversion area is controlled by the feedback signal FB, and the periodic jitter modulation is superimposed on the OSC frequency. A Vcs_ jitter signal is superimposed before the V _cs signal enters the PWM comparator to achieve the jitter modulation of the primary coil inductance peak current I _pk , so that the switching frequency of the system can also be modulated by the jitter periodic signal. V _CS _ jitter is a way that the periodically changing signal is consistent with the OSC period, and the signal amplitude is continuously changing during the period.

FIG. 11 shows a schematic block diagram of another implementation of jitter control of a QR system according to an embodiment of the present disclosure. This figure is only an example, and it should not unduly limit the scope of patent applications. Those of ordinary skill in the art should understand many variations, substitutions, and modifications. The controller shown is similar to FIG. 10, and its connection relationship is not repeated here. In the embodiment shown in FIG. 11, a low-pass filter (LPF) is further included, which is configured to receive a feedback signal and output the filtered feedback signal to an oscillator. In the QR system light-load frequency reduction, the FB signal controls the frequency reduction of the OSC, reducing the highest frequency to achieve frequency reduction. Compared with the embodiment shown in FIG. 10, the FB signal enters the OSC after passing through the LPF. Since V _CS _ jitter is a periodically changing signal consistent with the OSC cycle, the signal amplitude is continuously changed in the cycle, which can reduce the secondary The influence of side EA feedback FB signal fluctuation on the amplitude of OSC jitter.

According to an embodiment, a periodic jitter modulation is superimposed on the OSC frequency, and a Vcs_ jitter signal is superimposed before the V _cs signal enters the PWM comparator to implement jitter modulation of the I _pk current, so that the switching frequency of the system can also be jittered. Periodic signal modulation. V _CS _ jitter is a way that the periodically changing signal is consistent with the OSC period, and the signal amplitude is continuously changing during the period.

FIG. 12 shows a schematic block diagram of still another implementation manner of jitter control of a QR system according to an embodiment of the present disclosure. This figure is only an example, and it should not unduly limit the scope of patent applications. Those of ordinary skill in the art should understand many variations, substitutions, and modifications. The controller shown is similar to FIG. 10, and its connection relationship is not repeated here. In the embodiment shown in FIG. 11, according to one embodiment, the OSC frequency of the light-load frequency reduction region is controlled by the feedback signal FB, and the periodic jitter modulation is superimposed on the OSC frequency. A Vcs_ jitter signal is superimposed before the V _cs signal enters the PWM comparator to achieve jitter modulation of the I _pk current. According to an embodiment, the clock signal of the secondary-side feedback FB signal and the OSC jitter controls the amplitude of the output signal of the jitter generator, thereby controlling the amplitude of the jitter superimposed on the CS, so that the jitter on the OSC can be controlled to correspond to the jitter signal superimposed on the CS, Reduce the interference of the OSC jitter on the entire loop, that is, the FB signal remains relatively constant during the OSC jitter cycle, and reduce the effect of the secondary-side EA on the OSC jitter.

In the embodiment of the present disclosure, a jitter signal is introduced on both the OSC and the CS to implement the jitter function of the system switching frequency. Turn-on EMI has a wider energy distribution range at each harmonic frequency point in the frequency spectrum. At the same time, because the total energy is constant, the amplitude of each harmonic frequency point will be lower, and the EMI margin will be greater.

The present invention may be implemented in other specific forms without departing from the spirit and essential characteristics thereof. For example, the algorithms described in particular embodiments may be modified without the system architecture departing from the basic spirit of the invention. Therefore, the current embodiment is considered in all aspects as exemplary rather than limiting, the scope of the present invention is defined by the scope of the attached patent application rather than the above description, and the meanings and equivalents falling within the scope of the patent application All changes within the scope of the substance are thus included in the scope of the present invention.

Some or all of the elements of the various embodiments of the invention, alone and / or in combination with at least another element, are one of one or more software elements, one or more hardware elements, and / or software and hardware elements Or multiple combinations to achieve. In another example, some or all of the elements of various embodiments of the present invention are implemented in one or more circuits alone and / or in combination with at least another element, such as in one or more analog circuits and / or Implemented in one or more digital circuits. In yet another example, various embodiments and / or examples of the present invention may be combined.

Although specific embodiments of the present invention have been described, those skilled in the art will appreciate that there are other embodiments equivalent to the described embodiments. Therefore, it will be understood that the present invention is not limited by the specific embodiments shown, but only by the scope of the patent application.

Claims (8)

A system for improving electromagnetic interference (EMI) of a flyback switching power supply includes: a logic circuit configured to generate a latch signal based at least in part on a first signal; an oscillator (OSC), the oscillation An input of the converter is connected to the feedback proportional voltage dividing resistor and an output is connected to the logic circuit, and is configured to generate the first signal and transmit the first signal to the logic circuit, wherein the feedback proportional voltage division The resistor is configured to generate a feedback signal according to an output voltage of the system; a jitter generator configured to generate a second signal and transmit the second signal to a comparator; the comparator, all The non-inverting input of the comparator is connected to the feedback proportional voltage dividing resistor, the inverting input is connected to the jitter generator, and the output is connected to the R terminal of the RS latch, so as to generate a comparison signal based on the feedback signal and the second signal; In the RS latch, an R terminal of the RS latch is connected to an output of the comparator, an S terminal is connected to an output of the logic circuit, and a Q terminal is connected to a gate driver. Input to generate a third signal based on the comparison signal and the latch signal; the gate driver, the gate driver is configured to receive the third signal, and is based at least in part on the third signal A signal generating driving signal to control on and off of a power transistor connected to the gate driver; and a jitter controller configured to receive a reference signal and generate based at least in part on the reference signal A control signal, wherein the first signal is generated by the oscillator based on the control signal; wherein the jitter generator is configured to be based at least in part on a change in an internal frequency of a switching frequency of the system Amplitude to generate the second signal. The system of claim 1, wherein the first signal is generated by the oscillator based on the control signal and the feedback signal. The system according to item 1 of the scope of patent application, further comprising a low-pass filter configured to receive the feedback signal and output the filtered feedback signal to the oscillator. The system of claim 1, wherein the jitter generator is configured to generate the second signal based at least in part on the clock signal. The system according to item 1 of the patent application scope, further comprising a sensing resistor, one end of which is coupled to the comparator, one end of which is grounded, and is configured to be based on a primary coil inductance of the system A current is used to generate a current sensing signal, wherein an output signal of the jitter generator is superimposed on the current sensing signal, and the superimposed signal is output to an inverting input terminal of the comparator. The system according to item 1 of the patent application scope, further comprising an error amplifier configured to receive an output voltage of the system and generate a feedback voltage based on the output voltage, wherein the feedback signal is based on The feedback voltage is generated. The system according to item 6 of the patent application scope, wherein the error amplifier is configured to control a bandwidth of the system to be less than 1/10 of a switching frequency of the system. A switching power supply includes the system for improving electromagnetic interference (EMI) of a flyback switching power supply according to any one of patent application scope items 1-7.