TWI650748B - Display panel and driving method thereof - Google Patents

Abstract

The display panel includes a data line, a scan line, and first and second sub-pixel circuits. The first sub-pixel circuit includes a first transistor. The control end of the first transistor is connected to the scan line, the other first end is connected to the data line, and the first transistor has a first threshold voltage. The second sub-pixel circuit includes a second transistor. The control end of the second transistor is connected to the scan line, the other first end is connected to the data line, and the second transistor has a second threshold voltage different from the first threshold voltage. During the first time period, the gate driving signal turns on the data signal of the second transistor receiving the data line and writes the data signal to the second storage capacitor. During the second period, the gate driving signal turns on the data signal of the first transistor receiving the data line and writes the data signal to the first storage capacitor. In the third period, the first transistor and the second transistor are in an off state.

Description

Display panel and display panel driving method

The present invention relates to a display panel and a driving method thereof; in particular, the present invention relates to a driving method of a pixel circuit in a display panel.

Conventionally, a plurality of scan lines and data lines are disposed on a pixel array substrate of a display device. The pixel circuit is connected to the scan line and the data line; and the scan circuit can transmit the scan signal through the scan line to turn on each column of pixel circuits, so that the pixel circuit receives the data signal transmitted from the data line.

In general, each sub-pixel requires a data line and a scan line to drive. However, as the resolution of display devices increases, more drive wafers will be required to provide more pins to connect to the scan lines and data lines; at the same time, the increase in drive wafers will increase the cost of many fabrications. Therefore, how to save the number of driving chips under the improved resolution has become a problem to be solved at present.

It is an object of the present invention to provide a display panel which can reduce the number of driving wafers.

An object of the present invention is to provide a driving method of a display panel capable of driving a plurality of sub-pixel circuits having different threshold voltages.

The display panel includes a data line, a scan line, a first sub-pixel circuit, and a second sub-pixel circuit. The first sub-pixel circuit includes a first transistor. The control end of the first transistor is connected to the scan line, the other first end is connected to the data line, and the first transistor has a first threshold voltage. The second sub-pixel circuit includes a second transistor. The control end of the second transistor is connected to the scan line, the other first end is connected to the data line, and the second transistor has a second threshold voltage different from the first threshold voltage. During the first time period, the gate driving signal turns on the data signal of the second transistor receiving the data line and writes the data signal to the second storage capacitor. During the second period, the gate driving signal turns on the data signal of the first transistor receiving the data line and writes the data signal to the first storage capacitor. In the third period, the first transistor and the second transistor are in an off state.

The driving method of the display panel comprises the steps of: receiving a gate driving signal from the scanning line; conducting the first transistor and the second transistor according to the gate driving signal; and in the first period, the gate driving signal is conducting the second transistor to receive the data The data signal of the line is written to the second storage capacitor. During the second period, the gate driving signal turns on the data signal of the first transistor receiving the data line and writes the data signal to the first storage capacitor. In the third period, the first transistor and the second transistor are in an off state.

10‧‧‧ display panel

12‧‧‧data circuit

14‧‧‧Scan circuit

16,16a‧‧‧pixel circuit

110‧‧‧First sub-pixel circuit

112‧‧‧Optoelectronics

112a‧‧‧ first end

114‧‧‧ Storage Capacitor

120‧‧‧Second sub-pixel circuit

122‧‧‧Optoelectronics

122a‧‧‧ first end

124‧‧‧ Storage Capacitor

130‧‧‧ Third sub-pixel circuit

132‧‧‧Optoelectronics

132a‧‧‧ first end

134‧‧‧ storage capacitor

140‧‧‧ fourth sub-pixel circuit

142‧‧‧Optoelectronics

142a‧‧‧ first end

144‧‧‧ storage capacitor

DL, DL1‧‧‧ data line

GL, GL1‧‧‧ scan line

1A is a schematic view of a display panel of the present invention.

FIG. 1B is a schematic diagram of an embodiment of a pixel circuit of a display panel of the present invention.

2A is a schematic diagram of an embodiment of a gate driving signal.

2B is a schematic diagram of another embodiment of a gate driving signal.

3 is an I _D -V _G electrical diagram of a transistor in a pixel structure.

4 is a driving flowchart of the display panel.

FIG. 5 is a schematic diagram of another embodiment of a pixel circuit of a display panel.

6 is a schematic diagram of another embodiment of a gate driving signal.

Fig. 7 is a flow chart showing another driving of the display panel.

8 and 9 are schematic views of different embodiments of a pixel circuit of a display panel.

The present invention provides a display panel and a driving method of the display panel, which can be used for various display devices such as a liquid crystal display device. In the following, the terms of the first, second, and third terms are used to distinguish the same technical terms, and are not intended to limit the present invention.

FIG. 1A is a schematic view of a display panel 10 of the present invention. As shown in FIG. 1A, the display panel 10 includes data lines (DL, DL1) and scan lines (GL, GL1). The data lines (DL, DL1) are connected to the data circuit 12, and the scan lines (GL, GL1) are connected to the scanning circuit 14. The data lines (DL, DL1) can pass the data signals generated by the data circuit 12, and the scan lines (GL, GL1) can pass the gate driving signals generated by the scanning circuit 14. Further, pixel circuits such as the pixel circuits 16 and 16a are provided at the intersection of the data lines (DL, DL1) and the scanning lines (GL, GL1).

The pixel circuit preferably includes a plurality of sub-pixel circuits. Taking the pixel circuit 16 as an example, as shown in FIG. 1B, the pixel circuit 16 includes a first sub-pixel circuit 110 and a second sub-pixel circuit 120. The first sub-pixel circuit 110 includes a first transistor 112 and a first storage capacitor 114. The control terminal of the first transistor 112 is connected to the scanning line GL, and the other first terminal 112a is connected to the data line DL. The second sub-pixel circuit 120 includes a second transistor 122 and a second storage capacitor 124. Similarly, the control terminal of the second transistor 122 is connected to the scanning line GL, and the other first terminal 122a is connected to the data line DL. Thereby, the first sub-pixel circuit 110 and the second sub-pixel circuit 120 can receive the data signals transmitted by the same data line DL. In the embodiment of FIG. 1B, the first transistor 112 and the second transistor 122 are located on the same side of the data line DL and on the same side of the scan line GL.

In addition, the aforementioned first transistor 112 and the second transistor 122 have different threshold voltages. Please refer to Figure 2A. 2A is a schematic diagram of an embodiment of a gate driving signal. As shown in Figure 2A, the gate drive signals have different levels during different periods of an operational cycle. For example, the first transistor 112 and the second transistor 122 in FIG. 1B are both N-type transistors, wherein the first transistor 112 has a threshold voltage V _TH1 and the second transistor 122 has a threshold voltage V _TH2 . And V _TH1 <V _TH2 . In this embodiment, the gate drive signal exhibits a step signal that decreases with time. The scan line GL turns on the first transistor 112 and the second transistor 122 according to the gate driving signal.

Please refer to FIG. 1B and FIG. 2A. During the time period t1, the level of the gate driving signal is greater than the threshold voltage V _TH2 , and the second transistor 122 is turned on to receive the data signal of the data line DL and write to the second storage capacitor 124 . During the time period t2, the level of the gate driving signal is between the threshold voltage V _TH1 and the threshold voltage V _TH2 , and the first transistor 112 is turned on to receive the data signal of the data line DL and written into the first storage capacitor 114 . During the period t3, the level of the gate driving signal is less than the threshold voltage V _TH1 , and the first transistor 112 and the second transistor 122 are in an off state.

It should be understood that, in the above embodiment, during the period t1, although the first transistor 112 is also turned on and erroneously receives the data transmitted from the data line, the error time is actually relative to the display panel in each column of pixels. The total write time is relatively short and should be negligible.

2B is a schematic diagram of another embodiment of a gate driving signal. As shown in Figure 2B, the gate drive signals have different levels during different periods of an operational cycle. In this embodiment, the first transistor 112 and the second transistor 122 in FIG. 1B are both P-type transistors, wherein the first transistor 112 has a threshold voltage V _TH1 and the second transistor 122 has a threshold voltage. V _TH2 and V _TH1 >V _TH2 . In this embodiment, the gate drive signal exhibits a step signal that increases with time. The scan line GL turns on the first transistor 112 and the second transistor 122 according to the gate driving signal. Please refer to FIG. 1B and FIG. 2B. During the time period t1, the level of the gate driving signal is less than the threshold voltage V _TH2 , and the second transistor 122 is turned on to receive the data signal of the data line DL and write to the second storage capacitor 124 . During the time period t2, the level of the gate driving signal is between the threshold voltage V _TH1 and the threshold voltage V _TH2 , and the first transistor 112 is turned on to receive the data signal of the data line DL and written into the first storage capacitor 114 . During the period t3, the level of the gate driving signal is greater than the threshold voltage V _TH1 , and the first transistor 112 and the second transistor 122 are in an off state.

Thereby, in different time periods, the level of the gate driving signal is located at different positions defined by the threshold voltage V _TH1 and the threshold voltage V _TH2 , and the lighting state of each sub-pixel circuit is changed, so that each sub-pixel circuit can be sequentially Receive data signals transmitted by the same data line. For the case where the transistor type is changed, the form of the gate driving signal can be adjusted correspondingly as shown in FIG. 2A or FIG. 2B, and the design of the plurality of sub-pixel circuits corresponding to the same data line as proposed by the invention can still be used. Since the number of data lines required for all sub-pixels is reduced, the demand for the pins is also reduced, which can reduce the amount of driving chips used in the data circuit and reduce the manufacturing cost. In addition, for the case where the same type of transistor is used for each sub-pixel circuit, the gate driving signals of each column preferably have the same waveform to provide a stable display effect.

3 is an I _D -V _G electrical diagram of a transistor in a pixel structure. FIG. 3 is a diagram showing the relationship of I _D -V _G by taking the operation mode of FIG. 2A as an example. As shown in FIG. 3, the vertical axis is the drain current (I _D ), the horizontal axis is the gate voltage (V _G ), and the curves C1 and C2 respectively indicate the different gate voltages of the first transistor 112 and the second transistor 122. The bungee current changes. As shown in FIG. 3, in the interval R1, the gate voltage is small, and the drain currents of the first transistor 112 and the second transistor 122 are both smaller than the lower boundary current IL, which may correspond to, for example, V _{G in the} operation of FIG. 2A. In the case of V _TH1 , the first transistor 112 and the second transistor 122 are in an off state. As the gate voltage increases, in the interval R2, the drain current of the first transistor 112 is greater than the upper bound current IU, and the drain current of the second transistor 122 is less than the lower bound current IL, at which time V _TH1 <V _G <V _TH2 , the first transistor 112 is turned on and the second transistor 122 is turned off. In the interval R3, the first current of the first transistor 112 and the second transistor 122 are greater than the upper limit current IU. At this time, V _G >V _TH2 , the first transistor 112 and the second transistor 122 are turned on.

4 is a driving flowchart of the display panel. As shown in FIG. 4, the driving method of the display panel includes steps S101, S103, and S105. In step S101, the gate driving signal is received from the scan line. In step S103: the second transistor is turned on according to the gate driving signal. In step S105: the first transistor is turned on according to the gate driving signal. With this design, the display panel can drive a plurality of sub-pixel circuits having different threshold voltages. It should be added that each transistor has a different threshold voltage, for example, through a change in the amount of doping. Taking the structure of FIG. 1B as an example, when doping is performed on a region corresponding to the second transistor 122, a region corresponding to the first transistor 112 is shielded, and when doping is performed on a region corresponding to the first transistor 112, correspondingly The regions of the first transistor 112 and the second transistor 122 are not obscured, and thus the regions corresponding to the first transistor 112 and the second transistor 122 have different doping concentrations. Since the doping concentration has a proportional relationship with the threshold voltage value, the second transistor 122 may have a larger threshold voltage than the first transistor 112. In other examples, different oxide voltage values can be obtained by varying the thickness of the oxide oxide layer to form different threshold voltages. In addition, another metal line can be formed through a region corresponding to the first transistor 112 (refer to FIG. 1B) to form a double gate structure transistor, and the threshold voltage is changed by the structure of the double gate to form a different Threshold voltage.

FIG. 5 is a schematic diagram of another embodiment of a pixel circuit of a display panel. As shown in FIG. 5, the difference from the foregoing embodiment is that the pixel circuit 16 of the display panel further includes a third sub-pixel circuit 130 and a fourth sub-pixel circuit 140. In the embodiment of FIG. 5, the third sub-pixel circuit 130 includes a third transistor 132 and a third storage capacitor 134. The control terminal of the third transistor 132 is connected to the scanning line GL, and the other first terminal 132a is connected to the data line DL. The fourth sub-pixel circuit 140 includes a fourth transistor 142 and a fourth storage capacitor 144. Similarly, the control terminal of the fourth transistor 142 is connected to the scanning line GL, and the other first end 142a is connected to the data line DL. Thereby, the first sub-pixel circuit 110, the second sub-pixel circuit 120, the third sub-pixel circuit 130, and the fourth sub-pixel circuit 140 can receive the data signals transmitted by the same data line DL.

In the embodiment of FIG. 5, the data line DL is interleaved with the scan line GL, and the first transistor 112, the second transistor 122, the third transistor 132, and the fourth transistor 142 are located on the same side of the data line DL, and Located on the same side of the scan line GL. In an embodiment, the sub-pixel circuits (110, 120, 130, 140) are connected to each other via a corresponding transistor. In detail, the first transistor 112 is connected to the first storage capacitor 114, the second transistor 122 is connected to the second storage capacitor 124, the third transistor 132 is connected to the third storage capacitor 134, and the fourth transistor 142 is connected to the fourth storage capacitor. 144. The first ends (112a, 122a, 132a, 142a) of the first transistor 112, the second transistor 122, the third transistor 132, and the fourth transistor 142 are respectively connected to the data line DL.

Further, the third transistor 132 and the fourth transistor 142 have different threshold voltages. Further, the magnitudes of the threshold voltages of the first transistor 112, the second transistor 122, the third transistor 132, and the fourth transistor 142 are different from each other. Please refer to Figure 6. 6 is a schematic diagram of another embodiment of a gate driving signal. As shown in Figure 6, the gate drive signals have different levels during different periods of an operational cycle. For example, the transistors (112, 122, 132, 142) in FIG. 5 are both N-type transistors, wherein the first transistor 112 has a threshold voltage V _TH1 , the second transistor 122 has a threshold voltage V _TH2 , and the third transistor 132 has a critical value. The voltage V _TH3 , the fourth transistor 142 has a threshold voltage V _TH4 , and V _TH1 <V _TH2 <V _TH3 <V _TH4 . In this embodiment, the gate drive signal exhibits a step signal that decreases with time. The scan line GL conducts the transistor (112, 122, 132, 142) according to the gate drive signal.

Please refer to FIG. 5 and FIG. 6 together with the driving flowchart shown in FIG. 7. In step S201, the gate driving signal is received from the scan line. In step S203: the fourth transistor is turned on according to the gate driving signal. During the time period t1, the level of the gate driving signal is greater than the threshold voltage V _TH4 , and the fourth transistor 142 is turned on to receive the data signal of the data line DL and write to the fourth storage capacitor 144.

In step S205: the third transistor is turned on according to the gate driving signal. During the time period t2, the level of the gate driving signal is between the threshold voltage V _TH3 and the threshold voltage V _TH4 , and the third transistor 132 is turned on to receive the data signal of the data line DL and write to the third storage capacitor 134 .

In step S207: the second transistor is turned on according to the gate driving signal. During the time period t3, the level of the gate driving signal is greater than the threshold voltage V _TH2 , and the second transistor 122 is turned on to receive the data signal of the data line DL and write to the second storage capacitor 124 .

In step S209, the first transistor is turned on according to the gate driving signal. During the period t4, the level of the gate driving signal is between the threshold voltage V _TH1 and the threshold voltage V _TH2 , and the first transistor 112 is turned on to receive the data signal of the data line DL and written into the first storage capacitor 114 . During the period t5, the level of the gate driving signal is less than the threshold voltage V _TH1 , and the transistor (112, 122, 132, 142) is in the off state. With this design, the display panel can drive a plurality of sub-pixel circuits having different threshold voltages.

Thereby, in different time periods, the level of the gate driving signal is at different positions defined by the threshold voltages (V _TH1 , V _TH2 , V _TH3 , V _TH4 ), and the lighting states of the respective sub-pixel circuits are changed, so that each The sub-pixel circuit can sequentially receive the data signals transmitted by the same data line. Since the data lines required for all sub-pixels are further reduced, the demand for the pins is also reduced, which further reduces the amount of driving wafers used in the data circuit and reduces manufacturing costs. In addition, for the case where the same type of transistor is used for each sub-pixel circuit, the gate driving signals of each column preferably have the same waveform to provide a stable display effect.

8 and 9 are schematic views of different embodiments of a pixel circuit of a display panel. As shown in FIG. 8, the data line DL and the scanning line GL are alternately arranged, which is different from the foregoing embodiment in that the second transistor 122 is disposed on a side of the data line DL opposite to the first transistor 112. Similarly, the first ends (112a, 122a) of the first transistor 112 and the second transistor 122 are respectively connected to the data line DL. The first transistor 112 and the second transistor 122 have different threshold voltages. The first sub-pixel circuit 110 and the second sub-pixel circuit 120 can be operated by using a gate driving signal as shown in FIG. 2A. Therefore, each sub-pixel circuit can sequentially receive the data signals transmitted by the same data line. The design can reduce the amount of driving wafers used in the data circuit and reduce the manufacturing cost.

As shown in FIG. 9, the data line and the scan line are alternately arranged, and the second transistor 122 is disposed on a side of the data line DL opposite to the first transistor 112. The third transistor 132 and the fourth transistor 142 are located on one side of the scanning line GL opposite to the first transistor 112 and the second transistor 122. In other words, the first transistor 112 and the second transistor 122 are in the same column, and the third transistor 132 and the fourth transistor 142 are in another column. The scan line GL conducts the transistor (112, 122, 132, 142) according to the gate drive signal. The first ends (112a, 122a, 132a, 142a) of the first transistor 112, the second transistor 122, the third transistor 132, and the fourth transistor 142 are respectively connected to the data line DL. When the first transistor 112 or the second transistor 122 is turned on, the data signal of the data line DL can be received and written into the corresponding storage capacitor. Similarly, when the third transistor 132 or the fourth transistor 142 is turned on, the data signal of the data line DL can be received and written into the corresponding storage capacitor.

The first transistor 112, the second transistor 122, the third transistor 132, and the fourth transistor 142 have different threshold voltages. The sub-pixel circuit (110, 120, 130, 140) can be operated by using a gate driving signal as shown in FIG. 6, so that each sub-pixel circuit can sequentially receive the data signals transmitted by the same data line. Thereby, in different time periods, the level of the gate driving signal is at different positions defined by the threshold voltages (V _TH1 , V _TH2 , V _TH3 , V _TH4 ), and the lighting states of the respective sub-pixel circuits are changed, so that each The sub-pixel circuit can sequentially receive the data signals transmitted by the same data line. As described above, the design can reduce the amount of driving wafers used in the data circuit and reduce the manufacturing cost. In addition, in the embodiment shown in FIG. 9, since the sub-pixel circuits of different columns can be driven by the same scanning line, the demand for the corresponding pins of the scanning lines is also reduced, and the circuit layout area can be saved. Or it can further reduce the amount of driving wafers used in the scanning circuit.

The present invention has been described by the above-described related embodiments, but the above embodiments are merely examples for implementing the present invention. It should be noted that the disclosed embodiments do not limit the scope of the present invention. Wai. On the contrary, modifications and equivalents of the spirit and scope of the invention are included in the scope of the invention.

Claims (8)

A display panel includes: a data line and a scan line; a first sub-pixel circuit, the first sub-pixel circuit includes a first transistor, a control end of the first transistor is connected to the scan line, and the other The first end is connected to the data line, and the first transistor has a first threshold voltage; a second sub-pixel circuit, the second sub-pixel circuit comprises a second transistor, and a control end of the second transistor Connecting the scan line, the other first end is connected to the data line, and the second transistor has a second threshold voltage different from the first threshold voltage; wherein the scan line turns on the first according to a gate driving signal And a second transistor, wherein the gate driving signal is at a first position outside the range of the first threshold voltage and the second threshold voltage during a first period of time, and the second transistor is turned on Receiving a data signal of the data line and writing to a second storage capacitor connected to the second transistor; and in a second period, the level of the gate driving signal is between the first threshold voltage and the second threshold One of the range of voltages a second position, the first transistor receives the data signal of the data line and is written into a first storage capacitor connected to the first transistor; and in a third period, the level of the gate driving signal is located at the second The first transistor and the second transistor are in an off state, outside the range of a threshold voltage and the second threshold voltage, and at a third position on the side opposite to the first position. The display panel of claim 1, wherein the gate driving signal is a step signal that decreases with time. The display panel of claim 1, wherein the gate driving signal has a higher level than the first threshold voltage and the second threshold voltage during the first period, and the gate driving signal is in the third period The level is lower than the first threshold voltage and the second threshold voltage. The display panel of claim 1, wherein the gate drive signal bit is in the first time period The level of the gate driving signal is higher than the first threshold voltage and the second threshold voltage in the third period. The display panel of claim 1, wherein the second electro-optic system is disposed on a side of the data line opposite to the first transistor. The display panel of claim 1, further comprising: a third sub-pixel circuit, comprising a third transistor, a control end of the third transistor is connected to the scan line, and the other first end is connected to the data line And the third transistor has a third threshold voltage; and a fourth sub-pixel circuit includes a fourth transistor, a control end of the fourth transistor is connected to the scan line, and the other first end is connected to the a data line, and the fourth transistor has a fourth threshold voltage, and the first threshold voltage, the second threshold voltage, the third threshold voltage, and the fourth threshold voltage are different from each other; wherein the data line Interleaved with the scan line, the third transistor and the fourth transistor are located on the side of the scan line opposite to the first transistor and the second transistor, and the scan line is turned on according to the gate drive signal. The fourth transistor and the fourth transistor, in a fourth period, the level of the gate driving signal is outside the range of the third threshold voltage and the fourth threshold voltage, and the first position is opposite to the a fourth on the side of the second position Positioning, the fourth transistor receives the data signal of the data line and writes to a fourth storage capacitor connected to the fourth transistor; and in a fifth period, the level of the gate driving signal is located at the third Between the threshold voltage and the fourth threshold voltage, and at a fifth position between the first position and the fourth position, turning on the third transistor to receive the data signal of the data line and writing the connection One of the three transistors is a third storage capacitor. A display panel driving method, the display panel includes a data line and a scan line, and the driving method of the display panel comprises the following steps: receiving a gate driving signal from the scan line, wherein the scan line is respectively connected to a first sub image a control terminal of a first transistor of a prime circuit and a control terminal of a second transistor of a second sub-pixel circuit, wherein the data line is respectively connected to the other first end of the first transistor and the second transistor The first transistor has a first threshold voltage, and the second transistor has a second threshold voltage different from the first threshold voltage; and the first transistor is turned on according to the gate driving signal And a second transistor; wherein, in a first period of time, the level of the gate driving signal is at a first position outside the range of the first threshold voltage and the second threshold voltage, and the second electricity is turned on Receiving, by the crystal, a data signal of the data line and writing to a second storage capacitor connected to the second transistor; and in a second time period, the level of the gate driving signal is between the first threshold voltage and the second a second position between the range of the threshold voltage, the first transistor receiving the data signal of the data line and writing to the first storage capacitor connected to the first transistor; and the gate during a third period The level of the drive signal is located at the first Outside the range of the second threshold voltage and the voltage, in the second position and a third position opposite to the position of the first side of the first transistor and the second transistor is turned off. The method of claim 7, wherein the display panel comprises a third sub-pixel circuit having a third transistor and a fourth sub-pixel circuit having a fourth transistor, the third transistor having a third a threshold voltage, and the fourth transistor has a fourth threshold voltage, the first threshold voltage, the second threshold voltage, the third threshold voltage, and the fourth threshold voltage are different from each other, and the method includes the following steps The scan line turns on the third transistor and the fourth transistor according to the gate driving signal, wherein, in a fourth period, the level of the gate driving signal is located at the third threshold voltage and the fourth threshold Outside the range of the voltage, and at a fourth position on the side opposite to the second position, the fourth transistor is turned on to receive the data signal of the data line and is written into one of the fourth transistors. a fourth storage capacitor; in a fifth period, the level of the gate driving signal is between the third threshold voltage and the fourth threshold voltage, and a first position between the first position and the fourth position In a five-position, the third transistor receives the data signal of the data line and writes to a third storage capacitor connected to the third transistor.