TWI637601B - Band selected clock data recovery circuit and associated method - Google Patents

Abstract

The first clock data recovery circuit comprises: a frequency band selection circuit, a low dropout voltage regulator, a charge pump and a voltage controlled oscillator, wherein the frequency band selection circuit generates a digital signal according to the at least one reference voltage; the low drop voltage voltage regulator Regulating a ground voltage, wherein the low dropout regulator adjusts a bias current of one of the amplifiers to change an operating frequency band by receiving at least a portion of the digital signal; the charge pump is based on at least a portion of the digital circuit Part of generating a control voltage; and the voltage control oscillator generates a clock signal according to the control voltage, wherein the voltage control oscillator adjusts a bias current of the voltage control oscillator by receiving at least a portion of the digital signal to change The clock data recovers an operating frequency band of the circuit.

Description

Band selection clock data recovery circuit and related method

The invention relates to a clock data recovery circuit (CDR), in particular to a frequency band selection clock data recovery circuit and related methods.

In a conventional thin film transistor (LCD) system, ground noise generated by high voltage (such as 12 volts) will generate jitter on the clock data recovery circuit, resulting in clock data. The performance of the recovery circuit is reduced. In addition, for a broadband application (such as 160MHz-1.8GHz operating frequency), the circuit components in the clock recovery circuit, such as a Voltage-Controlled Oscillator (VCO), need to be sufficient to respond. Different frequency bands are used to obtain better performance, otherwise the clock signal generated by the voltage control oscillator will generate more jitter.

One of the objects of the present invention is to provide a band selection clock data recovery circuit and a related method to solve the problems in the prior art.

According to an embodiment of the invention, a clock data recovery circuit includes: a frequency band selection circuit, a low dropout voltage regulator, a charge pump, and a voltage controlled oscillator, wherein the band selection circuit is used according to at least a reference voltage generating a frequency band select digital signal; the low dropout voltage regulator is configured to regulate a ground voltage, wherein the low dropout voltage regulator adjusts the low voltage difference by receiving at least a portion of the digital signal of the frequency band a bias current of an amplifier in the voltage converter to change an operating frequency band of the low dropout voltage regulator; the charge pump is configured to select at least a portion of the digital signal to generate a control voltage according to the frequency band; and the voltage control The oscillator is configured to generate a clock signal according to the control voltage, wherein the voltage control oscillator adjusts a bias current of the voltage control oscillator to change the clock data recovery circuit by receiving at least a portion of the frequency band selection digital signal An operating band.

According to an embodiment of the invention, a method for recovering a clock data applied to a clock data recovery circuit includes: generating a frequency band selection digital signal according to at least one reference voltage; and performing a ground voltage by using a low drop voltage regulator Voltage regulation, wherein the low dropout regulator adjusts a bias current of an amplifier in the low dropout regulator to change an operating frequency band of the low dropout regulator by receiving at least a portion of the frequency band selection signal; Selecting at least a portion of the digital signal based on the frequency band to generate a control voltage; and utilizing a voltage control oscillator to generate a clock signal based on the control voltage, wherein the voltage control oscillator adjusts by receiving at least a portion of the frequency band select digital signal The voltage controls a bias current of the oscillator to change an operating frequency band of the clock data recovery circuit.

Certain terms are used throughout the description and following claims to refer to particular elements. Those of ordinary skill in the art should understand that a hardware manufacturer may refer to the same component by a different noun. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection means. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the device. The second device is indirectly electrically connected to the second device through other devices or connection means.

1 is a schematic diagram of a clock data recovery circuit 10 according to an embodiment of the present invention. As shown in FIG. 1, the clock data recovery circuit 10 includes a conventional circuit component such as a preamplifier 1' and a differential single terminal ( Differential-to-single) conversion circuit 2', a two-bit phase detector 3' (Bang-bang Phase Detector, BBPD), a phase frequency detector 4', a multiplexer 5', a lock detection A lock detector 6' and a frequency divider 7', and further comprising a band selection circuit 101, a low drop regulator (LDO) 102, and a voltage-controlled oscillator. VCO) 103, a charge pump 104 and a low pass filter 105. The present invention applies a band selection technique to the low dropout regulator 102, the voltage controlled oscillator 103, and the charge pump 104 (the elements are shown to the right of the dashed line in Figure 1) regarding the conventional circuit components (in the first The figure is shown to the left of the dashed line) is a known technique and will not be further described here to save space. The band selection circuit 101 is configured to compare a control voltage VCTRL with a reference voltage VREF to generate a band selection digital signal BS. It should be noted that the band selection digital signal BS is represented by BS[2:0] in this embodiment. However, this is merely an illustrative example and is not a limitation of the present invention. In other embodiments of the invention, the band select digital signal BS may comprise more or less than 3 bits, depending on actual design requirements.

The low dropout regulator 102 regulates a ground voltage VSS using a regulated ground voltage VSSVCO generated by the voltage controlled oscillator 103 to prevent ground noise generated by a high voltage from affecting the clock data recovery circuit 10. Other circuit components included in the integrated circuit. The low dropout regulator 102 can alternatively receive at least a portion of the band select digital signal BS, such as two bits of the band select digital signal BS (ie, BS[2:1]) to change the bias voltage by changing its bias current. The effect of the operating band of the difference regulator 102.

The voltage control oscillator 103 generates a clock signal CLK according to the control voltage VCTRL. After the low voltage difference regulator 102 regulates the ground voltage, the jitter accompanying the clock signal CLK generated by the voltage control oscillator 103 will be inhibition. The voltage controlled oscillator 103 additionally receives the band select digital signal BS to change the bias current thereof to achieve the effect of changing the operating band of the voltage controlled oscillator 103. The circuit architecture of the low dropout regulator 102 and voltage controlled oscillator 103 will be discussed in the following paragraphs.

The charge pump 104 generates a control voltage VCTRL by transmitting a current I _cp to the low pass filter 105, wherein the current I _cp is adjusted by transmitting at least a portion of the band selection digital signal BS, such as two of the band selection digital signal BS. Yuan (ie BS[2:1]). Table 1 shows the current I _{cp of the} two bits of the corresponding frequency band selection digital signal BS. It should be noted that the variation value of the current I _cp of the two bits of the corresponding frequency band selection digital signal BS listed in Table 1 is only an example. It is not a limitation of the present invention. Table 1 <TABLE border="1"borderColor="#000000"width="85%"><TBODY><tr><td> BS2 </td><td> BS1 </td><td>I_cp</td></tr><tr><td> 0 </td><td> 0 </td><td> 1X </td></tr><tr><td > 0 </td><td> 1 </td><td> 2X </td></tr><tr><td> 1 </td><td> 0 </td><td> 3X </td></tr><tr><td> 1 </td><td> 1 </td><td> 4X </td></tr></TBODY></TABLE>

As shown in FIG. 1 , the low pass filter 105 includes a resistor R1 and capacitors C1 and C2, wherein one end of the resistor R1 is coupled to an end point N1 and the other end is coupled to one end of the capacitor C1. The other end of C1 is coupled to a supply voltage VDD. One end of the capacitor C2 is coupled to the terminal N2 and the other end is coupled to the supply voltage VDD. It should be noted that the circuit architecture of the low-pass filter 105 in this embodiment is merely an example, and is not a limitation of the present invention. Those skilled in the art should readily understand other circuits that can be used to implement the low-pass filter 105. Architecture.

Considering a clock signal generated by the conventional clock data recovery circuit (the clock data recovery circuit without the band selection circuit 101), assuming that the conventional clock data recovery circuit operates in a high frequency band, when the frequency of the clock signal is When lower, the strong current I _cp generated by the charge pump 104 (since the frequency band is higher, the current is stronger) causes a large change in the control voltage, resulting in a large change in the frequency of the clock signal; Assuming that the conventional clock data recovery circuit operates in a low frequency band, when the frequency of the clock signal is high, the weak current I _cp generated by the charge pump 104 (the current is weak due to the lower frequency band) represents the control voltage. VCTRL only changes in a small range, making the spread spectrum ability weak. The band selection circuit 101 proposed by the present invention can dynamically adjust the current I _cp , the bias current of the voltage control oscillator 103, and the bias current of the low drop voltage regulator 102 for different frequency bands to effectively solve the above problem. In detail, the low dropout regulator 102 and the voltage controlled oscillator 103 can respond to the low frequency band by reducing the bias current to operate in a low operating frequency band, and increase the bias current to operate in a manner of operating in a high operating frequency band. The high frequency band, detailed implementation details will be discussed in subsequent paragraphs.

It should be noted that the architecture of the band selection circuit 101 is not a limitation of the present invention, as long as the band selection circuit 101 can respond by adjusting the bias current of the low-dropout regulator 102 and the voltage-controlled oscillator 103 by generating the band-selection digital signal BS. The frequency of the control voltage VCTRL should be within the scope of the present invention. For example, the band selection circuit 101 can be implemented using a comparator and a logic gate circuit.

2 is a schematic diagram of a low dropout regulator 102 in a clock data recovery circuit 10 according to an embodiment of the invention. The low dropout regulator 102 includes a bias control circuit 201, an amplifier 202, and a transistor T1. And resistors R2 and R3, wherein the bias control circuit 201 is configured to receive at least a portion of the band select digital signal BS, such as two bits of the band select digital signal BS (ie, BS[2:1]) to control the flow Through the bias current I _{bias of} the amplifier 202, please note that in this embodiment, the transistor T1 is implemented by an N-metal-Oxide-Semiconductor Field-Effect Transistor (NMOS). However, this is merely an illustrative example and is not a limitation of the present invention. Table 2 shows the bias current _{Ibias of the} 2-bit corresponding to the band selection digital signal BS (i.e., BS[2:1]). Table 2 <TABLE border="1"borderColor="#000000"width="85%"><TBODY><tr><td> BS2 </td><td> BS1 </td><td>I_bias</td></tr><tr><td> 0 </td><td> 0 </td><td> 1X </td></tr><tr><td > 0 </td><td> 1 </td><td> 2X </td></tr><tr><td> 1 </td><td> 0 </td><td> 3X </td></tr><tr><td> 1 </td><td> 1 </td><td> 4X </td></tr></TBODY></TABLE>

The amplifier 202 is configured to generate an output voltage V _out according to a feedback voltage _Vfeed and a reference voltage VREF. As shown in FIG. 2, a source terminal of the transistor T1 is coupled to the ground voltage VSS and is extremely stable. Pressing the ground voltage VSSVCO, one end of the resistor R2 is coupled to the drain terminal of the transistor T1 and the other end is connected to one end of the resistor R3 and additionally coupled to an end point N _feed , and the other end of the resistor R2 It is coupled to the supply voltage VDD. The feedback voltage V _feed received by amplifier 202 is generated at the endpoint N _feed . The bias band current signal BS is used to adjust the bias current I _{bias to} adjust the operating band of the low dropout regulator 102 in response to different frequency bands of the clock data recovery circuit 100.

3 is a schematic diagram of a voltage controlled oscillator 103 in the clock data recovery circuit 10 according to an embodiment of the present invention. The voltage controlled oscillator 103 includes a current generating circuit 301 and a control circuit 302. The current generating circuit 301 A transistor T2 is included, and the control circuit 302 includes a plurality of transistors CT0-CT9. The transistor T2 in the current generating circuit 301 generates a reference current I _ref at a source terminal by using a gate terminal receiving control voltage VCTRL, and the plurality of transistors CT0-CT9 in the control circuit 302 are received as a plurality of current mirrors from the transistor T2. The reference current I _ref , the person skilled in the art should be able to understand the operation of the current mirror, the detailed description is omitted here to save space. It should be noted that the gate terminals of the transistors CT0-CT7 are coupled to the corresponding switches SW0-SW7, wherein the corresponding switches SW0-SW7 are controlled by the band selection digital signal BS. In detail, as shown in Table 3, the band selection digits are selected. The signal BS is first converted into a thermal code comprising 8 bits (band0-band7), wherein each bit of the thermal code is used to control the switches SW0-SW7 corresponding to the transistors CT0-CT7, respectively. . Table 3 <TABLE border="1"borderColor="#000000"width="85%"><TBODY><tr><td> Band Select Digital Signal</td><td> Hot Code</td></ Tr><tr><td> BS2 </td><td> BS1 </td><td> BS0 </td><td> Band7 </td><td> Band6 </td><td> Band5 </td><td> Band4 </td><td> Band3 </td><td> Band2 </td><td> Band1 </td><td> Band0 </td></tr><tr><td> 0 </td><td> 0 </td><td> 0 </td><td> 0 </td><td> 0 </td><td> 0 </td><td > 0 </td><td> 0 </td><td> 0 </td><td> 0 </td><td> 1 </td></tr><tr><td> 0 </td><td> 0 </td><td> 1 </td><td> 0 </td><td> 0 </td><td> 0 </td><td> 0 </td ><td> 0 </td><td> 0 </td><td> 1 </td><td> 1 </td></tr><tr><td> 0 </td><td > 1 </td><td> 0 </td><td> 0 </td><td> 0 </td><td> 0 </td><td> 0 </td><td> 0 </td><td> 1 </td><td> 1 </td><td> 1 </td></tr><tr><td> 0 </td><td> 1 </td ><td> 1 </td><td> 0 </td><td> 0 </td><td> 0 </td><td> 0 </td><td> 1 </td><Td> 1 </td><td> 1 </td><td> 1 </td></tr><tr><td> 1 </td><td> 0 </td><td> 0 </td><td> 0 </td><td> 0 </td><td> 0 </td><td> 1 </td><td> 1 </td><td> 1 </ Td><td> 1 </td><td> 1 </t d></tr><tr><td> 1 </td><td> 0 </td><td> 1 </td><td> 0 </td><td> 0 </td><Td> 1 </td><td> 1 </td><td> 1 </td><td> 1 </td><td> 1 </td><td> 1 </td></tr ><tr><td> 1 </td><td> 1 </td><td> 0 </td><td> 0 </td><td> 1 </td><td> 1 </ Td><td> 1 </td><td> 1 </td><td> 1 </td><td> 1 </td><td> 1 </td></tr><tr><Td> 1 </td><td> 1 </td><td> 1 </td><td> 1 </td><td> 1 </td><td> 1 </td><td> 1 </td><td> 1 </td><td> 1 </td><td> 1 </td><td> 1 </td></tr></TBODY></TABLE>

The voltage controlled oscillator 103 further includes a plurality of inverters inv1-inv6 driven by a bias current I _drive , wherein the bias current I _drive is composed of currents generated by the transistors CT0-CT7 when the thermal code is turned on. The more switches, the greater the bias current I _drive will be. By adjusting I _drive by using the band selection digital signal BS, the operating band of the oscillator 103 can be controlled for the voltage corresponding to the different frequency bands of the clock data recovery circuit 100. In addition, the control voltage VCTRL received by the transistor T2 can be adjusted by using the band selection digital signal BS to adjust the current I _cp , thereby adjusting the reference current I _ref , in other words, using the frequency band to select the digital signal. The BS changing current I _cp can also adjust the operating band of the voltage controlled oscillator 103 at the same time.

4 is a schematic diagram showing the operating frequency band of the oscillator 103 corresponding to the control voltage VCTRL and the voltage of the band selection digital signal BS according to an embodiment of the present invention. As shown in FIG. 4, when the control voltage VCTRL is adjusted from 0.3 volts to 1 At volts, the operating band of the voltage controlled oscillator 103 will vary over a small range, and as the band select digital signal BS changes, the operating band of the voltage controlled oscillator 103 will vary widely. In this embodiment, the control voltage VCTRL is adjusted within a range of 0.3 volts to 1 volt and the operating band of the voltage controlled oscillator 103 varies from 160 MHz to 1.8 GHz, but this is merely an example, not a limit.

It should be noted that the number of inverters used to generate the clock signal CLK and the number of transistors used to generate the bias current I _drive are merely illustrative and are not a limitation of the present invention. For example, the voltage controlled oscillator 103 can receive only a portion of the band select digital signal BS, such as 2 bits of the band select digital signal BS (ie, BS[2:1]), thus requiring only 4 powers. The crystal is used to generate the bias current I _drive , and these design variations are all within the scope of the present invention.

Briefly summarized, the present invention provides a clock data recovery circuit having a band selection circuit for reducing jitter on a clock signal. In detail, there is a band selection circuit 101 for a low frequency band, low dropout regulator 102. And the voltage controlled oscillator 103 can be correspondingly operated in a low operating frequency band, and for a high frequency band, the low dropout voltage regulator 102 and the voltage controlled oscillator 103 can be correspondingly operated in a high operating frequency band, thus, The jitter caused by the large change in the frequency of the clock signal can be reduced. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

<TABLE border="1" borderColor="#000000" width="85%"><TBODY><tr><td> 1' </td><td> preamplifier</td></tr>< Tr><td> 2' </td><td> Differential Single-Ended Conversion Circuit</td></tr><tr><td> 3' </td><td> Two-Dimensional Phase Detector </td></tr><tr><td> 4' </td><td> Phase Frequency Detector</td></tr><tr><td> 5' </td><td > Multiplexer</td></tr><tr><td> 6' </td><td> Lock Detector</td></tr><tr><td> 7' </td> <td> Divider</td></tr><tr><td> 10 </td><td> Clock Data Recovery Circuit</td></tr><tr><td> 101 </ Td><td> Band Selection Circuit</td></tr><tr><td> 102 </td><td> Low Dropout Regulator </td></tr><tr><td> 103 </td><td> Voltage Control Oscillator 103 </td></tr><tr><td> 104 </td><td> Charge Pump </td></tr><tr><td > 105 </td><td> low pass filter</td></tr><tr><td> VREF </td><td> reference voltage</td></tr><tr><td > VSS </td><td> Ground Voltage </td></tr><tr><td> VSSVCO </td><td> Regulated Ground Voltage </td></tr><tr><td > CLK </td><td> Clock Signal </td></tr><tr><td> VCTRL </td><td> Control Voltage</td></tr><tr><td> I_cp </td><td> current </td></tr><tr><td> N1 </td><td> endpoint </td></tr><tr><td> BS[2: 0] </td><td> Band selection signal</td></tr><tr><td> C1, C2 </td><td> Capacitance </td></tr><tr><td > R1, R2, R3 </td><td> Resistor </td></tr><tr><td> VDD </td><td> Supply Voltage </td></tr><tr>< Td> V_feed</td><td> feedback voltage</td></tr><tr><td> I_bias, I_drive</td><td> Bias current </td></tr><tr><td> V_out</td><td> Output voltage </td> </tr><tr><td> T1, T2, CT0-CT9 </td><td> transistor </td></tr><tr><td> 201 </td><td> bias Control circuit</td></tr><tr><td> 202 </td><td> Amplifier</td></tr><tr><td> Inv1-inv6 </td><td> Phaser</td></tr><tr><td> I_ref</td><td> Reference Current</td></tr><tr><td> SW0- SW7 </td><td> Switch</td></tr><tr><td> 301 </td><td> Current Generation Circuit</td></tr><tr><td> 302 < /td><td> Control Circuit</td></tr></TBODY></TABLE>

1 is a schematic diagram of a clock data recovery circuit according to an embodiment of the present invention. 2 is a schematic diagram of a low dropout voltage regulator in the clock data recovery circuit according to an embodiment of the invention. Figure 3 is a schematic diagram of a voltage controlled oscillator in the clock data recovery circuit in accordance with an embodiment of the present invention. Figure 4 is a schematic illustration of the operating frequency band of the oscillator controlled by the voltage corresponding to the control voltage and the band select digital signal in accordance with an embodiment of the present invention.

Claims (14)

A clock data recovery circuit includes: a charge pump for generating a control voltage; a band selection circuit coupled to the charge pump, wherein the band selection circuit is configured to use the control voltage and a reference voltage Generating a comparison result, and generating a frequency band selection digital signal according to the comparison result; a low dropout regulator (LDO) for regulating a ground voltage, wherein the low dropout voltage regulator receives the The frequency band selects at least a portion of the digital signal to adjust a bias current of an amplifier of the low dropout regulator to change an operating frequency band of the low dropout regulator; and a voltage-controlled oscillator (VCO) And generating a clock signal according to the control voltage, wherein the voltage control oscillator adjusts a bias current of the voltage control oscillator by receiving at least a portion of the frequency band selection digital signal to adjust the clock data recovery circuit An operating band. The clock data recovery circuit of claim 1, wherein the low dropout voltage regulator comprises: a bias control circuit for receiving at least a portion of the frequency selective digital signal to control flow through the low dropout regulator The bias current of the amplifier. The clock data recovery circuit of claim 1, wherein the low dropout voltage regulator receives a regulated ground voltage generated by the voltage controlled oscillator to regulate the ground voltage. The clock data recovery circuit of claim 1, wherein the voltage control oscillator comprises: a current generating circuit for receiving the control voltage to generate a reference current; and a control circuit for determining the reference current according to the reference current And selecting a digital signal from the frequency band to generate the bias current of the voltage controlled oscillator. The clock data recovery circuit of claim 4, wherein the voltage control oscillator adjusts the bias current of the voltage control oscillator by receiving at least a portion of the frequency band selection digital signal to adjust the clock data recovery circuit The step of operating the frequency band includes: receiving, by the control circuit, the frequency selective digital signal and generating the bias current according to the reference current and the frequency selective digital signal to adjust the operating frequency band of the clock data recovery circuit. The clock data recovery circuit of claim 5, wherein the adjusted operating frequency band of the clock data recovery circuit corresponds to one of a plurality of clock signal frequency ranges. The clock data recovery circuit of claim 1, wherein the voltage control oscillator adjusts the bias current of the voltage control oscillator by receiving at least a portion of the frequency band selection digital signal to adjust the clock data recovery circuit. The step of operating the frequency band includes: receiving, by the charge pump, at least a portion of the frequency selective digital signal to generate the control voltage to the current generating circuit of the voltage controlled oscillator; generating the reference current to the control according to the control voltage a circuit; generating the bias current according to the reference current; and adjusting the operating frequency band of the clock data recovery circuit according to the bias current. For example, the clock data recovery circuit of claim 1 further includes: a low pass filter coupled between the charge pump and the voltage controlled oscillator. A clock data recovery method applied to a clock data recovery circuit, comprising: generating a control voltage by using a charge pump; generating a comparison result according to the control voltage and a reference voltage, and generating a frequency band selection digit according to the comparison result Signaling: a low voltage drop regulator (LDO) is used to regulate a ground voltage, wherein the low dropout regulator receives at least a portion of the frequency selective digital signal to adjust the low dropout regulator a bias current of an amplifier to adjust an operating frequency band of the low dropout regulator; and a voltage-controlled oscillator (VCO) to generate a clock signal according to the control voltage, wherein the voltage The control oscillator adjusts a bias current of the voltage controlled oscillating circuit by receiving at least a portion of the frequency selective digital signal to adjust an operating frequency band of the clock data recovery circuit. The clock data recovery method of claim 9, wherein the low dropout voltage regulator receives a regulated ground voltage generated by the voltage controlled oscillator to regulate the ground voltage. The clock data recovery method of claim 9, further comprising: receiving the control voltage to generate a reference current; and generating the bias of the voltage controlled oscillator according to the reference current and the frequency band selecting the digit signal Voltage current. The clock data recovery method of claim 11, wherein the voltage control oscillator adjusts the bias current of the voltage control oscillator by receiving at least a portion of the frequency band selection digital signal to adjust the clock data recovery circuit The operating frequency band includes receiving the frequency band selection digital signal through a control circuit and generating the bias current according to the reference current and the frequency band selection digital signal to adjust the operating frequency band of the clock data recovery circuit. The clock data recovery method of claim 12, wherein the adjusted operating frequency band of the clock data recovery circuit corresponds to one of a plurality of clock signal frequency ranges. The clock data recovery method of claim 12, wherein the voltage control oscillator adjusts the bias current of the voltage control oscillator by receiving at least a portion of the frequency band selection digital signal to adjust the clock data recovery circuit The step of operating the frequency band includes: receiving, by the charge pump, at least a portion of the frequency selective digital signal to generate the control voltage to the current generating circuit of the voltage controlled oscillator; generating the reference current to the control according to the control voltage a circuit; generating the bias current according to the reference current; and adjusting the operating frequency band of the clock data recovery circuit according to the bias current.