TWI633686B - Light emitting diode and manufacturing method thereof - Google Patents

Abstract

A light emitting diode includes a carrier board, a wafer and a packaging material. The carrier board includes a conductive region and an insulating region. The conductive region has an upper surface and a lower surface. The insulating region covers a part of the conductive region. The conductive region includes at least one first contact region, which is located in a region of the lower surface of the conductive region that is not covered by the insulating region. There is a first distance between adjacent first contact regions. The conductive region also includes at least one second contact region, which is located in a region of the upper surface of the conductive region that is not covered by the insulating region. There is a second distance between adjacent second contact regions, wherein the first distance is greater than the second distance. The chip is electrically connected to the carrier board through the conductive region. The packaging material covers at least one surface of the wafer that is relatively far from the carrier board.

Description

Light emitting diode and manufacturing method thereof

The invention relates to a light emitting diode and a manufacturing method thereof, and in particular to a packaging structure of a light emitting diode and a manufacturing method thereof.

In order to meet the requirements of lightness, thinness, and shortness of electronic products, semiconductor packages, which are the core components of electronic products, have also developed in the direction of miniaturization. In recent years, the industry has developed a miniaturized semiconductor package with a Chip Scale Package (CSP), which is characterized in that the ratio of the package volume to the size of the light-emitting diode chip is not greater than 1.2 times. With this volume limitation, the distance between the electrodes provided on the bottom surface of the light emitting diode wafer will also become narrower. Because the distance between the electrodes on the bottom surface of the light-emitting diode chip of the conventional chip-size package (CSP) is too narrow, when soldering the chip-size package to other plates, it is easy to spill tin between the two electrodes and cause a short circuit, and Not conducive to the application of Surface Mount Technology (SMT). In addition, in addition to improving reliability, further improving the luminous efficiency of chip-size packages is also a goal constantly pursued by the industry.

The invention provides a light-emitting diode, which has better structural reliability and light-emitting efficiency.

The invention also provides a method for manufacturing a light emitting diode, which is used for manufacturing the above light emitting diode.

The light-emitting diode of the present invention includes a wafer, a carrier board, and a packaging material. The carrier board includes: a conductive region having an upper surface and a lower surface; an insulating region covering at least a portion of the conductive region; wherein the conductive region includes at least a first contact region in a region of the lower surface of the conductive region that is not covered by the insulating region There is a first distance between adjacent first contact areas; at least one second contact area is located in an area where the upper surface of the conductive area is not covered by the insulation area, and there is a second distance between adjacent second contact areas Pitch; wherein the first pitch is greater than the second pitch. The packaging material directly or indirectly covers part of the surface of the wafer.

In one embodiment, the packaging material of the light-emitting diode of the present invention is a light-transmitting material, including silicone, quartz, glass, light-transmitting ceramic, thermoplastic resin, and thermosetting resin. The packaging material may also include fluorescent substances or light scattering particles.

In an embodiment, in the light-emitting diode of the present invention, there is still a third gap between adjacent second contact regions, and the first gap is larger than the third gap, and the third gap is smaller than or equal to the second gap. .

In one embodiment, the light-emitting diode of the present invention includes a first insulating layer, a second insulating layer, and a third insulating layer in the insulating region of the carrier board. The second insulating layer is located between the first insulating layer and the third insulating layer. Between the layers, the first insulating layer has at least one first opening, the second insulating layer has at least one second opening, and the third insulating layer has at least one third opening. Part of the lower surface and part of the upper surface of the conductive region of the carrier board The first opening and the third opening are respectively exposed.

In another embodiment, the conductive region of the light-emitting diode of the present invention also includes a plurality of conductive layer structures, wherein adjacent two conductive layers are connected by at least one conductive via.

In another embodiment, the light-emitting diode of the present invention also includes a protective layer disposed on the carrier board and directly or indirectly surrounding the wafer. At least one side of the protective layer is substantially coplanar with at least one side of the carrier board.

In yet another embodiment, the light-emitting diode of the present invention has a packaging material directly or indirectly covering at least a portion of a surface of the wafer that is relatively far from the carrier board and at least a portion of the surface of the protective layer, and at least one side of the packaging material and the protective layer At least one side of is substantially coplanar.

In yet another embodiment, the packaging material of the light-emitting diode of the present invention may be partially disposed between the wafer and the protective layer.

In yet another embodiment, the distance between the surface of the wafer having an electrode of the light emitting diode of the present invention and the upper surface of the conductive region of the carrier is smaller than that of the other surface of the wafer having no electrode and the conductive region of the carrier Distance from the top surface.

In another embodiment, the wafer of the light-emitting diode of the present invention is disposed on the second contact region of the carrier board in a flip-chip bonding manner.

In another embodiment, the light-emitting diode of the present invention may include an electrostatic protection element disposed on a carrier board.

In another embodiment, the light emitting diode of the present invention may include a surface coating disposed on at least one of the upper surface and the lower surface of the conductive region of the carrier board.

In another embodiment, the second contact region and the first contact region of the conductive region of the light-emitting diode of the present invention are recessed in the insulating region, respectively.

The manufacturing method of the light-emitting diode of the present invention includes the following manufacturing steps: A carrier board is provided. At least one wafer is disposed on the carrier plate, and the wafer has a top surface and a bottom surface opposite to each other, wherein the top surface is far from the carrier plate. A release layer is attached on the top surface of the wafer, wherein the orthographic projection area of the release layer on the carrier is greater than or equal to the orthographic projection area of the wafer on the carrier. The carrier plate carrying the wafer and the release layer is inverted into a concave mold, so that the release layer is located at a bottom of the concave mold, and a gap is formed between a side surface of the wafer and an inner surface of the concave mold. A protective layer is formed in the gap on the side of the wafer. The concave mold and the release layer are removed to expose the top surface of the wafer and a surface of the protective layer, wherein the top surface of the wafer and the surface of the protective layer are substantially coplanar. A packaging material is directly or indirectly formed on the top surface of the wafer and the surface of the protective layer.

Based on the above, in the light-emitting diode of the present invention, the wafer is electrically connected to the carrier board through the conductive region, wherein the first distance between the first contact regions of the carrier board is greater than the second distance between the second contact regions, Therefore, when the light-emitting diode is soldered to other circuit boards through solder, the first contact area of the carrier board can increase the contact area between the light-emitting diode and the circuit board, and avoid the problem of short circuit caused by solder overflow.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic cross-sectional view of a light emitting diode according to an embodiment of the present invention. Please refer to FIG. 1. The light emitting diode 100a of this embodiment includes a carrier board 110a, a chip 130a, and a packaging material 140a. The carrier board 110a includes a conductive region 112a and an insulating region 114a. The conductive region 112a has an upper surface S1 and a lower surface S2. The insulating region 114a covers at least a part of the conductive region 112a. A part of the upper surface S1 of the conductive region 112a is not covered by the insulating region 114a, and is referred to as a second contact region CP (only two are schematically illustrated in FIG. 1). Part of the lower surface S2 is not covered by the insulating region 114a, and is referred to as a first contact region SP (only two are schematically shown in FIG. 1), and adjacent first contact regions SP have a first pitch P1 therebetween. The wafer electrodes 120a (two are schematically shown in FIG. 1) of the wafer 130a are in direct or indirect contact with the second contact regions CP of the conductive region 112a, respectively, wherein a second pitch P2 is provided between adjacent second contact regions CP. And the first pitch P1 is greater than the second pitch P2. The chip 130a is electrically connected to the carrier 110a through the chip electrode 120a. The encapsulating material 140a may directly or indirectly cover a part of the surface of the wafer 130a. In FIG. 1, the encapsulating material 140a covers a top surface 132a of the wafer 130a relatively far from the carrier board 110a.

In detail, the carrier board 110a of this embodiment is embodied as a single-layer metal substrate, wherein the insulating region 114a includes a first insulating layer 114a1, a second insulating layer 114a2, and a third insulating layer 114a3, and the conductive region 112a Is at least one conductive layer 112a1. The second insulating layer 114a2 is located between the first insulating layer 114a1 and the third insulating layer 114a3. The first insulating layer 114a1 has at least one first opening 115a1, and the second insulating layer 114a2 has at least one second opening 115a2. The three insulating layers 114a3 have at least one third opening 115a3. The conductive region 112a is located in the second opening 115a2 and is substantially flush with the second insulating layer 114a2. The conductive region 112a has an upper surface S1 and a lower surface S2, and the first opening 115a1 exposes a portion of the lower surface S2 of the conductive region 112a. And the third opening 115a3 exposes a part of the upper surface S1 of the conductive region 112a. The conductive region 112a and the second insulating layer 114a2 are located substantially on the same horizontal plane. Here, there is a second pitch P2 between adjacent second contact regions CP and a first pitch P1 between adjacent first contact regions SP, where the first pitch P1 is greater than the second pitch. The material of the first insulating layer 114a1, the second insulating layer 114a2, and the third insulating layer 114a3 may be the same or different, and the material of the conductive region 112a may be copper foil, silver, gold, aluminum, or other metal materials having electrical conductivity and thermal conductivity. .

As shown in FIG. 1, the wafer electrode 120 a of this embodiment is located on a bottom surface 134 a of the wafer 130 a which is relatively far away from the top surface 132 a. The wafer 130 a is connected to the conductive region 112 a of the carrier plate 110 a by flip-chip bonding through the wafer electrode 120 a. Electrical connection. In other words, the distance between the bottom surface 134a of the wafer 130a and the upper surface S1 of the conductive region 112a is smaller than the distance between the top surface 132a of the wafer 130a and the upper surface S1 of the conductive region 112a. Here, the wafer 130a is, for example, a blue light emitting diode wafer, a red light emitting diode wafer, a white light emitting diode wafer, or an ultraviolet light emitting diode wafer.

In order to prevent the conductive region 112a of the carrier board 110a from being oxidized or wet, the light emitting diode 100a of this embodiment may further include, for example, at least one first surface coating layer 150a or at least one second surface coating layer 160a. The first surface coating layer 150a is disposed in the second contact region CP of the conductive region 112a and directly contacts the upper surface S1 of the conductive region 112a. The first surface coating layer 150a is located between the wafer electrode 120a and the conductive region 112a. The second surface coating layer 160a is disposed in the first contact region SP of the conductive region 112a and directly contacts the lower surface S2 of the conductive region 112a. Here, the materials of the first surface coating layer 150a and the second surface coating layer 160a are selected from metal materials that can facilitate subsequent solid-state bonding, such as silver, gold, gold tin, and nickel silver (Ni / Ag). , Nickel-palladium (Ni / Pt / Au) plating or other appropriate metals or alloys.

As shown in FIG. 1, since the thickness of the first surface coating layer 150a in this embodiment is smaller than the thickness of the third insulating layer 114a3, that is, the second contact region CP is recessed in the third insulating layer 114a3, so when the wafer electrode 120a is When in direct or indirect contact with the second contact region CP of the conductive region 112a, electrical connection between the two wafer electrodes 120a due to solder overflow can be avoided, thereby causing a short circuit problem. The solder is, for example, a gold ball, a solder paste, a eutectic bonding material, or an anisotropic conductive paste. Similarly, since the thickness of the second surface coating layer 160a in this embodiment is smaller than the thickness of the first insulating layer 114a1, that is, the first contact region SP is recessed in the first insulating layer 114a1, so when the light emitting diode 100a is borrowed When soldering to other circuit boards (not shown) by solder, the problem of solder overflowing to the adjacent first contact area SP and causing a short circuit can be avoided.

In addition, the light emitting diode 100a of this embodiment may further include a protective layer 170a, wherein the protective layer 170a is disposed on the carrier board 110a and is disposed directly or indirectly around the wafer 130a. Here, the protective layer 170a directly contacts the peripheral surface 136a of the wafer 130a, and at least one side of the protective layer 170a is substantially coplanar with at least one side of the carrier board 110a. Here, the material of the protective layer 170a is, for example, silicon rubber or epoxy resin and is doped with one of titanium dioxide, silicon dioxide, zirconia, boron nitride, or a combination thereof. The protective layer 170a may also have a reflection function, which may reflect more than 30%, preferably 50% or more, and more than 70% of the light from the wafer 130a.

In addition, please refer to FIG. 1 again. The packaging material 140a of this embodiment is a light-transmitting material, which may include silicone, quartz, glass, light-transmitting ceramics, thermoplastic resins, thermosetting resins, or fluorescent materials or light-scattering particles. The packaging material 140a directly or indirectly covers at least a portion of the top surface 132a and at least a portion of the surface of the wafer 130a that are relatively far from the carrier board 110a and the protective layer 170a. Here, the fluorescent substance is, for example, an aluminate garnet-based material, a silicate-based material, a nitride-based material, a phosphate-based material, a sulfide-based material, or a sulfonate, and the like is not limited thereto. More specifically, the phosphor can be selected from one or more of the following groups: β-SiAlON, Sr5 (PO4) 3Cl: Eu2 +, (Sr, Ba) MgAl10O17: Eu2 +, (Sr, Ba ) 3MgSi2O8: Eu2 +, SrAl2O4: Eu2 +, SrBaSiO4: Eu2 +, CdS: In, CaS: Ce3 +, Y3 (Al, Gd) 5O12: Ce3 +, (Y, Gd) 3Al5O12: Ce3 +, Y3Al5O12: Ce3 +, Ya 5O12: Ce3 +, Lu3Al5O12: Ce3 +, (Y, Lu) 3Al5O12: Ce3 +, Lu3 (Al, Ga) 5O12: Ce3 +, (Y, Lu) 3 (Al, Ga) 5O12: Ce3 +, Ca3Sc2Si3O12: Ce3 +, SrSiON: Eu2 +, ZnS: Al3 +, Cu +, CaS: Sn2 +, CaS: Sn2 +, F, CaSO4: Ce3 +, Mn2 +, LiAlO2: Mn2 +, BaMgAl10O17: Eu2 +, Mn2 +, ZnS: Cu +, Cl-, Ca3WO6: U, Ca3SiO4Cl2: Eu2 +, SrxBayClzO2 / 2: Ce3 +, Mn2 + (X: 0.2, Y: 0.7, Z: 1.1), Ba2MgSi2O7: Eu2 +, Ba2SiO4: Eu2 +, Ba2Li2Si2O7: Eu2 +, ZnO: S, ZnO: Zn, Ca2Ba3 (PO4) 3Cl: Eu2 +, BaAl2O4: Eu2 +, SrGa2S4: Eu2 +, ZnS: Eu2 +, Ba5 (PO4) 3Cl: U, Sr3WO6: U, CaGa2S4: Eu2 +, SrSO4: Eu2 +, Mn2 +, ZnS: P, ZnS: P3-, Cl-, ZnS: Mn2 +, CaS: Yb2 +, Cl, Gd3Ga4O12: Cr3 +, CaGa2S4: Mn2 +, Na (Mg, Mn) 2 LiSi4O10F2: Mn, ZnS: Sn2 +, Y3Al5O12: Cr3 +, SrB8O13: Sm2 +, MgSr3Si2O8: Eu2 +, Mn2 +, _-SrOS: CdS ZnSe: Cu +, Cl, ZnGa2S4: Mn2 +, ZnO: Bi3 +, BaS: Au, K, ZnS: Pb2 +, ZnS: Sn2 +, Li +, ZnS: Pb, Cu, CaTiO3: Pr3 +, CaTiO3: Eu3 +, Y2O3: Eu3 +, (Y , Gd) 2O3: Eu3 +, CaS: Pb2 +, Mn2 +, YPO4: Eu3 +, Ca2MgSi2O7: Eu2 +, Mn2 +, Y (P, V) O4: Eu3 +, Y2O2S: Eu3 +, SrAl4O7: Eu3 +, CaYAlO4: Eu3 +, O3 +, O3 + : Eu3 +, Sm3 +, (Sr, Ca, Ba, Mg) 10 (PO4) 6Cl2: Eu2 +, Mn2 +, Ba3MgSi2O8: Eu2 +, Mn2 +, ZnS: Mn2 +, Te2 +, Mg2TiO4: Mn4 +, K2SiF6: Mn4 +, SrS1: Eu2 +, 23K0.42Eu0.12TiSi4O11, Na1.23K0.42Eu0.12TiSi5O13: Eu3 +, CdS: In, Te, CaAlSiN3: Eu2 +, CaSiN3: Eu2 +, (Ca, Sr) 2Si5N8: Eu2 +, and Eu2W2O7. The above-mentioned packaging material 140a is a light-transmitting material, and is preferably an epoxy-based resin composition or a siloxane-based resin composition. In other embodiments not shown, the packaging material may also be doped with a diffusing agent, a thickener, an antioxidant, or other materials that can increase the light emitting efficiency or uniformity of the wafer 130a, which still belongs to the protection of the present invention. Range.

In short, the wafer 130a of this embodiment is electrically connected to the carrier plate 110a through the wafer electrode 120a, wherein the first distance P1 between the first contact areas SP of the carrier plate 110a is greater than the second distance between the second contact areas CP The pitch P2, therefore, when the light-emitting diode 100a is soldered to the circuit board, it can provide a wider electrical connection area to avoid short-circuit problems caused by solder overflow during bumping. In addition, the first contact region SP of the carrier plate 110a with a wide cross-sectional area can also increase the contact area between the light emitting diode 100a and the solder, thereby improving the heat dissipation effect and soldering stability of the carrier plate 110a. Moreover, because the first contact region SP can be set to be recessed in the insulating region 114a, the problem of short circuit caused by solder overflow can be further avoided. Therefore, the light emitting diode 100a of this embodiment can be applied to a micro light emitting diode (micro LED) or a chip scale package.

It must be noted here that the following embodiments use the component numbers and parts of the foregoing embodiments, in which the same reference numerals are used to indicate the same or similar components, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments are not repeated.

FIG. 2 is a schematic cross-sectional view of a light emitting diode according to another embodiment of the present invention. Please refer to FIG. 1 and FIG. 2 at the same time. The light-emitting diode 100b of this embodiment is similar to the light-emitting diode 100a of FIG. 1. The difference between the two is that the packaging material 140b of this embodiment directly or indirectly covers the chip 130a and packages. A partial area of the material 140b is located between the wafer 130a and the protective layer 170b.

FIG. 3 is a schematic cross-sectional view of a light emitting diode according to another embodiment of the present invention. Please refer to FIG. 2 and FIG. 3 at the same time. The light-emitting diode 100c of this embodiment is similar to the light-emitting diode 100b of FIG. 2. The difference between the two is that in this embodiment, the two wafer electrodes 120c are respectively located on the bottom surface of the wafer 130c. 134a and the top surface 132a. That is, the wafer 130c is, for example, a vertical wafer, and the wafer electrode 120c on the bottom surface 134a is directly disposed on the carrier board 110a, for example. The other chip electrode 120c on the top surface 132a is electrically connected to the carrier board 110a through a wire W1.

FIG. 4 is a schematic cross-sectional view of a light emitting diode according to another embodiment of the present invention. Please refer to FIG. 3 and FIG. 4 at the same time. The light-emitting diode 100d of this embodiment is similar to the light-emitting diode 100c of FIG. 3. The difference between the two is that the wafer 130d of this embodiment is, for example, a horizontal wafer, and the wafer 130d The two wafer electrodes 120d are located on the top surface 132a of the wafer 130d, and the two wafer electrodes 120d are electrically connected to the carrier board 110a through the wires W2, respectively.

FIG. 5 is a schematic cross-sectional view of a light emitting diode according to another embodiment of the present invention. Please refer to FIG. 1 and FIG. 5 at the same time. The light emitting diode 100e of this embodiment is similar to the light emitting diode 100a of FIG. 1. The difference between the two is that the conductive region 112b of the carrier plate 110b of this embodiment includes a plurality of conductive layers. Layer structure, and adjacent two conductive layers are connected by at least one conductive via 112b2. In detail, the insulating region 114b of the carrier board 110b in this embodiment includes a first insulating layer 114b1, a second insulating layer 114b2, and a third insulating layer 114b3. The second insulating layer 114b2 is located between the first insulating layer 114b1 and the first insulating layer 114b1. Between the third insulating layers 114b3. The conductive region 112b of the carrier board 110b includes at least one first conductive layer 112b1, at least one conductive via 112b2, and at least one second conductive layer 112b3. The first conductive layer 112b1 and the second conductive layer 112b3 are located on opposite sides of the second insulating layer 114b2, respectively. The conductive via 112b2 penetrates the second insulating layer 114b2 and is electrically connected to the first conductive layer 112b1 and the second conductive layer 112b3. The first conductive layer 112b1 has a lower surface S2, and the second conductive layer 112b3 has an upper surface S1. The insulating region 114b covers at least a portion of the conductive region 112b. A portion of the upper surface S1 of the conductive region 112b is not covered by the insulating region 114b, and is referred to as a second contact region CP. A portion of the lower surface S2 of the conductive region 112b is not covered by the insulating region 114b. Is a first contact region SP, wherein a first pitch P1 is formed between adjacent first contact regions SP. The wafer electrode 120a of the wafer 130a is in direct or indirect contact with the second contact region CP of the conductive region 112b, wherein a second pitch P2 is formed between adjacent second contact regions CP, and the first pitch P1 is greater than the second pitch P2. . The chip 130a is electrically connected to the carrier 110b through the chip electrode 120a.

Since the first pitch P1 between the first contact regions SP of the carrier board 110b in this embodiment is greater than the second pitch P2 between the second contact regions CP, it can be avoided when the light emitting diode 100e is soldered to other circuit boards. Short circuit caused by solder overflow when hitting parts. In addition, the first contact region SP of the carrier board 110b with a wide cross-sectional area can also increase the contact area between the light emitting diode 100e and the circuit board, thereby improving the heat dissipation effect and soldering stability of the carrier board 110b. Furthermore, since the first contact region SP can be set to be recessed in the insulating region 114b, the problem of short circuit caused by solder overflow can be further avoided. Therefore, the light emitting diode 100e of this embodiment can be applied to a micro light emitting diode (micro LED) or a chip scale package.

FIG. 6 is a schematic cross-sectional view of a light emitting diode according to another embodiment of the present invention. Please refer to FIG. 5 and FIG. 6 at the same time. The light-emitting diode 100f of this embodiment is similar to the light-emitting diode 100e of FIG. 5. The difference between the two is that the packaging material 140b of this embodiment directly or indirectly covers the chip 130a and a part Located between the wafer 130a and the protective layer 170b. That is, the packaging material 140b of this embodiment is filled in the gap between the chip 130a and the protective layer 170b, and the protective layer 170b directly contacts the packaging material 140b.

FIG. 7A is a schematic cross-sectional view of a light emitting diode according to another embodiment of the present invention. FIG. 7B is a schematic top view of a carrier plate of the light-emitting diode of FIG. 7A. FIG. 7C is a schematic cross-sectional view taken along the line I-I of FIG. 7B. It should be noted that the carrier plate in FIG. 7A is a cross section taken along the line II-II in FIG. 7B. Please refer to FIG. 1 and FIG. 7A at the same time. The light-emitting diode 100 g of this embodiment is similar to the light-emitting diode 100 a of FIG. 1. The difference between the two is that the insulation region 114 g of the carrier plate 110 g of this embodiment includes a first The insulating layer 114g1 and a second insulating layer 114g2. The conductive region 112g includes at least one first conductive layer 112g1, at least one second conductive layer 112g2, and an extended pattern 113g. The first insulating layer 114g1 has at least one first opening 115g1. The first conductive layer 112g1 has a lower surface S2 and is located in the first opening 115g1 to form a first contact region SP. The second insulating layer 114g2 has at least one second opening 115g2. The second conductive layer 112g2 has an upper surface S1, is disposed on the first conductive layer 112g1, and is located in the second opening 115g2 to form a second contact region CP.

Please refer to FIG. 7B and FIG. 7C. FIG. 7B illustrates a plurality of element regions, and the dashed box in the figure only illustrates a range of one element region. The extended pattern 113g is connected to the second conductive layer 112g2 in the different element region, but the extended pattern 113g is not connected to the second conductive layer 112g2 in the same element region. However, in other embodiments, the extended pattern 113g may also be connected to the first conductive layer 112g1 of different element regions, or penetrate the first insulating layer 114g1 and the second insulating layer 114g2, which still belongs to the scope of the present invention. The structural shapes of the conductive region 112g and the extended pattern 113g can be formed by stamping, etching, and the like, and the material of the insulating region 114g can be a solder resist commonly used in semiconductors, which has suitable heat resistance and processability. In addition, a reflective material such as titanium dioxide, silicon dioxide, zirconia, boron nitride, or any combination of the foregoing may be added to the 114 g element of the insulating region to improve the light emitting effect of 100 g of the light-emitting diode. Of course, in other embodiments not shown, a surface coating (not shown) may be added on the upper surface S1 or the lower surface S2 of the conductive region 112g to prevent oxidation or moisture of the conductive region 112g.

Please refer to FIG. 7A again. The second conductive layer 112g2 of this embodiment protrudes from the second insulating layer 114g2, and the wafer electrode 120a directly or indirectly contacts the second conductive layer 112g2, or, for example, directly contacts the second conductive layer 112g2. Surface coating (not shown). Here, the interval P1 between the first contact regions SP is larger than the interval P3 between the second contact regions CP, and the interval P1 between the first contact regions SP is also larger than the interval P2 between the wafer electrodes. The orthographic projection of the second conductive layer 112g2 on the first conductive layer 112g1 at least partially overlaps the first conductive layer 112g1. As shown in FIG. 7A, the first conductive layer 112g1 and the second conductive layer 112g2 are stacked in a step shape. The packaging material 140g covers, for example, the wafer 130a directly or indirectly. Here, at least one side of the packaging material 140g and at least one side of the carrier board 110g are coplanar.

FIG. 8 is a schematic cross-sectional view of a carrier board according to another embodiment of the present invention. Please refer to FIG. 7A and FIG. 8 at the same time. The carrier board 110h of this embodiment is similar to the carrier board 110g of FIG. 7A. The difference between the two is that the second conductive layer 112h2 of the conductive region 112h and the first conductive layer 112h1 of this embodiment The orthographic projection completely overlaps the first conductive layer 112h1. The width of the second opening 115h2 of the second insulating layer 114h2 is larger than the width of the first opening 115h1 of the first insulating layer 114h1, so that the width of the second conductive layer 112h2 is greater than the width of the first conductive layer 112h1, thereby forming the upper width and the lower width. The narrow conductive region 112h can make the insulating region 114h have a good coupling force when covering the conductive region 112h, and reduce the occurrence of the loss of the conductive region 112h and the insulating region 114h.

9A is a schematic top view of a carrier board according to an embodiment of the present invention. FIG. 9B is a schematic cross-sectional view taken along line A-A of FIG. 9A. FIG. 9C is a schematic cross-sectional view taken along line B-B of FIG. 9A. Please refer to FIG. 8, FIG. 9A, FIG. 9B, and FIG. 9C at the same time. The carrier board 110 j in this embodiment is similar to the carrier board 110 h in FIG. 8. The difference between the two is that the insulation region 114 j of the carrier board 110 j in this embodiment includes In addition to the first insulating layer 114j1 and the second insulating layer 114j2, a third insulating layer 114j3 is further disposed on a portion of the second conductive layer 112h2 and the second insulating layer 114j2. Part of the upper surface S1 of the second conductive layer 112h2 is not covered by the third insulating layer 114j3. The height of the second insulating layer 114j2 between the second contact areas CP will not be higher than the height of the second contact area CP, which can avoid subsequent wafer bonding. Is blocked by the insulating region 114j.

FIG. 10 is a schematic cross-sectional view of a light emitting diode according to another embodiment of the present invention. Please refer to FIG. 7A and FIG. 10 at the same time. The light-emitting diode 100k of this embodiment is similar to the light-emitting diode 100g of FIG. 7A. The difference between the two is that the light-emitting diode 100k of this embodiment further includes a protective layer 170k. It is arranged on the carrier board 110g and is directly or indirectly arranged around the chip 130a. The packaging material 140k directly or indirectly covers the wafer 130a. Here, at least one side of the protective layer 170k is coplanar with at least one side of the carrier plate 110g.

FIG. 11 is a schematic cross-sectional view of a light emitting diode according to another embodiment of the present invention. Please refer to FIG. 7A and FIG. 11 at the same time. The light-emitting diode 100m of this embodiment is similar to the light-emitting diode 100g of FIG. 7A. The difference between the two is that the light-emitting diode 100m of this embodiment further includes a protective layer 170m. It is arranged on the carrier board 110g and is directly or indirectly arranged around the chip 130a. The protective layer 170m covers at least a peripheral surface 136m of the wafer 130m, a part of the upper surface S1 of the second conductive layer 112g2, and a first surface 111g of the carrier board 110g. There is a gap S between the wafer electrode 120a and the second conductive layer 112g2, and the packaging material 140m directly or indirectly covers the top surface 132a and the protective layer 170m of the wafer 130a, and at least one side of the packaging material 140m and at least the protective layer 170m One side or at least one side of the carrier board 110g is coplanar.

FIG. 12A is a schematic top view of a light emitting diode according to another embodiment of the present invention. FIG. 12B is a schematic partial perspective view of the light-emitting diode of FIG. 12A. Please refer to FIG. 5, FIG. 12A and FIG. 12B at the same time. The light-emitting diode 100n of this embodiment is similar to the light-emitting diode 100e of FIG. 5. The difference between the two is that the light-emitting diode 100n of this embodiment has a structure before being singulated, and includes a plurality of wafers 130a. They are respectively arranged on the component areas of the carrier board 110b. The carrier board 110b includes a plurality of first connection layers 113b1 and second connection layers 113b2. The first connection layer 113b1 is used to connect, for example, a positive conductive second conductive layer 112b3 in different device regions, and the second connection layer 113b2 is used to The first conductive layer 112b1, for example, which is electrically negative, is connected to different device regions. In detail, the second conductive layers 112b3 in the respective element regions in the same row (for example, the first row) are connected to each other through the first connection layer 113b1, and are finally electrically connected to the positive electrodes in the same row (for example, the first row). Test point E1. The first conductive layers 112b1 in the respective element regions in the same column (for example, the first column) are connected to each other through the second connection layer 113b2, and are finally electrically connected to the negative electrode test point E2 in the same column (for example, the first column). A second conductive layer 112b3 connected to each other through the first connection layer 113b1 under each chip 130a is located in an oblique diagonal direction of the first conductive layer 112b1 connected to each other through the second connection layer 113b2. The arrangement extending direction of the positive electrode test point E1 is perpendicular to the arrangement extending direction of the negative electrode test point E2.

FIG. 12B is a schematic partial perspective view of the light-emitting diode of FIG. 12A. For easier explanation, please refer to FIG. 12B. Since the above-mentioned carrier plate with a double-layer metal substrate has two upper and lower conductive layers, the first connection layer 113b1 used for positive electrode interconnection and the second connection layer 113b2 used for negative electrode interconnection can be respectively disposed on the second insulation. On the opposite sides of the layer 114b2, and the first connection layer 113b1 is located obliquely above the second connection layer 113b2, so that the second conductive layer 112b3 connected to the positive electrode of the different element region and the first conductive layer 112b1 connected to the negative electrode can be staggered from each other. And avoid the problem of short circuit. In this way, the circuit configuration of the double-layer metal substrate is more convenient for electrically connecting the conductive layer layers of adjacent element regions in the same column or the same row.

With the design of the carrier board with the double-layer metal substrate, the color of the light emitted from the wafer 130a in each element area can be measured electrically at the same time when the phosphor coating operation is performed in the manufacturing process. And brightness, you can know whether the coating condition of the fluorescent powder meets the requirements, in order to determine whether to stop or continue the above coating operation. The foregoing fluorescent powder coating can be spray coating, dispensing or covering the fluorescent patch or Other phosphor packaging methods. For example, when you want to know the status of the phosphor coating on the wafer 130a located in the component area, you can press the positive electrode probe and the negative electrode probe to one of the positive electrode test points E1 and one of the negative electrode test points, respectively. E2, the phosphor coating status of the wafer 130a at the relative position can be obtained. After the phosphor coating process or other phosphor packaging process is completed, singulation can be performed to obtain a plurality of independent light-emitting diodes, as shown in the light-emitting diode 100e of FIG. 5. It is worth mentioning that after cutting the light-emitting diode, electrical residues will be left on at least one side of the light-emitting diode 100e. For example, in this embodiment, a light-emitting diode will remain on one side of the light-emitting diode 100n. The two electrical residues of the first connection layer 113b1 and the second connection layer 113b2 (shown in FIG. 12A) used to connect adjacent element regions are left below, and are left on the opposite side of the light emitting diode 100n. An electrical residual point of the second connection layer 113b2 adjacent to the adjacent element region is connected. In short, each light-emitting diode 100n after cutting has at least a plurality of electrical residual points, and these electrical residual points may be located on the same horizontal plane or different horizontal planes, and the positions of the electrical residual points are not limited here.

In addition, in this embodiment, the reason for placing the electrical measurement points (that is, the positive electrode test point E1 and the negative electrode test point E2) on the front surface of the carrier plate having a double-layer metal substrate is that whether it has a double-layer metal substrate or a single-layer metal The thickness of the carrier plate of the substrate is very thin. Therefore, during the manufacturing process, an additional layer of a relatively hard carrier substrate needs to be adhered to the back of the carrier plate having a single / double-layer metal substrate in order to facilitate subsequent processes without As for damaging the substrate during the manufacturing process, yield problems are caused. In addition, since the current spot measurement is performed from the back of the integrated circuit board, in the case where a carrier substrate (not shown) is attached to the back of a carrier board with a single / double-layer metal substrate, the It is not feasible to perform spot measurement on the back surface of the carrier plate of the multilayer metal substrate. Therefore, if spot measurement is to be performed on a carrier board on which a chip is configured, the electrical measurement points need to be extended to the front side of the carrier board so that it can be spot-tested from the front side of the carrier board. Since the circuit configuration of the carrier board with a double-layer metal substrate in this embodiment can realize the establishment of a front measurement point on the front surface of the carrier board, it can meet the requirements of subsequent procedures that need to perform spot measurement. In addition, after the above packaging process is completed, the carrier substrate can be removed, and then the subsequent singulation step is performed.

FIG. 13 is a schematic top view of a light emitting diode according to another embodiment of the present invention. Please refer to FIG. 12A and FIG. 13 at the same time. The light-emitting diode 100p of this embodiment is similar to the light-emitting diode 100n of FIG. 12A. The difference between the two is that the arrangement and extension direction of the positive test points E1 'is parallel to the negative test, for example. The arrangement direction of the point E2 '. In other words, different arrangement directions of the positive test points E1, E1 'and the negative test points E2, E2' can be selected according to different circuit configuration requirements.

14A is a schematic top view of a carrier board according to another embodiment of the present invention. FIG. 14B is a schematic bottom view of the carrier board of FIG. 14A. Please refer to FIG. 14A and FIG. 14B at the same time. The carrier board 110q in this embodiment may be a single-layer metal substrate or a double-layer metal substrate, which is not limited herein. The third distance P3 between the second contact regions CP of the conductive region 112q of the carrier board 110q is, for example, 200 micrometers. By matching the insulating region 114q and the conductive region 112q, the first distance between the first contact regions SP can be made. P1 is adjusted to, for example, 250 micrometers, but the adjustment range of the pitch is not limited to this.

15A and 15B are schematic top views of a carrier board according to another embodiment of the present invention. Please refer to FIG. 14A, FIG. 15A, and FIG. 15B at the same time. The carrier board 110r of this embodiment is similar to the carrier board 110q of FIG. 14A. The difference between the two is that at least one electrostatic protection element is disposed on the carrier board 110r of this embodiment. 180a, where the electrostatic protection element 180a is, for example, a Zener diode or a transient suppression diode (TSV). The wafer, the carrier board and the electrostatic protection element according to the embodiment of the present invention may present a combination of quadrangles with different lengths, and the present invention is not limited thereto.

It is worth mentioning that the shape of the part of the conductive region 112q in FIG. 14A, FIG. 14B, and FIG. 15A may have a beveled edge shape. However, this shape with a beveled edge is only for the purpose of identifying positive and negative electrodes. The shape may also be designed as The square (such as the conductive region 112s of FIG. 15B) or other shapes is not limited in the present invention.

With the design of the carrier plates 110a, 110b, 110g, 110h, 110j, 110q, 110r, and 110s of this embodiment (such as the design of a single-layer metal substrate or a double-layer metal substrate), it is convenient to package a wafer size without a substrate. The effect of a relatively short chip electrode pitch is to expand the pitch of the first contact area by using a carrier plate with a single / double-layer metal substrate, so that the light emitting diodes 100a, 100b, 100c, and 100d are subsequently expanded. , 100e, 100f, 100g, 100k, 100m, 100n, 100p when soldering to other subsequent circuit boards can avoid short-circuit problems caused by tin overflow. In addition, the design of the carrier plates 110a, 110b, 110g, 110h, 110j, 110q, 110r, and 110s can maintain or further improve the contact area with the solder during subsequent soldering, heat dissipation effect, and reliability. In addition, the carrier boards 110r and 110s of this embodiment may also be provided with an electrostatic protection element 180a, which can protect the wafers 130a, 130c, and 130d from electrostatic damage. In addition, the light-emitting diodes 100n and 100p of this embodiment may further have positive electrode test points E1, E1 'and negative electrode test points E2, E2' on the front surface of the carrier plate 110b, so as to facilitate electrical measurement during the manufacturing process.

16A to 16F are schematic cross-sectional views illustrating a method for manufacturing a light emitting diode according to an embodiment of the present invention. The manufacturing method of the light-emitting diode of this embodiment includes the following manufacturing steps. First, referring to FIG. 16A, a carrier board 110t is provided. Here, the carrier board 110t may be, for example, the above-mentioned carrier boards 110a, 110b, 110g, 110h, 110j, 110q, 110r, and 110s, which may be single-layer metal substrates, double-layer metal substrates, or removable carriers. Substrate or substrate that does not need to be removed. In the following, a substrate that does not need to be removed is taken as an illustrative example, but the present invention is not limited thereto.

Next, please refer to FIG. 16A again, at least one wafer 130t is disposed on the carrier board 110t, wherein the wafer 130t has a top surface 132t and a bottom surface 134t opposite to each other, and the bottom surface 134t of the wafer 130t is disposed on the carrier board 110t, and the top The surface 132t is far from the carrier plate 110t. As shown in FIG. 16A, it is shown that a plurality of wafers 130t are arranged on a carrier board 110t. In the embodiment of the present invention, a single wafer may also be used. Here, the wafer 130t may be a flip-chip light emitting diode wafer, a vertical light emitting diode wafer, or a horizontal light emitting diode wafer, which is not limited herein.

16B, attach a release layer 10 on the top surface 132t of the wafer 130t, wherein the orthographic projection area of the release layer 10 on the carrier plate 110t is greater than or equal to the orthographic projection of the wafer 130t on the carrier plate 110t. area. Here. The release layer 10 is, for example, a thermal release adhesive layer. Of course, in other embodiments, the release layer 10 may also have other characteristics that will not damage the adjacent structure when it is removed.

Next, referring to FIG. 16C, the carrier plate 130t carrying the wafer 130t and the release layer 10 is inverted in a concave mold 30, so that the release layer 10 is located at the bottom 32 of the concave mold 30, and the wafer 130t and the inner surface of the concave mold 30 (Such as the first peripheral surface 34 and the second peripheral surface 38).

Next, please refer to FIG. 16C again, and attach a backing adhesive 20 on the surface of the carrier board 110t relatively far from the chip 130t. Next, in FIG. 16D, a protective layer 170t is formed on the side of the wafer 130t. 16E, the concave mold 30, the adhesive 20, and the release layer 10 are removed to expose the top surface 132t of the wafer 130t and a surface 172t of the protective layer 170t to expose the top surface 132t of the wafer 130t and the protective layer. The surface 172t of 170t, wherein the top surface 132t of the wafer 130t and the surface 172t of the protective layer 170t are substantially coplanar. Here, the step of removing the release layer 10 includes heating the release layer 10, wherein the temperature of heating the release layer 10 is between 150 degrees and 270 degrees, and the time of heating the release layer 10 is between 10 seconds and 3 minutes. Since the release layer 10 of this embodiment is embodied as a thermal release adhesive layer, when the thermal release adhesive layer is to be removed, it is only necessary to heat the carrier plate 110t to more than 100 degrees, for example, 170 degrees up and down for about 3 minutes Left or right, or for example, a higher temperature can be used and the thermal release adhesive layer can be removed in just a few seconds. Because the thermal release adhesive layer loses its viscosity at high temperature, the thermal release adhesive layer can be easily removed without hurting the wafer 130t and the protective layer 170t that has been formed.

In addition, in other embodiments, after the thermal release adhesive layer is removed, ethyl acetate can also be used to remove the overflow adhesive residue of the thermal release adhesive layer and / or use alcohol to remove other residues.

Finally, in FIG. 16F, a packaging material 140t is directly or indirectly formed on the top surface 132t of the wafer 130t and the surface 172t of the protective layer 170t. Here, the encapsulating material 140t is, for example, that the encapsulating material is a light-transmitting material, and may include, for example, silicone, quartz, glass, light-transmitting ceramics, thermoplastic resin, thermosetting resin. The packaging material may also include fluorescent substances or light scattering particles. But it is not limited to this. The aforementioned packaging material may be replaced with a fluorescent patch, for example, and the present invention is not limited thereto. So far, the fabrication of light-emitting diodes that have not been singulated has been completed.

In short, through the above-mentioned manufacturing method of the light-emitting diode, a light-emitting diode having a protective layer 170t having a height substantially the same as the height of the wafer 130t can be manufactured, thereby improving the brightness (lumens) .

It is worth mentioning that although the above description is based on a substrate that does not need to be removed as an illustrative example, a removable substrate can also be used, that is, an LED chip is arranged on a removable substrate, and an LED chip is arranged. After the removable substrate is placed in a mold, and the protective layer surrounding the wafer is formed by using the above method, the release layer is removed, and subsequent processes or applications are performed. The above-mentioned subsequent process is, for example, after removing the release layer, first forming a packaging material on the wafer or the surface of the wafer and the protective layer away from the removable substrate, and then removing the removable substrate and performing a single Integration process (cutting process). The singulated package wafer can then be used directly as a substrate-less wafer-size package, or it can be placed on the single-layer metal substrate or double-layer metal substrate (for example, the carrier plates 110a, 110b, 110g, 110h, 110j, 110q, 110r, 110s). In other embodiments, the above-mentioned subsequent process is, for example, after the release layer is removed, a singulation process such as cutting is performed, and the singulated structure having a wafer and a protective layer surrounding the wafer is arranged on the single-layer metal The substrate or the double-layer metal substrate (for example, the above-mentioned carrier plates 110a, 110b, 110g, 110h, 110j, 110q, 110r, 110s), and then the packaging material manufacturing process is performed. In another embodiment, for example, the LED chip may be directly disposed on the single-layer metal substrate or the double-layer metal substrate as described above (for example, the above-mentioned carrier plates 110a, 110b, 110g, 110h, 110j, 110q, 110r, 110s), Then, the above process method is used to form a protective layer surrounding the wafer. However, the present invention is not limited to the above examples.

17A is a schematic top view of a light emitting diode according to another embodiment of the present invention. Fig. 17B is a schematic cross-sectional view taken along the line C-C of Fig. 17A. Please refer to FIG. 17A and FIG. 17B at the same time. The light emitting diode 100u of this embodiment further includes at least one electrostatic protection element 180u disposed on the carrier board 110u. The protective layer 170u covers the electrostatic protection element 180u, and the packaging material 140u directly or Indirectly disposed on the protective layer 170u and the wafer 130u. The electrostatic protection element 180u is, for example, a Zener diode or a transient suppression diode (TSV).

In addition, when the electrostatic protection element 180u and the wafer 130u are arranged on the same carrier board 110u, the conventional electrostatic protection element is usually black, so it absorbs light adjacent to the wafer 130u, which causes the luminous efficiency of the wafer 130u to decrease. However, the electrostatic protection element 180u of this embodiment has a protective layer 170u at the periphery, which can reflect the light emitted from the adjacent chip 130u, so that the overall luminous brightness of the light emitting diode 100u can be improved. In addition, the electrostatic protection element 180u can be arranged on the carrier board 110u by using a flux, for example, to avoid short circuit caused by tin overflow.

In summary, in the light-emitting diode of the present invention, the wafer is electrically connected to the carrier board through the conductive region, wherein the first distance between the first contact regions of the carrier board is greater than the second distance between the second contact regions. The distance between the light-emitting diodes and other circuit boards can increase the contact area between the light-emitting diodes and the solder in the first contact area of the carrier board, and avoid short circuit caused by solder overflow. In addition, the above design can also maintain the heat dissipation effect and reliability of the carrier board. Furthermore, an electrostatic protection element may be disposed on the carrier board of the present invention to protect the wafer from electrostatic damage. In addition, a protective layer can also be arranged on the carrier board of the present invention, thereby protecting the light emitting diode and improving the brightness (lumen number) of the light emitting diode. In addition, the light-emitting diode of this embodiment may further have a positive electrode test point and a negative electrode test point on the front surface of the carrier board, so as to facilitate electrical measurement during the manufacturing process.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

10‧‧‧ Release layer

20‧‧‧ Adhesive

30‧‧‧ concave mould

32‧‧‧ bottom

34‧‧‧First surrounding surface

38‧‧‧ second peripheral surface

100a, 100b, 100c, 100d, 100e, 100f, 100g, 100k, 100m, 100n, 100p, 100u‧‧‧ light emitting diode

110a, 110b, 110g, 110h, 110j, 110q, 110r, 110s, 110t, 110u‧‧‧ carrier boards

111a, 111g‧‧‧First surface

112a, 112b, 112g, 112h, 112q, 112s‧‧‧ conductive area

112a1‧‧‧ conductive layer

112b1, 112g1, 112h1‧‧‧ the first conductive layer

112b2‧‧‧ conductive via

112b3, 112g2, 112h2‧‧‧ second conductive layer

113b1‧‧‧First connection layer

113b2‧‧‧Second connection layer

113g‧‧‧Extended pattern

114a, 114b, 114g, 114h, 114j, 114q‧‧‧

114a1, 114b1, 114g1, 114h1, 114j1‧‧‧ First insulation layer

114a2, 114b2, 114g2, 114h2, 114j2‧‧‧Second insulation layer

114a3, 114b3, 114j3‧‧‧ Third insulation layer

115a1‧‧‧First opening

115a2‧‧‧Second opening

115a3‧‧‧ Third opening

120a, 120c, 120d

130a, 130c, 130d, 130t, 130u‧‧‧

132a, 132t‧‧‧ Top

134a, 134t‧‧‧ underside

136a, 136m‧‧‧surrounding surface

140a, 140b, 140g, 140k, 140m, 140t, 140u‧‧‧

150a‧‧‧first surface coating

160a‧‧‧Second surface coating

170a, 170b, 170k, 170m, 170t, 170u‧‧‧

172t‧‧‧ surface

180a, 180u‧‧‧ESD protection element

CP‧‧‧Second Contact Zone

E1, E1 ’‧‧‧ positive test points

E2, E2 ’‧‧‧ negative test points

SP‧‧‧First Contact Zone

P1‧‧‧First pitch

P2‧‧‧Second Pitch

P3‧‧‧ Third pitch

S1‧‧‧ Top surface

S2‧‧‧ lower surface

FIG. 1 is a schematic cross-sectional view of a light emitting diode according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of a light emitting diode according to another embodiment of the present invention. FIG. 3 is a schematic cross-sectional view of a light emitting diode according to another embodiment of the present invention. FIG. 4 is a schematic cross-sectional view of a light emitting diode according to another embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of a light emitting diode according to another embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a light emitting diode according to another embodiment of the present invention. FIG. 7A is a schematic cross-sectional view of a light emitting diode according to another embodiment of the present invention. FIG. 7B is a schematic top view of a carrier plate of the light-emitting diode of FIG. 7A. FIG. 7C is a schematic cross-sectional view taken along the line I-I of FIG. 7B. FIG. 8 is a schematic cross-sectional view of a carrier board according to another embodiment of the present invention. 9A is a schematic top view of a carrier board according to an embodiment of the present invention. FIG. 9B is a schematic cross-sectional view taken along line A-A of FIG. 9B. FIG. 9C is a schematic cross-sectional view taken along line B-B of FIG. 9B. FIG. 10 is a schematic cross-sectional view of a light emitting diode according to another embodiment of the present invention. FIG. 11 is a schematic cross-sectional view of a light emitting diode according to another embodiment of the present invention. FIG. 12A is a schematic top view of a light emitting diode according to another embodiment of the present invention. FIG. 12B is a schematic partial perspective view of the light-emitting diode of FIG. 12A. FIG. 13 is a schematic top view of a light emitting diode according to another embodiment of the present invention. 14A is a schematic top view of a carrier board according to another embodiment of the present invention. FIG. 14B is a schematic bottom view of the carrier board of FIG. 14A. 15A is a schematic top view of a carrier board according to another embodiment of the present invention. 15B is a schematic top view of a carrier board according to another embodiment of the present invention. 16A to 16F are schematic cross-sectional views illustrating a method for manufacturing a light emitting diode according to an embodiment of the present invention. 17A is a schematic top view of a light emitting diode according to another embodiment of the present invention. Fig. 17B is a schematic cross-sectional view taken along the line C-C of Fig. 17A.

Claims (17)

A light emitting diode includes: a wafer; a carrier board including: a conductive region having an upper surface and a lower surface; an insulating region covering at least a portion of the conductive region; wherein the conductive region includes at least a first contact Area and at least one second contact area, the first contact area is located in an area of the lower surface of the conductive area that is not covered by the insulation area, and adjacent first contact areas have a first distance therebetween, and the second The contact area is located in an area where the upper surface of the conductive area is not covered by the insulation area, and a second distance between the adjacent second contact areas is greater than the second distance; a packaging material, Directly or indirectly covering a part of the surface of the wafer; and a protective layer disposed on the carrier board and directly or indirectly surrounding the wafer, at least one side of the protective layer is substantially coplanar with at least one side of the carrier board. According to the light emitting diode described in item 1 of the patent application scope, there is still a third gap between the two adjacent second contact regions, and the first gap is larger than the third gap, and the third gap is smaller than Or equal to the second pitch. The light-emitting diode according to item 1 of the scope of patent application, wherein the insulating region of the carrier board includes a first insulating layer, a second insulating layer, and a third insulating layer, and the second insulating layer is located in the first insulating layer. Between an insulating layer and the third insulating layer, the first insulating layer has at least one first opening, the second insulating layer has at least one second opening, the third insulating layer has at least one third opening, and the carrier Part of the lower surface and part of the upper surface of the conductive region of the board are exposed to the first opening and the third opening, respectively. The light-emitting diode according to item 1 of the scope of patent application, wherein the conductive region includes a plurality of conductive layer structures, and adjacent two conductive layers are connected by at least one conductive via. The light-emitting diode according to item 1 of the scope of patent application, wherein the packaging material directly or indirectly covers at least part of the surface of the wafer that is relatively far from the carrier board and at least part of the surface of the protective layer, and at least one side of the packaging material It is substantially coplanar with at least one side of the protective layer. The light-emitting diode according to item 1 of the scope of patent application, wherein a part of the packaging material is located between the wafer and the protective layer. The light-emitting diode according to item 1 of the patent application range, wherein a distance between a surface of the wafer having an electrode and the upper surface of the conductive region of the carrier board is smaller than a surface of the wafer not having the electrode Distance from the upper surface of the conductive region of the carrier board. The light-emitting diode according to item 1 of the scope of patent application, wherein the wafer is disposed on the second contact region of the carrier board in a flip-chip bonding manner. The light-emitting diode according to item 1 of the patent application scope further includes: an electrostatic protection element disposed on the carrier board. The light-emitting diode according to item 1 of the patent application scope, wherein the packaging material is a light-transmitting material. The light-emitting diode according to item 10 of the scope of patent application, wherein the packaging material includes silicon, quartz, glass, transparent ceramics, thermoplastic resin, and thermosetting resin. The light-emitting diode according to item 10 of the patent application scope, wherein the packaging material includes a fluorescent substance or light scattering particles. The light-emitting diode according to item 1 of the patent application scope further includes: at least one surface coating layer disposed on at least one of the upper surface and the lower surface of the conductive region of the carrier board. The light-emitting diode according to item 1 of the scope of patent application, wherein the second contact region and the first contact region are recessed in the insulation region, respectively. A method for manufacturing a light emitting diode includes: providing a carrier board; arranging at least one wafer on the carrier board, the wafer having a top surface and a bottom surface opposite to each other, wherein the top surface is far from the carrier plate; A release layer is on the top surface of the wafer, wherein the orthographic projection area of the release layer on the carrier plate is greater than or equal to the orthographic projection area of the wafer on the carrier plate; the wafer and the release layer will be carried. The carrier plate of the layer is inverted in a concave mold, so that the release layer is located at a bottom of the concave mold, and a gap is formed between a side surface of the wafer and an inner surface of the concave mold; A protective layer is on the side of the wafer; the concave mold and the release layer are removed to expose the top surface of the wafer and a surface of the protective layer, wherein the top surface of the wafer and the protective layer The surface is substantially coplanar; and a packaging material is directly or indirectly formed on the top surface of the wafer and the surface of the protective layer. The method for manufacturing a light-emitting diode according to item 15 of the scope of patent application, wherein the release layer is a thermal release adhesive layer. The method for manufacturing a light-emitting diode according to item 15 of the patent application scope, wherein the carrier board includes: a conductive region having an upper surface and a lower surface; and an insulating region covering at least a part of the conductive region; at least A first contact area, which is located in an area of the conductive surface where the lower surface is not covered by the insulation area, at least a second contact area, which is located in an area where the upper surface of the conductive area is not covered by the insulation area, the second The contact area is used for electrically connecting the chip; wherein two adjacent first contact areas have a first distance, and two adjacent second contact areas have a second distance, and the first distance is greater than The second pitch.