TWI626535B - Power management system and controller - Google Patents

Abstract

The invention provides a power management system. The power management system includes a processor, a chipset, a controller, and a power regulation circuit. The chipset is electrically connected to the processor, and transmits a power source information to the controller through an enhanced serial peripheral interface. The controller is electrically connected to the chipset through the enhanced serial peripheral interface, receives power information through the enhanced serial peripheral interface, and decodes the power information to obtain a status information. The power adjustment circuit receives a control signal from one of the controllers, and according to the control signal, turns off, turns on, or adjusts the power of the processor.

Description

Power management systems and controllers

The description of the present invention mainly relates to a processor power management technology, and particularly relates to connecting a chipset and a controller through an Enhanced Serial Peripheral Interface (eSPI) to directly manage the processor through the controller. Processor power management technology for power supply.

In order to extend the battery life of the computer device, a power logic circuit will be configured in the traditional computer device to monitor the SLP_S0 # pin of the chipset to determine whether the computer device enters or leaves the low power consumption mode. The power logic circuit instructs the Voltage Regulator Module (VRM) to turn off or turn on the power of the computer's Central Processing Unit (CPU) according to the judgment result.

In other words, in traditional computer devices, embedded controller (EC) or super input output (SIO) chips do not participate in the management of processor power. Furthermore, when the SLP_S0 # pin is at a low level, the power state of the processor is usually in the C10 state. In addition, compared to the traditional Low Pin Count Bus (LPC Bus), which is used to connect the chipset and embedded controller (or Super I / O), the Enhanced Serial Peripheral Interface (eSPI) can be used to provide processing C10 status information.

Therefore, how to manage the power of the processor by using the embedded controller or super I / O chip originally configured in the computer device will be a topic worthy of discussion.

In view of the foregoing problems of the prior art, the present invention provides a power management system for connecting a chipset and a controller through an enhanced serial peripheral interface to directly manage the power of a processor through the controller.

According to an embodiment of the present invention, a power management system is provided. The power management system includes a processor, a chipset, a controller, and a power adjustment circuit. The chipset is electrically connected to the processor, and transmits a power source information to the controller through an enhanced serial peripheral interface. The controller is electrically connected to the enhanced serial peripheral interface, receives the power source information through the enhanced serial peripheral interface, and decodes the power source information to obtain a status information. The power adjustment circuit receives a control signal from one of the controllers, and turns off, turns on, or adjusts the power of the processor according to the control signal.

According to some embodiments of the present invention, the controller includes a decoding circuit for decoding the power information. According to some embodiments of the present invention, the controller generates a control signal according to the status information, and transmits the control signal to the power adjustment circuit.

According to some embodiments of the present invention, the above-mentioned state information includes SLP_S0 # pin information of a chipset, and a processor power state information. According to some embodiments of the present invention, the processor power state information includes a C10 state information.

According to an embodiment of the present invention, a controller is provided. Above The controller includes a decoding circuit. The controller is connected to a chipset via an enhanced serial peripheral interface, and receives the power supply information transmitted from the chipset via the enhanced serial peripheral interface.

According to some embodiments of the present invention, the controller further includes a control circuit. The control circuit generates a control signal according to the state information, and transmits the control signal to a power regulating circuit.

Regarding other additional features and advantages of the present invention, those skilled in the art can make some modifications based on the user device and system for performing the contact procedure disclosed in the implementation method of the present invention without departing from the spirit and scope of the present invention. Changes and retouching.

100‧‧‧Power Management System

110‧‧‧ processor

120‧‧‧chipset

130‧‧‧controller

131‧‧‧ decoding circuit

132‧‧‧Control circuit

140‧‧‧Power Regulation Circuit

150‧‧‧Enhanced serial peripheral interface

S1‧‧‧Control signal

FIG. 1 is a block diagram showing a power management system according to an embodiment of the present invention.

FIG. 2 is a block diagram of a controller according to an embodiment of the present invention.

This section describes the best way to implement the present invention. The purpose is to explain the spirit of the present invention and not to limit the scope of protection of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application. .

FIG. 1 is a block diagram of a power management system 100 according to an embodiment of the present invention. The power management system 100 can be a computer host, a notebook computer, a tablet computer, or a mobile device, but the invention is not limited thereto. As shown in FIG. 1, the power management system 100 may include a processor. 110. A chipset 120, a controller 130, a power adjustment circuit 140, and an enhanced serial peripheral interface (eSPI) 150. It should be noted that the block diagram in FIG. 1 is only for the convenience of describing the embodiments of the present invention, but the present invention is not limited thereto. The power management system 100 may also include other components.

According to an embodiment of the present invention, the processor 110 is electrically connected to the chipset 120 and the power adjustment circuit 140 respectively. In the embodiment of the present invention, the controller 130 is electrically connected to the chipset 120 through the enhanced serial peripheral interface 150.

According to an embodiment of the present invention, the chip set 120 may include a north bridge wafer and a south bridge wafer. The processor 110 may be electrically connected to the northbridge chip of the chipset 120 through a front-end bus, and the controller 130 may be electrically connected to the southbridge chip of the chipset 120 through an enhanced serial peripheral interface 150. In some embodiments of the present invention, the chipset 120 may be a Platform Controller Hub (PCH).

According to an embodiment of the present invention, the controller 130 may be an embedded controller (EC) or a super input output (SIO) chip, but the present invention is not limited thereto. According to an embodiment of the present invention, the controller 130 configures a control or judgment circuit related to the power state of the processor 110 (for example, the control circuit 132), so that the controller 130 can decode the chipset 120 by enhancing the serial peripheral Information about the power state of the processor 110 in the power information provided by the interface 150.

According to an embodiment of the present invention, the power regulation circuit 140 may be a voltage regulator module (VRM). In the present invention In an embodiment, the power regulating circuit 140 may be used to provide the power required by the processor 110 and appropriately adjust the power provided to the processor 110 according to an instruction of the controller 130, such as: turning off, turning on, or adjusting the power of the processor 110 .

FIG. 2 is a block diagram of the controller 130 according to an embodiment of the present invention. As shown in FIG. 2, according to an embodiment of the present invention, the controller 130 may include a decoding circuit 131 and a control circuit 132. It is noted that the block diagram in FIG. 2 is only for the convenience of describing the embodiment of the present invention, but the present invention is not limited thereto.

According to an embodiment of the present invention, the controller 130 obtains the power information provided by the chipset 120 through the enhanced serial peripheral interface 150. After the controller 130 obtains the power supply information provided by the chipset 120, the decoding circuit 131 of the controller 130 decodes the power supply information received from the enhanced serial peripheral interface 150 to obtain a status information and transmits the status information to The control circuit 132 of the controller 130. The control circuit 132 can obtain the current power status (or operation status) of the processor 110 and the chipset 120 according to the status information. For example, the control circuit 132 can know whether the current processor 110 and the chipset 120 enter a low power consumption state or a hibernation state according to the status information.

According to some embodiments of the present invention, the state information generated by the decoding circuit 131 after decoding may include SLP_S0 # pin information of the chipset 120 and a processor power state information, but the present invention is not limited thereto.

The SLP_S0 # pin information indicates the potential value of the SLP_S0 # pin of the south bridge chip (group) of the chipset 120. The potential value of the SLP_S0 # pin can be used to indicate whether the power management system 100 enters or leaves a power consumption mode. According to an embodiment of the present invention, when the control circuit 132 obtains SLP_S0 # pin information After the communication, the control circuit 132 can obtain the current potential value of the SLP_S0 # pin according to the extracted SLP_S0 # pin information, and determine whether the current power management system 100 enters or leaves a power consumption mode according to the potential value. For example, when the current potential of the SLP_S0 # pin is low, the control circuit 132 determines that the power management system 100 enters a power consumption mode, and when the current value of the SLP_S0 # pin is high The control circuit 132 determines that the power management system 100 leaves a power consumption mode.

According to an embodiment of the present invention, the processor power state information indicates a C10 state information. C-state is a standard used in the Advanced Configuration and Power Interface (ACPI) to formulate the power state of the processor (CPU). In the C-state specification, the power state of the processor (CPU) includes C1 ~ C10 states, where C10 indicates that the external voltage adjustment of the processor can be reduced to 0V or turned off completely.

According to an embodiment of the present invention, when the control circuit 132 of the controller 130 obtains the C10 state information, the control circuit 132 can know whether the processor 110 is currently in the C10 state according to the C10 state information. Therefore, according to the C10 status information, the control circuit 132 generates a control signal S1 and transmits the control signal S1 to the power adjustment circuit 140. When the adjustment circuit 140 receives the control signal S1, the power adjustment circuit 140 turns off, turns on, or adjusts the power supplied to the processor 110 according to the instruction of the control signal S1.

According to an embodiment of the present invention, the power management system 100 can control the power of the fan and the status light according to the status information generated by the decoding circuit 131 through the control circuit 132 of the controller 130.

According to the power management system 100 proposed in the embodiment of this case, The computer device can directly use its own controller (such as EC or SIO) to decode the power information received from the enhanced serial peripheral interface, and manage the power of the processor based on the decoded state information. Therefore, there is no need to monitor the SLP_S0 # pin of the chipset by configuring additional power logic circuits in the computer device to manage the power of the processor.

"One embodiment" or "an embodiment" mentioned in this specification indicates that the specific feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment according to the present invention, but does not mean that They exist in every embodiment. Thus, the appearances of the phrase "in one embodiment" or "in an embodiment" in various places in this specification do not necessarily denote the same embodiment of the invention.

The above paragraphs are described at multiple levels. Obviously, the teachings of this article can be implemented in many ways, and any particular architecture or function disclosed in the examples is only a representative situation. According to the teachings of this article, anyone familiar with the art should understand that the aspects disclosed in this article can be implemented independently or that more than two levels can be combined and implemented.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.

Claims (10)

A power management system includes: a processor; a chipset electrically connected to the processor, and transmitting power information through an enhanced serial peripheral interface (eSPI); and a controller, electrically connected to the enhanced serial peripheral Interface (eSPI), receives the power information through the enhanced serial peripheral interface (eSPI), and decodes the power information to obtain a status information; and a power adjustment circuit receives a control signal from the controller, and according to the above The control signal regulates the power supplied to the processor. The power management system according to item 1 of the patent application scope, wherein the controller includes a decoding circuit for decoding the power information. The power management system according to item 1 of the scope of patent application, wherein the controller generates the control signal according to the status information, and transmits the control signal to the power adjustment circuit. The power management system according to item 3 of the scope of patent application, wherein the power adjustment circuit turns off, turns on, or adjusts the power of the processor according to the control signal. The power management system according to item 1 of the scope of patent application, wherein the above-mentioned state information includes one of the chipset SLP_S0 # pin information and a processor power state information. The power management system according to item 5 of the scope of patent application, wherein the processor power state information includes a C10 state information. A controller includes: a decoding circuit that decodes a power source information to obtain a status information, wherein the controller is connected to a chipset via an enhanced serial peripheral interface (eSPI), and via the enhanced serial peripheral interface (eSPI) ) Receive the power information transmitted from the chipset. The controller according to item 7 of the scope of patent application, further comprising: a control circuit, which generates a control signal according to the above-mentioned state information, and transmits the above-mentioned control signal to a power regulating circuit. The controller according to item 7 of the scope of patent application, wherein the above-mentioned status information includes one of the chipset SLP_S0 # pin information and a processor power status information. The controller according to item 9 of the scope of patent application, wherein the processor power state information is a C10 state information.