TWI623200B - Decoding device and decoding method for absolute positioning code - Google Patents

Abstract

A decoding device for locating an absolute code, comprising a linear feedback shift register, a look-up table circuit, a counter, and a calculation circuit. The linear feedback shift register includes n registers, loads the positioning absolute code at the first frequency, and performs a shift operation according to the clock signal, the clock signal having a second frequency not less than the first frequency. The look-up table circuit outputs the look-up result value and the check-table effective flag according to the values stored by the n registers, and the result of the look-up table has k different kinds of data, k≦(2 ⁿ -1). The counter is reset according to the lookup table valid flag, and the counting operation is performed according to the clock signal to generate a count result value. When the lookup table valid flag indication is valid, the calculation circuit calculates a decoding result according to the lookup table result value and the count result value.

Description

Decoding device and decoding method for locating absolute code

The present invention relates to a decoding apparatus for locating an absolute code and a decoding method applied thereto.

Optical encoders (for example, rotary encoders, optical scales, and optical encoders in the present specification will be referred to as optical encoders in the following description) can be classified into an incremental output and an absolute output depending on the output type. The absolute output type optical scale has the advantages of directly reading the absolute value of the displacement coordinate, no cumulative error, and the position information is not lost after the power is cut off, and is widely used in equipments such as numerical control machine tools, servo drives, and robots that need to detect displacement. The signal read by the optical scale needs to obtain the position information of the object to be tested through the corresponding decoder. Therefore, how to design a decoding device and a decoding method suitable for the absolute output optical scale is a current problem in the industry. one.

The present invention relates to a decoding apparatus for positioning an absolute code and a decoding method applied thereto.

According to an embodiment of the present invention, a decoding apparatus for positioning an absolute code is provided, including a linear feedback shift register, a look-up table circuit, a counter, and a calculation circuit. The linear feedback shift register includes n registers, n registers load the positioning absolute code at the first frequency, and perform a shift operation according to the clock signal, the clock signal has a second frequency, and the second The frequency is not less than the first frequency. The table lookup circuit is based on the values stored in the n registers, corresponding to the output checklist result value and the check table valid flag, wherein the check result value has k different data, k≦(2 ⁿ -1), check table effective flag Indicates whether the result of the table check is valid. The counter is reset according to the lookup table valid flag, and the counting operation is performed according to the clock signal to generate a count result value. When the lookup table valid flag indication is valid, the calculation circuit calculates a decoding result according to the lookup table result value and the count result value.

In addition, according to an embodiment of the present invention, a decoding method for locating an absolute code is provided, including the following steps. A linear feedback shift register is provided, including n registers, and n registers load the positioning absolute code at a first frequency. The shift operation is performed by linearly returning the shift register according to the clock signal, and the clock signal has a second frequency, and the second frequency is not less than the first frequency. Using the look-up table, according to the values stored in the n registers, the output check result value and the check table valid flag, wherein the check result value has k different materials, k≦(2 ⁿ -1), the check table is valid. The flag indicates whether the result of the lookup table is valid. The counting operation is performed according to the clock signal to generate a counting result value, wherein the counting result value is reset according to the look-up table valid flag. When the lookup table valid flag indication is valid, a decoding result is generated according to the lookup table result value and the count result value calculation.

In order to better understand the above and other aspects of the present invention, The preferred embodiment is described in detail with reference to the accompanying drawings.

1‧‧‧Decoding device

100, 100_F, 100_G‧‧‧ linear feedback shift register

102‧‧‧Table lookup circuit

104‧‧‧ counter

106‧‧‧Computation circuit

108‧‧‧clock switch circuit

200‧‧‧Responsible multiplexer

210, 310‧‧‧Multiplexer

212, 312‧‧‧ logical mutual exclusion or gate

A‧‧‧First control data

B‧‧‧Second control data

C‧‧‧ count result value

CLK‧‧‧ clock signal

Cal _F (1)~Cal _F (3), Cal _G (1)~Cal _G (3)‧‧‧Operational logic circuit

R(1)~R(4)‧‧‧ register

S(1)~S(2)‧‧‧Switch

S400, S402, S404, S406, S408‧‧‧ steps

VF‧‧‧Table effective flag

X‧‧‧ Positioning absolute code

Y‧‧‧Check results

Z‧‧‧ decoding results

FIG. 1A is a schematic diagram showing a monorail absolute value output type optical linear scale.

FIG. 1B is a schematic view showing a monorail absolute value output type optical circular scale.

FIG. 2A is a schematic diagram showing a linear feedback shift register.

FIG. 2B is a schematic diagram showing a sequence of data generated by the linear feedback shift register of FIG. 2A.

FIG. 3 is a schematic diagram of a decoding apparatus according to an embodiment of the invention.

FIG. 4 is a schematic diagram of a decoding apparatus according to another embodiment of the present invention.

FIG. 5A is a schematic diagram of an elastic linear feedback shift register according to an embodiment of the invention.

FIG. 5B is a schematic diagram of the arithmetic logic circuit as shown in FIG. 5A.

FIG. 6A is a schematic diagram of an elastic linear feedback shift register according to another embodiment of the present invention.

FIG. 6B is a schematic diagram of the arithmetic logic circuit as shown in FIG. 6A.

FIG. 7 is a schematic diagram of sampling a data sequence generated by an LFSR at regular intervals according to an embodiment of the invention.

FIG. 8 is a schematic diagram showing the correspondence relationship of data of the look-up table circuit according to an embodiment of the invention.

FIG. 9 is a schematic diagram of a truth table of a table lookup circuit according to an embodiment of the invention.

FIG. 10 is a schematic diagram showing the circuit implementation of the look-up table circuit according to an embodiment of the invention.

FIG. 11 is a schematic diagram of a decoding process according to an embodiment of the invention.

FIG. 12 is a flow chart of a decoding method according to an embodiment of the invention.

In order to obtain a position information, the absolute output type optical scale reads a set of position information by using a plurality of sets of photo-electrical sensors. Since the noise suppression, discriminating the positive and negative, and preventing misreading must be considered to improve the reliability, the absolute output optical scale uses the multi-track Gray code in the encoding method. The biggest difference between the Gray code and the general binary code is that the Gray code only changes one bit at a time, so it is not easy to cause misreading.

However, the practice of generating a Gray code in a multi-track arrangement, even if a very small amount of declination is introduced, it may cause a phase difference of the read head signal, causing a positional misjudgment, and thus gradually develops into a monorail absolute value output type optical scale. The scale of the monorail absolute output optical scale can be encoded using a maximum length sequence (MLS), which is a pseudorandom binary sequence that can be used with a linear feedback shift register (linear feedback) Shift registers, LFSR) are generated. For an optical scale encoded with LFSR, a linear feedback shift register can also be used at the decoding end to restore the order of encoding to obtain position information.

In practice, the monorail absolute value output type optical scale includes a direct scale and a circular scale, FIG. 1A shows a schematic diagram of a monorail absolute value output type optical linear scale, and FIG. 1B shows a monorail absolute value output type optical circle. The schematic diagram of the scale, the pseudo-random binary sequence generated by the LFSR is sequentially depicted on the optical scale, and can be distinguished by 0 and 1 by different degrees of light transmission, for example, the permeable area is 1 and the light-shielding area is 0. In the optical ruler The light source and the photo sensor array can be respectively disposed on both sides of the optical sensor array, and the absolute position of the optical scale represented by the subsequent decoding process can be obtained by the data read by the photo sensor array. As shown in FIGS. 1A and 1B, the photosensor array can read a plurality of adjacent codes on the scale by the received light, and can obtain an absolute position based on the information. A linear scale can be used to measure the amount of displacement, and a circular scale can be placed on a disk that rotates about a rotation axis to measure the amount of rotation of the object.

However, as the requirements for position resolution increase, the optical scale needs to increase the detection length, that is, an M-sequence pseudo-random code requiring a larger number of bits. For MLS with a large number of bits, if you simply use the shift register to restore the encoding order, the location information will be very slow. What is more, the algorithm for shifting the encoding order of the shift register needs to be matched with the MLS random code depicted on the optical scale body. If you can develop a read head architecture that can read multiple versions of the ruler sequence, you can save on the development cost of the read head.

For the decoding method of the absolute position of the position, another way is to use a lookup table (LUT) method to generate a unique corresponding sequence signal for each MLS random code depicted on the optical ruler, so that the decoding end obtains the order. When the signal is received, the corresponding position of the optical ruler and the ruler is immediately known. The method is to input the signal to the LUT by using a plurality of sets of photo-inductors mounted on the optical scale read head, and input the signal to the LUT via the signal of the MLS random code of the optical scale; when the LUT obtains a valid bit At the address, a corresponding data is immediately output to the data bus. This method also faces the same problem. As the length of the optical scale detection increases, the M-series pseudo-random code of more bits makes the LUT capacity expand rapidly, occupying too large memory space and hardware area, and the capacity is too large. The LUT will cause problems with the size and manufacturing cost of the optical scale.

The following is a description of the operation of the LFSR related operation. The LFSR includes a plurality of registers, characterized in that the input of the register is a linear function of the previous state of the register, which is common in the LFSR. Implemented using a mutex or gate (XOR). The initial value of the scratchpad in the LFSR is called "seed". Because the operation of the LFSR is deterministic, the data stream generated by the LFSR can be completely determined by the current or previous state of the LFSR. Moreover, since the possible state of the LFSR is limited, it will be a repeating loop. Thus with proper pre-selection polynomial processing, the LFSR can generate sequences that appear to be random and have very long cycle times.

Specifically, the LFSR can change the corresponding polynomial according to the position of the XOR feedback point, or the tap position. For the LFSR including n registers, when the tap position of the LFSR corresponds to a primitive polynomial, as long as the initial state of the register is not all 0, the length (2 ⁿ -1) can be generated. MLS. Similarly, when a set of "seeds" is obtained, the shift operation and counting of the LFSR can be utilized to find out where the "seed" is located in the data stream generated by the LFSR.

FIG. 2A is a schematic diagram of a linear feedback shift register. The figure is illustrated by an LFSR including four registers. As shown in the figure, the next state of the register R3 is the current register R3. The state and the XOR operation result of the current state of the register R0, the primitive polynomial corresponding to this figure is ( x ⁴ + x ³ +1). FIG. 2B is a schematic diagram showing a data sequence generated by the linear feedback shift register of FIG. 2A. Such an LFSR having a bit length of 4 can sequentially generate an MLS having a length of (2 ⁴ -1)=15. FIG. 2A illustrates only one implementation of the LFSR. In this example, the architecture is shifted to the right. In other embodiments, the LFSR may also use a left-shifting architecture, and the operation principle is similar. This is not repeated here.

As described above, for an optical scale with a long detection length, if LFSR decoding is used, the speed may be too slow, and if the LUT is used, the hardware space may be too large to reduce the cost, so the present invention proposes a hybrid decoding architecture. In order to achieve the advantages of both calculation time and hardware area.

FIG. 3 is a schematic diagram of a decoding apparatus according to an embodiment of the invention. The decoding device 1 for locating the absolute code includes a linear feedback shift register 100, a look-up table circuit 102, a counter 104, and a calculation circuit 106. The linear feedback shift register 100 includes n registers, and the n registers load the positioning absolute code X at the first frequency f ₁ and perform a shift operation according to the clock signal CLK, and the clock signal CLK has The second frequency f ₂ , the second frequency f _{2 is} not less than the first frequency f ₁ . The lookup table circuit 102 correspondingly outputs the lookup result value Y and the table check valid flag VF according to the values stored by the n registers, wherein the table lookup result value Y has k different materials, k≦(2 ⁿ -1), The table check valid flag VF indicates whether the check result value Y is valid. The counter 104 performs a reset according to the look-up table valid flag VF, and performs a counting operation based on the clock signal CLK to generate a count result value C. When the look-up table valid flag VF indicates that it is valid, the calculation circuit 106 calculates the generated decoding result Z based on the look-up table result value Y and the count result value C. The components and related operating conditions are described in detail below.

The linear feedback shift register 100 includes n registers, and the register can be implemented, for example, by a D-type flip flop having a preset function, and the linear feedback shift register 100 can be By presetting the D-type flip-flop, the positioning absolute code X read by the optical sensor is loaded into n registers as the initial value of n registers, and the absolute code X is, for example, n. One bit signal. This action of loading the absolute code X can be operated at a first frequency f ₁ , for example in relation to the required optical measurement frequency. For example, for a motion speed of 20 m/s, which is calculated by a 10 μm period conversion, the first frequency f ₁ can be set to 2 MHz, that is, for the decoding apparatus 1, the decoded operation bandwidth needs to be greater than 2 MHz.

The look-up table circuit 102 performs a lookup table based on the values stored in the n registers, and the look-up table circuit 102 can store the data generated by the "partial" linear feedback shift register 100. For example, the linear feedback shift register 100 can generate an MLS of length (2 ⁿ -1), and the lookup circuit 102 can store the complete (2 ⁿ -1) pen data, or this (2 ⁿ -1) The position information corresponding to the k-pen data in the pen data, k≦(2 ⁿ -1). That is, after the linear feedback shift register 100 is loaded with the positioning absolute code X, the use of the positioning absolute code X may not be able to find the corresponding look-up result from the look-up table circuit 102, so the look-up table circuit 102 further includes an output. The pin check table valid flag VF is used to indicate whether the currently output check result value Y is valid.

Since the look-up table circuit 102 can only store the location information corresponding to the partial MLS, the hardware area required for the look-up table circuit 102 can be effectively reduced. If the positioning absolute code X can find the corresponding position information from the look-up table circuit 102, the decoding operation is completed, and the position information can be output according to the table look-up result value Y. On the other hand, if the positioning absolute code X cannot find the corresponding position information from the look-up table circuit 102, and the output table check valid flag VF indicates invalid, the calculation circuit 106 may not output the result first, and the decoding action is not completed yet. The linear feedback shift register 100 and the counter 104 continue the subsequent decoding operation operations.

In the case that the table look-up valid flag VF indication is invalid, the linear feedback shift register 100 can perform a displacement operation according to the clock signal CLK, and change n register registers to the next state, according to the displacement operation. The result is again checked, and such a displacement operation can be repeated until it is successfully found in the lookup circuit 102. Data, the output checklist valid flag VF indication is valid. At the same time, the counter 104 can count to obtain the count result value C to calculate that the linear feedback shift register 100 performs several shift operations in the above process. The result value C of the count is equivalent to representing the absolute code X from the initial position. After several times of displacement operation, the corresponding data can be successfully found from the look-up table circuit 102, and a valid look-up result value Y is found.

That is, the positional data corresponding to the absolute code X and the lookup result value Y have a difference of C. Therefore, when the look-up table valid flag VF indication is valid, the calculation circuit 106 can check the result value Y according to the look-up result value Y and the count result value C, for example, by addition (or subtraction). It is the result of the look-up table Y after the shift, or a multiple of the result Y of the look-up table.) The calculation result value C is added to generate the decoding result Z. Meanwhile, when the look-up table valid flag VF indication is valid, it indicates that the decoding operation has ended, so the counter 104 can be reset, for example, the calculation result value C is zeroed to facilitate the next decoding operation.

As described above, each decoding operation may require linearly shifting the shift register of the shift register 100 multiple times and accumulating the counter 104 multiple times. Therefore, the linear feedback shift register 100 shift operation and the counter 104 accumulate The second frequency f _{2 of the} clock signal CLK according to it should be greater than or equal to the first frequency f _{1 of the} linear feedback shift register 100 loaded with the positioning absolute code X. The relationship between the first frequency f ₁ and the second frequency f ₂ is related to the data interval stored in the look-up table circuit 102. If the data stored in the look-up table circuit 102 is far apart in the pseudo-random sequence code, the representative may need to go through More than one linear feedback shift register 100 shift operation and counter 104 accumulate to successfully find the data, so the difference between the first frequency f ₁ and the second frequency f ₂ should be given; otherwise, if the table is checked The circuit 102 stores more data, and is closer to each other in the pseudo random sequence code, so that the difference between the first frequency f ₁ and the second frequency f ₂ can be given. Similarly, the data interval to be stored by the look-up table circuit 102 can also be determined according to the operating speed of the look-up table circuit 102.

For example, if the first frequency f ₁ is 2 MHz, the speed at which the look-up circuit 102 finds data can be operated at 400 MHz. Considering the actual hardware factor and the safety factor range, the data interval stored by the look-up table circuit 102 can be set to 50. ~100, that is, the linear feedback shift register 100 can successfully find the corresponding position data in the look-up table circuit 102 after up to 50-100 displacement operations.

For the decoding method used by the decoding device 1 shown in FIG. 3, reference may be made to FIG. 12 for a flowchart of a decoding method according to an embodiment of the present invention. The decoding method includes the following steps. Step S400: providing a linear feedback shift register, the linear feedback shift register comprising n registers, loading the positioning absolute code X at the first frequency f ₁ . Step S402: Perform a shift operation according to the clock signal CLK in a linear feedback shift register. The clock signal CLK has a second frequency f ₂ , and the second frequency f _{2 is} not less than the first frequency f ₁ . Step S404: using the lookup table, according to the values stored by the n registers, correspondingly outputting the lookup result value Y and the table check effective flag VF, wherein the table lookup result value Y has k different materials, k≦(2n-1) ), the table check valid flag VF indicates whether the check result value Y is valid. Step S406: Perform a counting operation according to the clock signal CLK to generate a count result value C, wherein the count result value C is reset according to the look-up table valid flag VF. Step S408: When the table lookup valid flag VF indication is valid, the decoding result Z is generated according to the lookup table result value Y and the count result value C.

Using the decoding device shown in FIG. 3 and the decoding method shown in FIG. 12, it is possible to combine the advantages of a small LFSR hardware circuit and a fast LUT speed. Since only some of the data can be stored in the look-up table, the circuit area can be effectively saved. For the part that is not stored in the table, you can use the LFSR to shift until you find the data. Since the lookup speed of the LUT is usually much higher than the decoding speed required by the optical scale, using a LUT with a smaller capacity and a LFSR that takes more time to operate can still not affect the required decoding speed, and can Reduce hardware costs. In addition, this architecture also makes the circuit design more flexible. When the circuit can give a larger space, the LUT can be given a larger capacity to speed up. When the decoding speed is looser, the LFSR can be given a larger length. To reduce the circuit area required for the LUT. Therefore, the decoding device and method of the present disclosure are flexible in design and can be applied to optical scales for various applications.

FIG. 4 is a schematic diagram of a decoding apparatus according to an embodiment of the invention. The decoding device 2 in this example further includes a clock switch circuit 108 as compared with the embodiment shown in FIG. The clock switch circuit 108 can generate a gated clock signal according to the original clock signal O_CLK and the table look-up valid flag VF, and transmit the gated clock signal as a gate feedback shift register 100 and The clock signal CLK of the counter 104. At this time, the pulse switch circuit 108 can stop the clock output when the table look-up valid flag VF indication is valid (corresponding to the representative decoding has been completed), so that the clock signal CLK stops oscillating, and thus linearly returns the shift register 100. The displacement is no longer performed, and the counter 104 also stops counting. This ensures that the operation of the decoding device 2 is correct, and since the decoding is completed, the linear feedback shift register 100 and the counter 104 are equivalent to the rest state, and can be achieved. The advantage of reducing circuit power consumption.

In an embodiment, the linear feedback shift register 100 can flexibly control the tap position and the number of encoded bits. For example, the linear feedback shift register 100 can change the bit length according to the first control data A, and The position of the feedback point can be changed according to the second control data B, that is, the polynomial used is changed. Use such a linear feedback transfer The bit register 100 can be designed with a read head hardware, and meets the requirements of multiple versions of the figure pattern decoding, that is, the application requirements of different lengths and different resolutions are simultaneously supported by a single hardware. The LFSR circuit implementation can choose to use the Galois architecture or the Fibonacci architecture. The following describes the implementation of the control circuit related to the elastic control of the tap position and the number of coded bits under the two architectures.

FIG. 5A is a schematic diagram of an elastic linear feedback shift register according to an embodiment of the present invention. In this example, a right-shifting Galois architecture is used, and n=4 is taken as an example. The linear feedback shift register 100_G includes n register R(1)~R(n), feedback multiplexer 200, and (n-1) arithmetic logic circuits Cal _G (1)~Cal _G ( N-1). The feedback multiplexer 200 has a plurality of input terminals, a selection control terminal, and an output terminal, wherein the selection control terminal of the feedback multiplexer 200 is coupled to the first control data A, and the plurality of feedback multiplexers 200 are The input ends are respectively coupled to the output ends of the n register R(1)~R(n) (for example, the Q pin of the D-type flip-flop). The i-th (1≦i≦n-1) arithmetic logic circuit Cal _G (i) inputs the i-th register R(i) according to the i-th sector B(i) of the second control data B The terminal (for example, the D pin of the D-type flip-flop) is selectively coupled to one of the following pins: the output of the feedback multiplexer 200, the (i+1)th register R ( The output of i+1) and the output of the feedback multiplexer 200 and the output of the (i+1)th register R(i+1) perform a logical exclusive or (XOR) operation result.

FIG. 5B is a schematic diagram of the arithmetic logic circuit as shown in FIG. 5A, and FIG. 5B is an exemplary implementation manner. Of course, the present invention is not limited thereto. In this example, the operational logic circuit Cal _G includes a multiplexer 210 and an XOR gate 212. The multiplexer 210(i) of the i-th operation logic circuit Cal _G (i) selects one of three inputs according to the i-th section B(i) of the second control material B (which may include a plurality of bits) An output.

According to the example shown in FIG. 5A, it can be determined by the second control data B whether the input of each register is directly connected to the previous stage register, or the result of the XOR operation of the feedback signal is equivalent to the decision. The tap position of the LFSR determines the polynomial used. The bit width of the first control data A may be related to the input quantity of the feedback multiplexer 200. Taking n=4 as an example, the feedback multiplexer 200 is a four-to-one multiplexer, and the first control data A can be a 2-bit control signal to select one of the four inputs, and the feedback multiplexer 200 determines which slave register to send back to, which determines the number of registers in series. Therefore, the linear feedback shift register 100_G shown in FIG. 5A can change the bit length according to the first control data A, and change the return point position according to the second control data B.

FIG. 6A is a schematic diagram of an elastic linear feedback shift register according to an embodiment of the present invention. In this example, a right-shifted Fibonacci architecture is used, and n=4 is taken as an example. The linear feedback shift register 100_F includes n register R(1)~R(n), (n-1) arithmetic logic circuits Cal _F (1)~Cal _F (n-1), (n -2) Switching switches S(1)~S(n-2).

FIG. 6B is a schematic diagram of the arithmetic logic circuit as shown in FIG. 6A. The i-th operational logic circuit Cal _F (i) includes a multiplexer 310(i) and a logical exclusive OR (XOR) gate 312(i) having a first input and a second input a control mutex or an output terminal, the logic mutex or gate 312(i) has a first input terminal, a second input terminal, and an output terminal, and the first input terminal of the multiplexer 310(i) is coupled to the logic mutual exclusion Or the output of the gate 312(i), the second input of the multiplexer 310(i) is coupled to the second input of the logic mutex or gate 312(i), and the selection control terminal of the multiplexer 310(i) The i-th segment B(i) of the second control signal B (which may be 1 bit) is coupled, and the first input of the logical mutex or gate 312(i) is coupled to the (i+1)th temporary The output of the register R(i+1).

The i-th switch S(i) will be the (i+1)th register R(i+1) according to the i-th segment A(i) of the first control data A (which may be 1 bit) The input terminal is selectively coupled to one of the following pins: the output of the (i+2)th register R(i+2), and the ith operational logic circuit Cal _F (i) The output of the multiplexer 310(i). If i=1, the logical input of the i-th operational logic circuit Cal _F (i) or the second input of the gate 312(i) is coupled to the output of the i-th register R(i); ≦i≦n-1, the logical mutex of the i-th operation logic circuit Cal _F (i) or the second input terminal of the gate 312(i) is coupled to the (i-1)th operation logic circuit Cal _F (i- 1) The output of the multiplexer.

According to the example shown in FIG. 6A, the second control data B determines whether the output of each register passes an XOR operation by a feedback path (separated by the arithmetic logic circuit Cal _{F in} series), which is equivalent to determining the tap position of the LFSR. That determines the polynomial used. The first control data A can control the position of disconnection between the registers, and where the feedback is formed, which determines the number of registers in series. Therefore, the linear feedback shift register 100_F shown in FIG. 6A can change the bit length according to the first control data A, and change the return point position according to the second control data B.

In the Fibonacci architecture, the feedback path formed by the arithmetic logic circuit Cal _F includes a plurality of XOR gates connected in series, which becomes a critical path of the circuit delay, and the calculation path exists in the first register and the last temporary Between the registers. In contrast, in the Galois architecture, there is at most one operational logic circuit Cal _G (including an XOR gate) between each register, so the critical path is shorter, allowing the circuit to operate at a higher frequency. For applications with higher speed requirements, you can choose to use the LFSR of the Galois architecture.

The data stored in the look-up table circuit 102 will be described in detail below. FIG. 7 is a schematic diagram of sampling a data sequence generated by an LFSR at regular intervals according to an embodiment of the present invention. Here, n=4 is taken as an example to illustrate that the length of the MLS generated by the LFSR using the primitive polynomial sequence is 15 (=2). ⁿ -1), the position information corresponding to each code in the MLS is as shown in Fig. 7, which is sequentially arranged from 0001 to 1111. The look-up table circuit 102 can store part of the contents of the table in FIG. For example, the k types of data stored by the lookup table circuit 102 are determined by sampling (2 ⁿ -1) data at a fixed interval m. As in the example shown in FIG. 7, the fixed interval m=4, so the lookup table circuit 102 can successfully find the location information corresponding to the positioning absolute codes {1000}, {0111}, {1101}, {0100} (eg, In the dark part of the figure, if the state of the LFSR register does not belong to the four types, the look-up table circuit 102 cannot successfully find the data, and the output table valid flag VF is designated as invalid.

Taking the example shown in FIG. 7, FIG. 8 is a schematic diagram showing the correspondence relationship of the data of the look-up table circuit according to an embodiment of the present invention. Since the look-up table circuit 102 only stores 4 pieces of data, the corresponding data does not need to store all the bits. In this example, only two pieces of position information from the Most Significant Bit (MSB) need to be stored. The bit, which is enough to represent 4 different data, can be stored as shown in the data bar of Figure 8. When performing the decoding, after reading the table lookup result value Y, the table lookup result value Y is shifted to the left by 2 bits, and then the least significant bit (LSB) is added to the 2 bits of the least significant bit (LSB). You can restore your original location information.

In one embodiment, the fixed interval m has a length of 2 ^p and p is a positive integer less than n. As in the examples shown in Figures 7 and 8, n = 4, p = 2. The advantage of sampling at a fixed interval of 2 ^p is that the p bits close to the LSB can be directly truncated. As in the example shown in Fig. 8, the position information of Fig. 7 is directly brought close to the p bits of the LSB. Truncated. In the decoding and restoration, it is also possible to directly shift the result Y of the look-up table to the left by p bits. The p bits are truncated so that the p bit information missing from the original full position information can be complemented by the counter 104, that is, the counter 104 can be a counter of p bits, and the calculation circuit 106 can check the result value of the table. After Y is shifted to the left by p bits, the count result value C of the p bits generated by the counter 104 is added to obtain the decoding result Z.

As shown in Fig. 7 and Fig. 8, by using a fixed interval m = 2 ^p for sampling, the size of the look-up table can be effectively reduced to the original (1/m), and the truncated p-bits are more More, the size of the lookup table can be smaller. For example, for an optical scale with 2 ¹² scales, sampling can be performed by a fixed interval of m=2 ⁴ , so that the size of the look-up table can be reduced to 1/16 times, and the circuit area is greatly reduced. Of course, sampling here with the power of m equal to 2 as an interval is merely an illustrative example, and in practice m may also be a positive integer such as 10, 50, 100, and the like. When the decoding is performed, the calculation circuit 106 may multiply the look-up result value Y by m, and add the count result value C generated by the counter 104 to obtain the decoding result Z.

The look-up table circuit 102 outputs the look-up result value Y and the look-up table effective flag VF, and the circuit implementation can be implemented in various ways. For example, the look-up table circuit 102 may include a determination circuit. When the look-up table circuit 102 cannot successfully find the corresponding look-up table data according to the values stored by the n registers, the look-up result value Y is a preset output value Q. The judging circuit can generate the table look-up valid flag VF by judging whether the preset output value Q and the look-up table result value Y are equal. In another embodiment, when the look-up table circuit 102 cannot successfully find the corresponding look-up table data, the look-up table result value Y can maintain the look-up result value Y output by the previous clock.

The look-up table circuit 102 can be implemented by a memory circuit. As shown in the example of FIG. 8, when the address of the memory is input, the corresponding data is found. Due to the lookup The data stored in the circuit 102 is the sampled discontinuous data, the address information is not regularly arranged, and the number of input address bits and the number of output data bits may not be equal, so in an embodiment, The table circuit 102 can be implemented by a combinational circuit.

FIG. 9 is a schematic diagram of a truth table of a table lookup circuit according to an embodiment of the invention. This example is to take the 7th and 8th pictures. For the sampled data (dark part of the table), the table valid flag VF is set to 1, and the table lookup result value Y is as shown in Fig. 8. For the unsampled data (light color part of the table), the look-up table effective flag VF is set to 0, and the look-up table result value Y may be the don't care term. The truth table shown in Figure 9 is a correspondence between 4 inputs and 3 outputs (the table result value Y has 2 bits, and the table valid flag VF has 1 bit), which can be composed of logic synthesis technology. Completing the corresponding combinational logic circuit, the number of logic gates can be optimized due to the elasticity of the random term x. The combinatorial logic circuit has no memory effect, and can determine the output result according to the current input, and can complete the hardware implementation of saving the circuit area for a specific table lookup requirement.

In an embodiment, the look-up table circuit 102 can be implemented using a programmable logic array (PLA), so that multiple inputs (table address) and output can be implemented (check result value Y and table look-up valid flag) Corresponding relationship of VF), FIG. 10 is a schematic diagram showing the circuit implementation of the look-up table circuit according to an embodiment of the present invention. The PLA can implement diverse combinational logic, and can control the example in FIG. 10 according to the actual table lookup content. Switching of the switch.

An example of the operation of the decoding apparatus and method of the present disclosure in timing will be described below using an example. 11 is a diagram showing a decoding process according to an embodiment of the present invention. schematic diagram. At time t0, the positioning absolute code X loaded by the linear feedback shift register 100 is 0101, and the look-up table circuit 102 cannot find the data, so the table valid flag VF indication is invalid, and the linear feedback shift is temporarily suspended. The register 100 performs a displacement operation, and the counter 104 starts to accumulate. At time t1, the data stored in the shifted linear feedback shift register 100 is 1011, and the lookup circuit 102 still cannot find the data, and the table valid flag VF indication is still invalid, and the count result value is 1 at this time. .

At time t2, the data stored in the linear feedback feedback register 100 after the displacement is 0111 again, and the look-up table circuit 102 successfully finds the data, and the corresponding look-up result value Y is, for example, 01, and the result value C is counted at this time. Is 2. Since the lookup table effective flag VF indication is valid, the calculation circuit 106 can shift the lookup result value Y to the left by 2 bits (or multiply by 4), and can make up the originally truncated 2 bits ("01"), and then Adding the count result value C=2, and obtaining the decoding result Z=0101 (01 left shift 2 bits and then 01) +0010 (binary representation of 2)=0111. Referring to FIG. 7, when the absolute code X=0101 is located, the corresponding position information is 0111.

At this time, the decoding operation has been completed, and the calculation circuit 106 has successfully output the decoding result Z, so the calculation circuit 106 can be appropriately controlled so that the circuit action at a subsequent time no longer affects the output result. As in the embodiment shown in FIG. 4, the decoding device 2 includes the time-switching circuit 108, and the clock signal oscillation can be stopped at the beginning of time t3, so that the linear feedback shift register 100 and the counter 104 are stopped. The operation ensures that the circuit works correctly and reduces power consumption.

In the above, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention is defined by the scope of the appended claims. quasi.

Claims (17)

A decoding device for locating an absolute code, the decoding device comprising: a linear feedback shift register comprising n registers, wherein the n registers load a positioning absolute code at a first frequency, and according to a clock signal is subjected to a shift operation, the clock signal has a second frequency, and the second frequency is not less than the first frequency; a look-up table circuit, according to the value stored by the n register registers, corresponding to the output one look-up table The result value and a table check valid flag, wherein the check result value has k different materials, k ≦ (2 ⁿ -1), the check table valid flag indicates whether the check result value is valid; a counter, according to The look-up table valid flag is reset, and a counting operation is performed according to the clock signal to generate a count result value; and a calculating circuit is configured to perform the look-up table according to the look-up table when the look-up table valid flag indication is valid The result value and the count result value calculation yield a decoding result. The decoding device of claim 1, further comprising a clock switch circuit, wherein the clock switch circuit generates a gated clock signal according to an original clock signal and the look-up table effective flag, and the gate is The clock signal is controlled as the clock signal. The decoding device of claim 1, wherein the linear feedback shift register changes the bit length according to a first control data, and changes the backpoint position according to a second control data. The decoding device of claim 3, wherein the linear feedback shift register further comprises: a feedback multiplexer having a plurality of inputs, a selection control terminal, and an output terminal, wherein The selection control end of the feedback multiplexer is coupled to the first control data, The plurality of input ends of the feedback multiplexer are respectively coupled to the output ends of the n register registers; and (n-1) operation logic circuits, wherein the ith operation logic circuit is configured according to the second control data The i-th bit selectively couples the input of the i-th register to one of the following pins: the output of the feedback multiplexer, the (i+1)th temporary storage The output of the device, and the output of the feedback multiplexer and the output of the (i+1)th register are logically exclusive or the result of the operation. The decoding device of claim 3, wherein the linear feedback shift register further comprises: (n-1) operational logic circuits, wherein the i-th operational logic circuit comprises a multiplexer and a logic mutual exclusion or gate, the multiplexer having a first input terminal, a second input terminal, a control selection terminal, and an output terminal, the logic mutual exclusion gate having a first input terminal and a second input The first input end of the multiplexer is coupled to the output end of the logic mutex or the gate, and the second input end of the multiplexer is coupled to the logic mutual exclusion or gate The second input end, the selection control end of the multiplexer is coupled to the i-th bit of the second control signal, and the first input end of the logic mutex or gate is coupled to the (i+1)th temporary storage And an (n-2) switch, wherein the i-th switch selectively selects the input of the (i+1)th register according to the i-th bit of the first control data Coupling to one of the following pins: an output of the (i+2)th register, and the output of the multiplexer of the i-th arithmetic logic circuit; Where i = 1, the logic of the ith operational logic circuit is mutually exclusive or the second of the gate The input end is coupled to the output end of the i-th register, and if 2≦i≦n-1, the logical input of the i-th operational logic circuit or the second input of the gate is coupled to the first (i-1) The output of the multiplexer of the operational logic circuit. The decoding device of claim 1, wherein the linear feedback shift register uses a primitive polynomial to sequentially generate (2 ⁿ -1) data, the k different materials being based on a fixed interval This is determined by sampling (2 ⁿ -1) data. The decoding device of claim 6, wherein the fixed interval has a length of 2 ^p and p is a positive integer less than n. The decoding device of claim 1, wherein the look-up table circuit comprises a determining circuit, and when the look-up table circuit cannot successfully find the corresponding look-up table data according to the stored values of the n register registers, the checking The result of the table is a preset output value, and the determining circuit determines whether the preset output value and the result of the look-up table are equal to generate the table valid flag. The decoding device of claim 1, wherein the look-up circuit is a combinational logic circuit. The decoding device of claim 1, wherein the calculation circuit performs an addition operation based on the look-up result value and the count result value to generate the decoding result. A decoding method for locating an absolute code, comprising: providing a linear feedback shift register, comprising n temporary registers, wherein the n registers load a positioning absolute code at a first frequency; according to a clock signal Performing a shift operation by the linear feedback shift register, the clock signal having a second frequency, the second frequency being not less than the first frequency; using a lookup table, storing according to the n registers The value corresponds to the output of a look-up table result value and a look-up table valid flag, wherein the look-up table result value has k different kinds of data, k≦(2 ⁿ -1), and the look-up table valid flag indicates the look-up table result value Whether it is valid; performing a counting operation according to the clock signal to generate a count result value, wherein the count result value is reset according to the look-up table valid flag; and when the look-up table valid flag indication is valid, according to the check The table result value and the count result value calculation yield a decoding result. The decoding method of claim 11, further comprising: generating a gated clock signal according to an original clock signal and the table valid flag, and using the gate clock signal as the clock signal . The decoding method of claim 11, further comprising: changing a bit length of the linear feedback shift register according to a first control data; and changing the linear feedback transfer according to a second control data. The location of the callback point of the bit buffer. The decoding method of claim 11, wherein the linear feedback shift register uses a primitive polynomial to generate (2 ⁿ -1) data in a sequence, the k different materials being based on a fixed interval This is determined by sampling (2 ⁿ -1) data. The decoding method of claim 14, wherein the fixed interval has a length of 2 ^p and p is a positive integer less than n. The decoding method as described in claim 11, wherein the lookup table When the circuit cannot successfully find the corresponding lookup table data according to the value stored by the n registers, the result of the lookup table is a preset output value, and the decoding method further comprises determining the preset output value and the result of the lookup table. Whether they are equal to produce the valid flag of the lookup table. The decoding method of claim 11, wherein the step of generating the decoding result according to the table lookup result value and the count result value is performing an addition operation based on the lookup table result value and the count result value.