TWI611322B - In-cell touch panel - Google Patents

In-cell touch panel Download PDF

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TWI611322B
TWI611322B TW105112976A TW105112976A TWI611322B TW I611322 B TWI611322 B TW I611322B TW 105112976 A TW105112976 A TW 105112976A TW 105112976 A TW105112976 A TW 105112976A TW I611322 B TWI611322 B TW I611322B
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layer
electrode
conductive layer
touch panel
thin film
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TW105112976A
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TW201640305A (en
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林依縈
李昆倍
江昶慶
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瑞鼎科技股份有限公司
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Abstract

本發明揭露一種內嵌式觸控面板,包含複數個像素。每個像素之一疊層結構包含一基板、一薄膜電晶體元件層、一液晶層、一彩色濾光層、一玻璃層及一第二導電層。薄膜電晶體元件層設置於基板上。薄膜電晶體元件層內設置有一第一導電層及一共同電壓電極。第一導電層係以網格狀排列。液晶層設置於薄膜電晶體元件層上方。彩色濾光層設置於液晶層上方。玻璃層設置於彩色濾光層上方。第二導電層設置於玻璃層上方。 The invention discloses an in-cell touch panel comprising a plurality of pixels. A laminated structure of each pixel comprises a substrate, a thin film transistor element layer, a liquid crystal layer, a color filter layer, a glass layer and a second conductive layer. The thin film transistor element layer is disposed on the substrate. A first conductive layer and a common voltage electrode are disposed in the thin film transistor component layer. The first conductive layers are arranged in a grid shape. The liquid crystal layer is disposed above the thin film transistor element layer. The color filter layer is disposed above the liquid crystal layer. The glass layer is disposed above the color filter layer. The second conductive layer is disposed above the glass layer.

Description

內嵌式觸控面板 In-line touch panel

本發明係與觸控面板有關,尤其是關於一種內嵌式觸控面板(In-cell touch panel)。 The present invention relates to a touch panel, and more particularly to an in-cell touch panel.

請參照圖1,圖1係繪示傳統具有On-Cell疊層結構的電容式觸控面板的疊層結構示意圖。如圖1所示,傳統On-Cell的電容式觸控面板之疊層結構1由下至上依序是:基板10、薄膜電晶體(TFT)元件層11、液晶層12、彩色濾光層13、玻璃層14、觸控感應層15、偏光片16、黏合劑17及上覆透鏡18。 Please refer to FIG. 1. FIG. 1 is a schematic diagram showing a laminated structure of a conventional capacitive touch panel having an On-Cell laminated structure. As shown in FIG. 1 , the stacked structure 1 of the conventional On-Cell capacitive touch panel is sequentially from bottom to top: a substrate 10, a thin film transistor (TFT) device layer 11, a liquid crystal layer 12, and a color filter layer 13. The glass layer 14, the touch sensing layer 15, the polarizer 16, the adhesive 17, and the overlying lens 18.

由圖1可知:傳統具有On-Cell疊層結構的電容式觸控面板則是將觸控感應層15設置於玻璃層14的上方,亦即設置於液晶顯示模組之外。雖然傳統具有On-Cell疊層結構的電容式觸控面板之厚度已較單片式玻璃觸控面板(One Glass Solution,OGS)來得薄,但在現今手機、平板電腦及筆記型電腦等可攜式電子產品強調輕薄短小之趨勢下,傳統具有On-Cell疊層結構的電容式觸控面板已達到其極限,無法滿足最薄化的觸控面板設計之需求。 As can be seen from FIG. 1 , the conventional capacitive touch panel having the On-Cell laminated structure has the touch sensing layer 15 disposed above the glass layer 14 , that is, disposed outside the liquid crystal display module. Although the thickness of the traditional capacitive touch panel with On-Cell laminate structure is thinner than that of the one-piece glass touch panel (One Glass Solution, OGS), it is portable in today's mobile phones, tablets and notebook computers. The emphasis on thin and light electronic products, the traditional capacitive touch panel with On-Cell laminated structure has reached its limit, can not meet the needs of the thinnest touch panel design.

有鑑於此,本發明提出一種內嵌式觸控面板,以有效解決先前技術所遭遇到之上述種種問題。 In view of this, the present invention provides an in-cell touch panel to effectively solve the above problems encountered in the prior art.

根據本發明之一具體實施例為一種內嵌式觸控面板。於 此實施例中,內嵌式觸控面板包含複數個像素。每個像素之一疊層結構包含一基板、一薄膜電晶體元件層、一液晶層、一彩色濾光層、一玻璃層及一第二導電層。薄膜電晶體元件層設置於基板上。薄膜電晶體元件層內設置有一第一導電層及一共同電壓電極。第一導電層係以網格狀排列。液晶層設置於薄膜電晶體元件層上方。彩色濾光層設置於液晶層上方。玻璃層設置於彩色濾光層上方。第二導電層設置於玻璃層上方。 An embodiment of the present invention is an in-cell touch panel. to In this embodiment, the in-cell touch panel includes a plurality of pixels. A laminated structure of each pixel comprises a substrate, a thin film transistor element layer, a liquid crystal layer, a color filter layer, a glass layer and a second conductive layer. The thin film transistor element layer is disposed on the substrate. A first conductive layer and a common voltage electrode are disposed in the thin film transistor component layer. The first conductive layers are arranged in a grid shape. The liquid crystal layer is disposed above the thin film transistor element layer. The color filter layer is disposed above the liquid crystal layer. The glass layer is disposed above the color filter layer. The second conductive layer is disposed above the glass layer.

於一實施例中,內嵌式觸控面板係為一內嵌式互電容(Mutual Capacitance)觸控面板。內嵌式互電容觸控面板之觸控電極包含一第一方向電極及一第二方向電極,其中第一方向電極係由網格狀排列的第一導電層所形成且第二方向電極係由第二導電層所形成。 In one embodiment, the in-cell touch panel is an in-line Mutual Capacitance touch panel. The touch electrode of the in-cell mutual-capacitive touch panel includes a first direction electrode and a second direction electrode, wherein the first direction electrode is formed by a grid-shaped first conductive layer and the second direction electrode is A second conductive layer is formed.

於一實施例中,第二導電層係由透明導電材料構成。 In an embodiment, the second conductive layer is composed of a transparent conductive material.

於一實施例中,第一導電層係形成於共同電壓電極之後。 In an embodiment, the first conductive layer is formed after the common voltage electrode.

於一實施例中,第一導電層係形成於共同電壓電極之前。 In one embodiment, the first conductive layer is formed before the common voltage electrode.

於一實施例中,彩色濾光層包含一彩色濾光片(Color Filter)及一黑色矩陣光阻(Black Matrix Resist),黑色矩陣光阻具有良好的光遮蔽性,第一導電層係位於黑色矩陣光阻之下方。 In one embodiment, the color filter layer comprises a color filter and a black matrix resist, the black matrix resist has good light shielding, and the first conductive layer is located in black. Below the matrix photoresist.

於一實施例中,薄膜電晶體元件層中還包含一原有導電層,原有導電層係電性連接共同電壓電極,以作為共同電壓電極之走線並降低共同電壓電極之電阻電容負荷(RC loading)。 In one embodiment, the thin film transistor component layer further includes an original conductive layer, and the original conductive layer is electrically connected to the common voltage electrode to serve as a common voltage electrode trace and reduce the resistance and capacitance load of the common voltage electrode ( RC loading).

於一實施例中,第一方向電極與第二方向電極分別為驅動電極(TX)與感測電極(RX)或第一方向電極與第二方向電極分別為感測電極(RX)與驅動電極(TX)。 In one embodiment, the first direction electrode and the second direction electrode are respectively a driving electrode (TX) and a sensing electrode (RX) or the first direction electrode and the second direction electrode are respectively a sensing electrode (RX) and a driving electrode. (TX).

於一實施例中,觸控電極之區域劃分係根據第一導電層之相連或斷開來決定。 In an embodiment, the area division of the touch electrodes is determined according to the connection or disconnection of the first conductive layer.

於一實施例中,未形成第一方向電極之部分的第一導電層係電性連接共同電壓電極,以作為共同電壓電極之走線並降低共同電壓電極之電阻電容負荷(RC loading)。 In one embodiment, the first conductive layer that is not formed in the first direction electrode is electrically connected to the common voltage electrode to serve as a common voltage electrode trace and reduce the RC loading of the common voltage electrode.

於一實施例中,未形成第一方向電極之部分的第一導電層係設置於觸控電極間之一空缺區域,以與共同電壓電極電性連接。 In one embodiment, the first conductive layer that is not formed in the first direction electrode is disposed in a vacant area between the touch electrodes to be electrically connected to the common voltage electrode.

於一實施例中,薄膜電晶體元件層中之一閘極與另一閘極係彼此相鄰排列於該像素之同一側。 In one embodiment, one of the gate and the other of the thin film transistor elements are adjacent to each other on the same side of the pixel.

於一實施例中,該像素之另一側係設置有未形成第一方向電極之部分的第一導電層或薄膜電晶體元件層中之一原有導電層並與共同電壓電極電性連接,以作為共同電壓電極之走線並降低共同電壓電極之電阻電容負荷(RC loading)。 In one embodiment, the other side of the pixel is provided with one of the first conductive layer or the thin film transistor element layer that is not formed in the first direction electrode and is electrically connected to the common voltage electrode. As a common voltage electrode trace and reduce the RC load of the common voltage electrode.

於一實施例中,當疊層結構具有半源極驅動(Half Source Driving,HSD)架構時,疊層結構會額外多空出一源極線之空間。 In one embodiment, when the stacked structure has a Half Source Driving (HSD) architecture, the stacked structure additionally leaves a space for a source line.

於一實施例中,薄膜電晶體元件層中之一原有導電層係利用額外多空出的源極線之空間與第一導電層電性連接,以作為第一方向電極之走線。 In one embodiment, one of the original conductive layers of the thin film transistor element layer is electrically connected to the first conductive layer by using a space of the extra vacant source line to serve as a trace of the first directional electrode.

於一實施例中,薄膜電晶體元件層還包含一原有導電層,原有導電層係利用額外多空出的源極線之空間與共同電壓電極電性連接,以作為共同電壓電極之走線並降低共同電壓電極之電阻電容負荷(RC loading)。 In one embodiment, the thin film transistor component layer further includes an original conductive layer, and the original conductive layer is electrically connected to the common voltage electrode by using a space of the extra vacant source line to serve as a common voltage electrode. Line and reduce the RC loading of the common voltage electrode.

於一實施例中,第二導電層所形成之第二方向電極之間係設置有一虛設電極(Dummy electrode),並且虛設電極係呈現一浮接(Floating)狀態。 In one embodiment, a dummy electrode is disposed between the second direction electrodes formed by the second conductive layer, and the dummy electrode is in a floating state.

於一實施例中,當內嵌式觸控面板運作於一觸控模式時,共同電壓電極係切換為一浮接(Floating)狀態或施加一觸控相關訊號。 In an embodiment, when the in-cell touch panel operates in a touch mode, the common voltage electrode is switched to a floating state or a touch-related signal is applied.

於一實施例中,內嵌式觸控面板之一觸控模式與一顯示模式係分時驅動,並且內嵌式觸控面板係利用顯示週期之一空白區間(Blanking interval)運作於觸控模式。 In one embodiment, one touch mode and one display mode of the in-cell touch panel are time-divisionally driven, and the in-cell touch panel operates in a touch mode by using a blanking interval of the display period. .

於一實施例中,空白區間係包含一垂直空白區間(Vertical Blanking Interval,VBI)、一水平空白區間(Horizontal Blanking Interval,HBI)及一長水平空白區間(Long Horizontal Blanking Interval)中之至少一種。長水平空白區間的時間長度等於或大於水平空白區間的時間長度,長水平空白區間係重新分配複數個水平空白區間而得或長水平空白區間包含垂直空白區間。 In an embodiment, the blank interval includes at least one of a Vertical Blanking Interval (VBI), a Horizontal Blanking Interval (HBI), and a Long Horizontal Blanking Interval. The length of the long horizontal blank interval is equal to or greater than the length of the horizontal blank interval, and the long horizontal blank interval is a redistribution of a plurality of horizontal blank intervals or the long horizontal blank interval includes a vertical blank interval.

於一實施例中,共同電壓電極具有複數個共同電壓電極區域分別與內嵌式觸控面板之複數個觸控感測電極重疊。當內嵌式觸控面板運作於觸控模式時,複數個觸控感測電極係依序施加複數個觸控感測訊號且共同電壓電極係相對應地依序施加與複數個觸控感測訊號同頻、同幅或同相之複數個觸控相關訊號,或是共同電壓電極係呈現浮接(Floating)狀態。 In one embodiment, the common voltage electrode has a plurality of common voltage electrode regions respectively overlapping with a plurality of touch sensing electrodes of the in-cell touch panel. When the in-cell touch panel is operated in the touch mode, the plurality of touch sensing electrodes sequentially apply a plurality of touch sensing signals and the common voltage electrodes are sequentially applied and the plurality of touch sensing signals are sequentially applied. A plurality of touch-related signals of the same frequency, the same or the same phase, or a common voltage electrode system is in a floating state.

於一實施例中,共同電壓電極具有單一個共同電壓電極區域同時與內嵌式觸控面板之複數個觸控感測電極均重疊。當內嵌式觸控 面板運作於觸控模式時,複數個觸控感測電極係施加一觸控感測訊號且共同電壓電極係施加與觸控感測訊號同頻、同幅或同相之一觸控相關訊號,或是共同電壓電極係呈現浮接(Floating)狀態。 In one embodiment, the common voltage electrode has a single common voltage electrode region and overlaps with a plurality of touch sensing electrodes of the in-cell touch panel. When in-cell touch When the panel is in the touch mode, the plurality of touch sensing electrodes apply a touch sensing signal and the common voltage electrode applies a touch-sensitive signal of the same frequency, the same or the same phase as the touch sensing signal, or It is a common voltage electrode system that exhibits a floating state.

相較於先前技術,根據本發明之內嵌式觸控面板具有下列優點及功效: Compared with the prior art, the in-cell touch panel according to the present invention has the following advantages and effects:

(1)觸控感應電極及其走線之設計簡單。 (1) The design of the touch sensing electrode and its routing is simple.

(2)佈局方式不影響內嵌式觸控面板原有的開口率。 (2) The layout method does not affect the original aperture ratio of the in-cell touch panel.

(3)降低共同電壓電極本身的電阻電容負荷(RC loading)。 (3) Reduce the RC loading of the common voltage electrode itself.

(4)當內嵌式觸控面板運作於觸控模式時,同時控制共同電壓電極以降低內嵌式觸控面板整體之電阻電容負荷。 (4) When the in-cell touch panel operates in the touch mode, the common voltage electrode is simultaneously controlled to reduce the overall resistance and capacitance load of the in-cell touch panel.

(5)將觸控模式與顯示模式分時驅動以提升訊號-雜訊比(Signal-Noise Ratio,SNR)。 (5) Time-division driving of the touch mode and the display mode to improve the signal-to-noise ratio (SNR).

關於本發明之優點與精神可以藉由以下的發明詳述及所附圖式得到進一步的瞭解。 The advantages and spirit of the present invention will be further understood from the following detailed description of the invention.

20‧‧‧共同電壓電極 20‧‧‧Common voltage electrode

21、81‧‧‧第一方向電極 21, 81‧‧‧ first direction electrode

22、82‧‧‧第二方向電極 22, 82‧‧‧second direction electrode

VIA‧‧‧通孔 VIA‧‧‧through hole

3、4、5、6‧‧‧疊層結構 3, 4, 5, 6‧‧‧ laminated structure

30、40、50、60‧‧‧基板 30, 40, 50, 60‧‧‧ substrates

31、41、51、61‧‧‧薄膜電晶體元件層 31, 41, 51, 61‧‧ ‧ thin film transistor component layer

32、42、52、62‧‧‧液晶層 32, 42, 52, 62‧‧‧ liquid crystal layer

33、43、53、63‧‧‧彩色濾光層 33, 43, 53, 63‧‧‧ color filter layers

34、44、54、64‧‧‧玻璃層 34, 44, 54, 64‧‧ ‧ glass layer

35、45、55、65‧‧‧第二導電層 35, 45, 55, 65‧‧‧ second conductive layer

310、410、510、610、710‧‧‧第一導電層 310, 410, 510, 610, 710‧‧‧ first conductive layer

312、412、512、612、712‧‧‧共同電壓電極 312, 412, 512, 612, 712‧‧‧ common voltage electrodes

314、414、514、614、714‧‧‧導電層 314, 414, 514, 614, 714‧‧‧ conductive layers

330、430、530、630‧‧‧黑色矩陣光阻 330, 430, 530, 630‧‧‧ black matrix photoresist

332、432、532、632‧‧‧彩色濾光片 332, 432, 532, 632‧‧‧ color filters

LC‧‧‧液晶單元 LC‧‧‧Liquid Crystal Unit

G‧‧‧閘極 G‧‧‧ gate

S‧‧‧源極 S‧‧‧ source

D‧‧‧汲極 D‧‧‧汲

3A~3C、4A~4C、5A~5C、6A~6C、7A~7C‧‧‧虛線標示的範圍 3A~3C, 4A~4C, 5A~5C, 6A~6C, 7A~7C‧‧‧

83‧‧‧虛設電極 83‧‧‧Dummy electrode

SIM‧‧‧影像訊號 SIM‧‧‧ video signal

HSync‧‧‧水平同步訊號 HSync‧‧‧ horizontal sync signal

VSync‧‧‧垂直同步訊號 VSync‧‧‧ vertical sync signal

STH‧‧‧觸控驅動訊號 STH‧‧‧ touch drive signal

VBI‧‧‧垂直空白區間 VBI‧‧‧ vertical blank interval

HBI‧‧‧水平空白區間 HBI‧‧‧ horizontal blank

LHBI‧‧‧長水平空白區間 LHBI‧‧‧Long horizontal blank

VCOM‧‧‧共同電壓電極 VCOM‧‧‧Common voltage electrode

VCOM1~VCOM3‧‧‧共同電壓電極區域 VCOM1~VCOM3‧‧‧Common voltage electrode area

TX1~TX3‧‧‧觸控感測電極 TX1~TX3‧‧‧Touch sensing electrode

TR‧‧‧走線 TR‧‧‧Wiring

G1~G3‧‧‧閘極驅動訊號 G1~G3‧‧‧ gate drive signal

S1~S3‧‧‧源極驅動訊號 S1~S3‧‧‧ source drive signal

STX1~STX3‧‧‧觸控感測訊號 STX1~STX3‧‧‧ touch sensing signal

SVCOM1~SVCOM3、SVCOM‧‧‧觸控相關訊號 SVCOM1~SVCOM3, SVCOM‧‧‧ touch related signals

圖1係繪示傳統具有On-Cell疊層結構的電容式觸控面板的疊層結構示意圖。 FIG. 1 is a schematic view showing a laminated structure of a conventional capacitive touch panel having an On-Cell laminated structure.

圖2係繪示根據本發明之一具體實施例的內嵌式互電容觸控面板之觸控電極佈局的示意圖。 2 is a schematic diagram of a touch electrode layout of an in-cell mutual-capacitive touch panel according to an embodiment of the invention.

圖3A係繪示本發明之內嵌式互電容觸控面板的疊層結構之第一實施例的剖面示意圖;圖3B係繪示其畫素設計的示意圖。 3A is a cross-sectional view showing a first embodiment of a laminated structure of an in-cell mutual-capacitive touch panel of the present invention; and FIG. 3B is a schematic view showing a pixel design thereof.

圖4A係繪示本發明之內嵌式互電容觸控面板的疊層結構 之第二實施例的剖面示意圖;圖4B係繪示其畫素設計的示意圖。 4A is a stacked structure of an in-cell mutual-capacitive touch panel of the present invention. A schematic cross-sectional view of a second embodiment; FIG. 4B is a schematic diagram of a pixel design.

圖5A係繪示本發明之內嵌式互電容觸控面板的疊層結構之第三實施例的剖面示意圖;圖5B係繪示其畫素設計的示意圖。 5A is a cross-sectional view showing a third embodiment of a laminated structure of an in-cell mutual-capacitive touch panel of the present invention; and FIG. 5B is a schematic view showing a pixel design thereof.

圖6A係繪示本發明之內嵌式互電容觸控面板的疊層結構之第四實施例的剖面示意圖;圖6B係繪示其畫素設計的示意圖。 6A is a cross-sectional view showing a fourth embodiment of a laminated structure of an in-cell mutual-capacitive touch panel of the present invention; and FIG. 6B is a schematic view showing a pixel design thereof.

圖7係繪示當內嵌式互電容觸控面板之疊層結構具有半源極驅動架構時之畫素設計的示意圖。 FIG. 7 is a schematic diagram showing a pixel design when the stacked structure of the in-cell mutual-capacitive touch panel has a half-source driving structure.

圖8A及圖8B係分別繪示內嵌式互電容觸控面板之觸控電極的不同分佈圖樣之示意圖。 8A and 8B are schematic diagrams respectively showing different distribution patterns of touch electrodes of the in-cell mutual-capacitive touch panel.

圖9係繪示由第二導電層所形成之該些第二方向電極之間設置有虛設電極之示意圖。 FIG. 9 is a schematic view showing a dummy electrode disposed between the second directional electrodes formed by the second conductive layer.

圖10A係繪示內嵌式互電容觸控面板利用影像訊號中之空白區間輸出觸控驅動訊號以運作於觸控模式下之示意圖;圖10B係分別繪示垂直空白區間、水平空白區間及長水平空白區間的示意圖。 FIG. 10A is a schematic diagram showing that the in-cell mutual-capacitive touch panel outputs a touch driving signal in a blank interval in the image signal to operate in the touch mode; FIG. 10B shows a vertical blank interval, a horizontal blank interval, and a long length. Schematic diagram of the horizontal blank interval.

圖11A係繪示內嵌式互電容觸控面板中之共同電壓電極具有複數個共同電壓電極區域分別與複數個觸控感測電極重疊的示意圖;圖11B係繪示當內嵌式互電容觸控面板運作於觸控模式時,複數個觸控感測電極依序施加複數個觸控感測訊號且共同電壓電極之複數個共同電壓電極區域相對應地依序施加與複數個觸控感測訊號同頻、同幅或同相之複數個觸控相關訊號的時序圖;圖11C係繪示當內嵌式互電容觸控面板運作於觸控模式時,複數個觸控感測電極依序施加複數個觸控感測訊號且共同電壓電極之複數個共同電壓電極區域均呈現浮接狀態的時序圖。 11A is a schematic diagram showing a common voltage electrode in an in-cell mutual-capacitive touch panel having a plurality of common voltage electrode regions overlapping with a plurality of touch sensing electrodes; FIG. 11B is a diagram showing an in-line mutual capacitance contact. When the control panel is in the touch mode, the plurality of touch sensing electrodes sequentially apply a plurality of touch sensing signals, and the plurality of common voltage electrode regions of the common voltage electrode are sequentially applied and the plurality of touch sensing signals are sequentially applied. A timing diagram of a plurality of touch-related signals of the same frequency, the same or the same phase; FIG. 11C shows that when the embedded mutual-capacitive touch panel operates in the touch mode, a plurality of touch sensing electrodes are sequentially applied. A timing diagram in which a plurality of touch sensing signals and a plurality of common voltage electrode regions of the common voltage electrode are in a floating state.

圖12A係繪示內嵌式互電容觸控面板中之共同電壓電極具有單一個共同電壓電極區域同時與內嵌式互電容觸控面板之複數個觸控感測電極均重疊的示意圖;圖12B係繪示當內嵌式互電容觸控面板運作於觸控模式時,複數個觸控感測電極依序施加複數個觸控感測訊號且共同電壓電極施加與複數個觸控感測訊號同頻、同幅或同相之觸控相關訊號的時序圖;圖12C係繪示當內嵌式互電容觸控面板運作於觸控模式時,複數個觸控感測電極依序施加複數個觸控感測訊號且共同電壓電極呈現浮接狀態的時序圖。 12A is a schematic diagram showing a common voltage electrode in an in-cell mutual-capacitive touch panel having a single common voltage electrode region and overlapping with a plurality of touch sensing electrodes of the in-cell mutual-capacitive touch panel; FIG. 12B When the in-cell mutual-capacitive touch panel is operated in the touch mode, the plurality of touch sensing electrodes sequentially apply a plurality of touch sensing signals and the common voltage electrodes are applied with the plurality of touch sensing signals. Timing diagram of the frequency, the same or the same phase of the touch-related signal; FIG. 12C shows that when the in-cell mutual-capacitive touch panel operates in the touch mode, the plurality of touch sensing electrodes sequentially apply a plurality of touches A timing diagram in which the sense signal and the common voltage electrode assume a floating state.

根據本發明之一具體實施例為一種內嵌式觸控面板。於此實施例中,內嵌式觸控面板係為內嵌式互電容觸控面板(In-cell mutual-capacitive touch panel),但不以此為限。 An embodiment of the present invention is an in-cell touch panel. In this embodiment, the in-cell touch panel is an in-cell mutual-capacitive touch panel, but is not limited thereto.

此實施例中之內嵌式觸控面板包含複數個像素。每個像素之一疊層結構包含基板、薄膜電晶體元件層、液晶層、彩色濾光層、玻璃層及第二導電層。薄膜電晶體元件層設置於基板上。薄膜電晶體元件層內設置有第一導電層及共同電壓電極。第一導電層係以網格狀排列。液晶層設置於薄膜電晶體元件層上方。彩色濾光層設置於液晶層上方。玻璃層設置於彩色濾光層上方。由透明導電材料構成的第二導電層設置於玻璃層上方。 The in-cell touch panel in this embodiment includes a plurality of pixels. One of the stacked structures of each of the pixels includes a substrate, a thin film transistor element layer, a liquid crystal layer, a color filter layer, a glass layer, and a second conductive layer. The thin film transistor element layer is disposed on the substrate. A first conductive layer and a common voltage electrode are disposed in the thin film transistor element layer. The first conductive layers are arranged in a grid shape. The liquid crystal layer is disposed above the thin film transistor element layer. The color filter layer is disposed above the liquid crystal layer. The glass layer is disposed above the color filter layer. A second conductive layer composed of a transparent conductive material is disposed over the glass layer.

請參照圖2,圖2係繪示本發明之內嵌式互電容觸控面板之觸控電極佈局之一實施例。如圖2所示,內嵌式互電容觸控面板之觸控電極包含第一方向電極21及第二方向電極22,其中第一方向電極21係由網 格狀排列的第一導電層所形成且第二方向電極22係由第二導電層所形成。其中,第一方向電極21及第二方向電極22可分別作為互電容觸控感測之驅動電極(TX)與感測電極(RX),抑或第一方向電極21及第二方向電極22可分別作為互電容觸控感測之感測電極(RX)與驅動電極(TX),並無特定之限制。 Please refer to FIG. 2. FIG. 2 illustrates an embodiment of a touch electrode layout of the in-cell mutual-capacitive touch panel of the present invention. As shown in FIG. 2, the touch electrodes of the in-cell mutual-capacitive touch panel include a first direction electrode 21 and a second direction electrode 22, wherein the first direction electrode 21 is a network A lattice-shaped first conductive layer is formed and the second direction electrode 22 is formed by the second conductive layer. The first direction electrode 21 and the second direction electrode 22 can be used as the driving electrode (TX) and the sensing electrode (RX) of the mutual capacitance touch sensing, respectively, or the first direction electrode 21 and the second direction electrode 22 can be respectively The sensing electrode (RX) and the driving electrode (TX) as mutual capacitance touch sensing are not particularly limited.

需說明的是,由於第一導電層及共同電壓電極20係設置於薄膜電晶體元件層內且第二導電層設置於薄膜電晶體元件層上方,因此,第二導電層會位於第一導電層之上方,亦即由第二導電層所形成的第二方向電極22會位於由第一導電層所形成的第一方向電極21之上方。 It should be noted that, since the first conductive layer and the common voltage electrode 20 are disposed in the thin film transistor element layer and the second conductive layer is disposed above the thin film transistor element layer, the second conductive layer may be located on the first conductive layer. Above, that is, the second direction electrode 22 formed by the second conductive layer is located above the first direction electrode 21 formed by the first conductive layer.

此外,共同電壓電極走線TR透過通孔VIA電性連接共同電壓電極20,以降低共同電壓電極20之電阻電容負荷(RC loading)。實際上,共同電壓電極走線TR可由薄膜電晶體元件層中未形成第一方向電極21之部分的第一導電層或是其他原有的導電層所形成,但不以此為限。 In addition, the common voltage electrode trace TR is electrically connected to the common voltage electrode 20 through the via VIA to reduce the RC loading of the common voltage electrode 20. In fact, the common voltage electrode trace TR may be formed by a first conductive layer or other original conductive layer in a portion of the thin film transistor element layer where the first direction electrode 21 is not formed, but is not limited thereto.

接著,請參照圖3A,圖3A係繪示本發明之內嵌式互電容觸控面板的疊層結構之第一實施例的剖面示意圖。如圖3A所示,內嵌式互電容觸控面板的疊層結構3包含基板30、薄膜電晶體元件層31、液晶層32、彩色濾光層33、玻璃層34及第二導電層35。薄膜電晶體元件層31設置於基板30上。薄膜電晶體元件層31內設置有第一導電層310及共同電壓電極312,並且第一導電層310係形成於共同電壓電極312之後。第一導電層310係以網格狀排列。包含複數個液晶單元LC的液晶層32係設置於薄膜電晶體元件層31上方。彩色濾光層33設置於液晶層32上方。玻璃層34設置於彩色濾光層33上方。第二導電層35設置於玻璃層34上方。 3A, FIG. 3A is a cross-sectional view showing a first embodiment of a laminated structure of an in-cell mutual-capacitive touch panel of the present invention. As shown in FIG. 3A, the laminated structure 3 of the in-cell mutual-capacitive touch panel includes a substrate 30, a thin film transistor element layer 31, a liquid crystal layer 32, a color filter layer 33, a glass layer 34, and a second conductive layer 35. The thin film transistor element layer 31 is disposed on the substrate 30. A first conductive layer 310 and a common voltage electrode 312 are disposed in the thin film transistor element layer 31, and the first conductive layer 310 is formed behind the common voltage electrode 312. The first conductive layers 310 are arranged in a grid shape. A liquid crystal layer 32 including a plurality of liquid crystal cells LC is disposed above the thin film transistor element layer 31. The color filter layer 33 is disposed above the liquid crystal layer 32. The glass layer 34 is disposed above the color filter layer 33. The second conductive layer 35 is disposed above the glass layer 34.

需說明的是,彩色濾光層33包含黑色矩陣光阻(Black Matrix Resist)330及彩色濾光片(Color Filter)332。網格狀排列的第一導電層310係設置於黑色矩陣光阻330之下方,藉以透過具有良好的光遮蔽性之黑色矩陣光阻330來遮蔽下方的第一導電層310。 It should be noted that the color filter layer 33 includes a black matrix resist (Black Matrix Resist) 330 and a color filter (Color Filter) 332. The grid-shaped first conductive layer 310 is disposed under the black matrix photoresist 330 to shield the underlying first conductive layer 310 through the black matrix photoresist 330 having good light shielding properties.

亦請參照圖3B,圖3B係繪示本發明之內嵌式互電容觸控面板之畫素設計的示意圖。如圖3B所示,內嵌式互電容觸控面板之觸控電極的區域劃分係根據第一導電層310之相連或斷開來決定。 Please refer to FIG. 3B. FIG. 3B is a schematic diagram showing the pixel design of the in-cell mutual-capacitive touch panel of the present invention. As shown in FIG. 3B, the area division of the touch electrodes of the in-cell mutual-capacitive touch panel is determined according to the connection or disconnection of the first conductive layer 310.

舉例而言,於虛線標示的範圍3A內,由於第一導電層310彼此相連,故上下畫素屬於同一個觸控電極範圍;於虛線標示的範圍3C內,由於第一導電層310彼此斷開,故上下畫素屬於不同的觸控電極範圍。此外,於虛線標示的範圍3B內,未形成第一方向電極之部分的第一導電層310可設置於觸控電極間之一空缺區域,並可透過通孔VIA與共同電壓電極312電性連接,但不以此為限。 For example, in the range 3A indicated by the broken line, since the first conductive layers 310 are connected to each other, the upper and lower pixels belong to the same touch electrode range; in the range 3C indicated by the broken line, the first conductive layers 310 are disconnected from each other. Therefore, the upper and lower pixels belong to different touch electrode ranges. In addition, in the range 3B indicated by the broken line, the first conductive layer 310 not forming the portion of the first direction electrode may be disposed in a vacant area between the touch electrodes, and may be electrically connected to the common voltage electrode 312 through the through hole VIA. , but not limited to this.

接著,請參照圖4A,圖4A係繪示本發明之內嵌式互電容觸控面板的疊層結構之第二實施例的剖面示意圖。如圖4A所示,內嵌式互電容觸控面板的疊層結構4包含基板40、薄膜電晶體元件層41、液晶層42、彩色濾光層43、玻璃層44及第二導電層45。薄膜電晶體元件層41設置於基板40上。薄膜電晶體元件層41內設置有第一導電層410及共同電壓電極412,並且第一導電層410係形成於共同電壓電極412之前。第一導電層410係以網格狀排列。包含複數個液晶單元LC的液晶層42係設置於薄膜電晶體元件層41上方。彩色濾光層43設置於液晶層42上方。玻璃層44設置於彩色濾光層43上方。第二導電層45設置於玻璃層44上方。 4A, FIG. 4A is a cross-sectional view showing a second embodiment of the laminated structure of the in-cell mutual-capacitive touch panel of the present invention. As shown in FIG. 4A , the stacked structure 4 of the in-cell mutual-capacitive touch panel comprises a substrate 40 , a thin film transistor element layer 41 , a liquid crystal layer 42 , a color filter layer 43 , a glass layer 44 , and a second conductive layer 45 . The thin film transistor element layer 41 is disposed on the substrate 40. A first conductive layer 410 and a common voltage electrode 412 are disposed in the thin film transistor element layer 41, and the first conductive layer 410 is formed before the common voltage electrode 412. The first conductive layers 410 are arranged in a grid shape. A liquid crystal layer 42 including a plurality of liquid crystal cells LC is disposed above the thin film transistor element layer 41. The color filter layer 43 is disposed above the liquid crystal layer 42. The glass layer 44 is disposed above the color filter layer 43. The second conductive layer 45 is disposed above the glass layer 44.

需說明的是,彩色濾光層43包含黑色矩陣光阻430及彩色濾光片432。網格狀排列的第一導電層410係設置於黑色矩陣光阻430之下方,藉以透過具有良好的光遮蔽性之黑色矩陣光阻430來遮蔽下方的第一導電層410。 It should be noted that the color filter layer 43 includes a black matrix photoresist 430 and a color filter 432. The grid-shaped first conductive layer 410 is disposed under the black matrix photoresist 430 to shield the underlying first conductive layer 410 through the black matrix photoresist 430 having good light shielding properties.

亦請參照圖4B,圖4B係繪示本發明之內嵌式互電容觸控面板之畫素設計的示意圖。如圖4B所示,內嵌式互電容觸控面板之觸控電極的區域劃分係根據第一導電層410之相連或斷開來決定。 Please refer to FIG. 4B. FIG. 4B is a schematic diagram showing the pixel design of the in-cell mutual-capacitive touch panel of the present invention. As shown in FIG. 4B, the area division of the touch electrodes of the in-cell mutual-capacitive touch panel is determined according to the connection or disconnection of the first conductive layer 410.

舉例而言,於虛線標示的範圍4A內,由於第一導電層410彼此相連,故上下畫素屬於同一個觸控電極範圍;於虛線標示的範圍4C內,由於第一導電層410彼此斷開,故上下畫素屬於不同的觸控電極範圍。此外,於虛線標示的範圍4B內,未形成第一方向電極之部分的第一導電層410可設置於觸控電極間之一空缺區域,並可透過通孔VIA與共同電壓電極412電性連接,但不以此為限。 For example, in the range 4A indicated by the broken line, since the first conductive layers 410 are connected to each other, the upper and lower pixels belong to the same touch electrode range; in the range 4C indicated by the broken line, the first conductive layers 410 are disconnected from each other. Therefore, the upper and lower pixels belong to different touch electrode ranges. In addition, in the range 4B indicated by the broken line, the first conductive layer 410 of the portion where the first direction electrode is not formed may be disposed in a vacant area between the touch electrodes, and may be electrically connected to the common voltage electrode 412 through the through hole VIA. , but not limited to this.

接著,請參照圖5A,圖5A係繪示本發明之內嵌式互電容觸控面板的疊層結構之第三實施例的剖面示意圖。如圖5A所示,內嵌式互電容觸控面板的疊層結構5包含基板50、薄膜電晶體元件層51、液晶層52、彩色濾光層53、玻璃層54及第二導電層55。薄膜電晶體元件層51設置於基板50上。薄膜電晶體元件層51內設置有第一導電層510及共同電壓電極512,並且第一導電層510係形成於共同電壓電極512之後。第一導電層510係以網格狀排列。包含複數個液晶單元LC的液晶層52係設置於薄膜電晶體元件層51上方。彩色濾光層53設置於液晶層52上方。玻璃層54設置於彩色濾光層53上方。第二導電層55設置於玻璃層54上方。 Next, please refer to FIG. 5A. FIG. 5A is a cross-sectional view showing a third embodiment of a laminated structure of an in-cell mutual-capacitive touch panel of the present invention. As shown in FIG. 5A, the laminated structure 5 of the in-cell mutual-capacitive touch panel includes a substrate 50, a thin film transistor element layer 51, a liquid crystal layer 52, a color filter layer 53, a glass layer 54, and a second conductive layer 55. The thin film transistor element layer 51 is disposed on the substrate 50. A first conductive layer 510 and a common voltage electrode 512 are disposed in the thin film transistor element layer 51, and the first conductive layer 510 is formed behind the common voltage electrode 512. The first conductive layers 510 are arranged in a grid shape. A liquid crystal layer 52 including a plurality of liquid crystal cells LC is disposed above the thin film transistor element layer 51. The color filter layer 53 is disposed above the liquid crystal layer 52. The glass layer 54 is disposed above the color filter layer 53. The second conductive layer 55 is disposed above the glass layer 54.

需說明的是,彩色濾光層53包含黑色矩陣光阻530及彩色濾光片532。網格狀排列的第一導電層510係設置於黑色矩陣光阻530之下方,藉以透過具有良好的光遮蔽性之黑色矩陣光阻530來遮蔽下方的第一導電層510。 It should be noted that the color filter layer 53 includes a black matrix photoresist 530 and a color filter 532. The grid-shaped first conductive layer 510 is disposed under the black matrix photoresist 530 to shield the underlying first conductive layer 510 through the black matrix photoresist 530 having good light shielding properties.

亦請參照圖5B,圖5B係繪示本發明之內嵌式互電容觸控面板之畫素設計的示意圖。如圖5B所示,內嵌式互電容觸控面板之觸控電極的區域劃分係根據第一導電層510之相連或斷開來決定。 Please refer to FIG. 5B. FIG. 5B is a schematic diagram showing the pixel design of the in-cell mutual-capacitive touch panel of the present invention. As shown in FIG. 5B, the area division of the touch electrodes of the in-cell mutual-capacitive touch panel is determined according to the connection or disconnection of the first conductive layer 510.

舉例而言,於虛線標示的範圍5A內,由於第一導電層510彼此斷開,故上下畫素屬於不同的觸控電極範圍;於虛線標示的範圍5C內,由於第一導電層510彼此相連,故上下畫素屬於同一個觸控電極範圍。此外,於虛線標示的範圍5B內,未形成觸控電極之導電層(例如閘極導電層G)可透過通孔VIA與共同電壓電極512電性連接,但不以此為限。 For example, in the range 5A indicated by the broken line, since the first conductive layers 510 are disconnected from each other, the upper and lower pixels belong to different touch electrode ranges; in the range 5C indicated by the broken lines, the first conductive layers 510 are connected to each other. Therefore, the upper and lower pixels belong to the same touch electrode range. In addition, the conductive layer (for example, the gate conductive layer G) of the touch electrode is electrically connected to the common voltage electrode 512 through the through hole VIA, but is not limited thereto.

需特別說明的是,如圖5B所示,薄膜電晶體元件層中之兩閘極G可彼此相鄰排列於像素之同一側,藉此可縮減位於上方之黑色矩陣光阻的寬度。此外,像素之另一側可設置有未形成第一方向電極之部分的第一導電層510或薄膜電晶體元件層中之其他原有導電層並與共同電壓電極512電性連接,以作為共同電壓電極512之走線並降低共同電壓電極512之電阻電容負荷。 It should be particularly noted that, as shown in FIG. 5B, the two gates G in the thin film transistor element layer may be arranged adjacent to each other on the same side of the pixel, whereby the width of the black matrix photoresist located above may be reduced. In addition, the other side of the pixel may be provided with a first conductive layer 510 that does not form a portion of the first direction electrode or other original conductive layer in the thin film transistor element layer and is electrically connected to the common voltage electrode 512 as a common The voltage electrode 512 is routed and reduces the resistance and capacitance load of the common voltage electrode 512.

接著,請參照圖6A,圖6A係繪示本發明之內嵌式互電容觸控面板的疊層結構之第四實施例的剖面示意圖。如圖6A所示,內嵌式互電容觸控面板的疊層結構6包含基板60、薄膜電晶體元件層61、液晶層62、彩色濾光層63、玻璃層64及第二導電層65。薄膜電晶體元件層61設置於 基板60上。薄膜電晶體元件層61內設置有第一導電層610及共同電壓電極612,並且第一導電層610係形成於共同電壓電極612之前。第一導電層610係以網格狀排列。包含複數個液晶單元LC的液晶層62係設置於薄膜電晶體元件層61上方。彩色濾光層63設置於液晶層62上方。玻璃層64設置於彩色濾光層63上方。第二導電層65設置於玻璃層64上方。 Next, please refer to FIG. 6A. FIG. 6A is a cross-sectional view showing a fourth embodiment of a laminated structure of the in-cell mutual-capacitive touch panel of the present invention. As shown in FIG. 6A, the laminated structure 6 of the in-cell mutual-capacitive touch panel comprises a substrate 60, a thin film transistor element layer 61, a liquid crystal layer 62, a color filter layer 63, a glass layer 64, and a second conductive layer 65. The thin film transistor element layer 61 is disposed on On the substrate 60. A first conductive layer 610 and a common voltage electrode 612 are disposed in the thin film transistor element layer 61, and the first conductive layer 610 is formed before the common voltage electrode 612. The first conductive layers 610 are arranged in a grid shape. A liquid crystal layer 62 including a plurality of liquid crystal cells LC is disposed above the thin film transistor element layer 61. The color filter layer 63 is disposed above the liquid crystal layer 62. The glass layer 64 is disposed above the color filter layer 63. The second conductive layer 65 is disposed above the glass layer 64.

需說明的是,彩色濾光層63包含黑色矩陣光阻630及彩色濾光片632。網格狀排列的第一導電層610係設置於黑色矩陣光阻630之下方,藉以透過具有良好的光遮蔽性之黑色矩陣光阻630來遮蔽下方的第一導電層610。 It should be noted that the color filter layer 63 includes a black matrix photoresist 630 and a color filter 632. The grid-shaped first conductive layer 610 is disposed under the black matrix photoresist 630 to shield the underlying first conductive layer 610 through the black matrix photoresist 630 having good light shielding properties.

亦請參照圖6B,圖6B係繪示本發明之內嵌式互電容觸控面板之畫素設計的示意圖。如圖6B所示,內嵌式互電容觸控面板之觸控電極的區域劃分可根據第一導電層610之相連或斷開來決定。 Please refer to FIG. 6B. FIG. 6B is a schematic diagram showing the pixel design of the in-cell mutual-capacitive touch panel of the present invention. As shown in FIG. 6B, the area division of the touch electrodes of the in-cell mutual-capacitive touch panel can be determined according to the connection or disconnection of the first conductive layer 610.

舉例而言,於虛線標示的範圍6A內,由於第一導電層610彼此斷開,故上下畫素屬於不同的觸控電極範圍;於虛線標示的範圍6C內,由於第一導電層610彼此相連,故上下畫素屬於同一個觸控電極範圍。此外,於虛線標示的範圍6B內,未形成觸控電極之導電層(例如閘極導電層G)可透過通孔VIA與共同電壓電極612電性連接,但不以此為限。 For example, in the range 6A indicated by the broken line, since the first conductive layers 610 are disconnected from each other, the upper and lower pixels belong to different touch electrode ranges; in the range 6C indicated by the broken lines, the first conductive layers 610 are connected to each other. Therefore, the upper and lower pixels belong to the same touch electrode range. In addition, in the range 6B indicated by the broken line, the conductive layer (for example, the gate conductive layer G) that is not formed with the touch electrode can be electrically connected to the common voltage electrode 612 through the through hole VIA, but is not limited thereto.

需特別說明的是,如圖6B所示,薄膜電晶體元件層中之兩閘極G可彼此相鄰排列於像素之同一側,藉此可縮減位於上方之黑色矩陣光阻的寬度。此外,像素之另一側可設置有未形成第一方向電極之部分的第一導電層610或薄膜電晶體元件層中之其他原有導電層並與共同電壓電極612電性連接,以作為共同電壓電極612之走線並降低共同電壓電極 612之電阻電容負荷。 It should be particularly noted that, as shown in FIG. 6B, the two gates G in the thin film transistor element layer may be arranged adjacent to each other on the same side of the pixel, whereby the width of the black matrix photoresist located above may be reduced. In addition, the other side of the pixel may be provided with a first conductive layer 610 that does not form a portion of the first direction electrode or other original conductive layer in the thin film transistor element layer and is electrically connected to the common voltage electrode 612 as a common Trace the voltage electrode 612 and lower the common voltage electrode 611 resistor and capacitor load.

接著,請參照圖7,當內嵌式互電容觸控面板之疊層結構具有半源極驅動(Half Source Driving,HSD)架構時,疊層結構會額外多空出一源極線之空間。於虛線標示的範圍7A及7B內,薄膜電晶體元件層中之原有導電層利用額外多空出的源極線之空間與第一導電層710電性連接,以作為第一導電層710所形成之觸控電極(第一方向電極)之走線。此外,於虛線標示的範圍7C內,薄膜電晶體元件層中之原有導電層亦可利用額外多空出的源極線之空間與共同電壓電極712電性連接,以作為共同電壓電極712之走線並降低共同電壓電極712之電阻電容負荷。 Next, referring to FIG. 7, when the laminated structure of the in-cell mutual-capacitive touch panel has a Half Source Driving (HSD) architecture, the stacked structure additionally has a space of a source line. In the range 7A and 7B indicated by the broken line, the original conductive layer in the thin film transistor element layer is electrically connected to the first conductive layer 710 by using the space of the extra vacant source line as the first conductive layer 710. A trace of the formed touch electrode (first direction electrode). In addition, in the range 7C indicated by the broken line, the original conductive layer in the thin film transistor element layer can also be electrically connected to the common voltage electrode 712 by using the space of the extra vacant source line as the common voltage electrode 712. The wiring is lined down and the resistance and capacitance load of the common voltage electrode 712 is lowered.

於實際應用中,如圖8A及圖8B所示,內嵌式互電容觸控面板之觸控電極包含第一方向電極81及第二方向電極82,其中第一方向電極81係由網格狀排列的第一導電層所形成且第二方向電極82係由第二導電層所形成,並且第二方向電極82係位於第一方向電極81上方。 In a practical application, as shown in FIG. 8A and FIG. 8B, the touch electrodes of the in-cell mutual-capacitive touch panel include a first direction electrode 81 and a second direction electrode 82, wherein the first direction electrode 81 is formed by a grid shape. The aligned first conductive layer is formed and the second directional electrode 82 is formed by the second conductive layer, and the second directional electrode 82 is positioned above the first directional electrode 81.

需說明的是,內嵌式互電容觸控面板之觸控電極分佈圖樣,亦即第一方向電極81與第二方向電極82之間的排列佈局方式並無特定之限制,可以如圖8A、圖8B或其他排列佈局方式。此外,如圖9所示,由第二導電層所形成之該些第二方向電極82之間可設置有虛設電極(Dummy electrode)83,並且虛設電極83係呈現浮接(Floating)狀態,但不以此為限。 It should be noted that the touch electrode distribution pattern of the in-cell mutual-capacitive touch panel, that is, the arrangement manner between the first-direction electrode 81 and the second-direction electrode 82 is not particularly limited, and may be as shown in FIG. 8A. Figure 8B or other arrangement layout. In addition, as shown in FIG. 9, a dummy electrode 83 may be disposed between the second directional electrodes 82 formed by the second conductive layer, and the dummy electrode 83 is in a floating state, but Not limited to this.

本發明之內嵌式互電容觸控面板可於不同時間分別運作於顯示模式與觸控模式下,亦即本發明之內嵌式互電容觸控面板的觸控模式與顯示模式係分時驅動。 The in-cell mutual-capacitive touch panel of the present invention can be respectively operated in the display mode and the touch mode at different times, that is, the touch mode and the display mode of the in-cell mutual-capacitive touch panel of the present invention are time-divisionally driven. .

當內嵌式互電容觸控面板運作於顯示模式時,其閘極驅動器及源極驅動器會分別輸出閘極驅動訊號G1~G3及源極驅動訊號S1~S3,以驅動內嵌式互電容觸控面板的畫素顯示畫面;當內嵌式觸控面板運作於觸控模式時,內嵌式觸控面板中之共同電壓電極可切換為浮接(Floating)狀態或施加一觸控相關訊號,但不以此為限。 When the in-cell mutual-capacitive touch panel operates in the display mode, the gate driver and the source driver respectively output the gate driving signals G1 to G3 and the source driving signals S1 to S3 to drive the in-line mutual capacitance contacts. The pixel display screen of the control panel; when the in-cell touch panel operates in the touch mode, the common voltage electrode in the in-cell touch panel can be switched to a floating state or a touch-related signal is applied. But not limited to this.

請參照圖10A,內嵌式互電容觸控面板係利用影像訊號SIM中之空白區間(Blanking interval)輸出觸控驅動訊號STH,以運作於觸控模式下。內嵌式互電容觸控面板10A會在非顯示時序(亦即空白區間)進行觸控感測。亦請參照圖10B,圖10B係分別繪示垂直空白區間、水平空白區間及長水平空白區間的示意圖。於實際應用中,內嵌式互電容觸控面板可根據不同驅動方式調整其使用的空白區間種類多寡。如圖10B所示,空白區間可包含垂直空白區間(Vertical Blanking Interval)VBI、水平空白區間(Horizontal Blanking Interval)HBI及長水平空白區間LHBI(Long Horizontal Blanking Interval)中之至少一種。其中,長水平空白區間LHBI的時間長度等於或大於水平空白區間HBI的時間長度。長水平空白區間LHBI可以是重新分配複數個水平空白區間HBI而得或是長水平空白區間LHBI包含有垂直空白區間VBI。 Referring to FIG. 10A, the in-cell mutual-capacitive touch panel outputs a touch driving signal STH by using a blanking interval in the image signal SIM to operate in the touch mode. The in-cell mutual-capacitive touch panel 10A performs touch sensing in a non-display timing (ie, a blank interval). Please also refer to FIG. 10B. FIG. 10B is a schematic diagram showing a vertical blank interval, a horizontal blank interval, and a long horizontal blank interval, respectively. In practical applications, the in-line mutual-capacitive touch panel can adjust the number of blank intervals used by the embedded mutual-capacitance touch panel according to different driving modes. As shown in FIG. 10B, the blank section may include at least one of a Vertical Blanking Interval (VBI), a Horizontal Blanking Interval (HBI), and a Long Horizontal Blanking Interval (HH). Wherein, the length of the long horizontal blank interval LHBI is equal to or longer than the length of the horizontal blank interval HBI. The long horizontal blank interval LHBI may be a redistribution of a plurality of horizontal blank intervals HBI or a long horizontal blank interval LHBI including a vertical blank interval VBI.

於實際應用中,本發明之內嵌式互電容觸控面板中之共同電壓電極可具有單一個或複數個共同電壓電極區域,並無特定之限制。 In a practical application, the common voltage electrode in the in-cell mutual-capacitive touch panel of the present invention may have a single one or a plurality of common voltage electrode regions, and is not particularly limited.

於一實施例中,如圖11A所示,內嵌式互電容觸控面板中之共同電壓電極VCOM可具有複數個共同電壓電極區域VCOM1~VCOM3,並且共同電壓電極區域VCOM1~VCOM3分別與複數個 觸控感測電極TX1~TX3重疊。如圖11B及圖11C所示,當內嵌式互電容觸控面板運作於顯示模式時,其閘極驅動器及源極驅動器會分別輸出閘極驅動訊號G1~G3及源極驅動訊號S1~S3,以驅動內嵌式互電容觸控面板的畫素顯示畫面;當內嵌式互電容觸控面板運作於觸控模式時,複數個觸控感測電極TX1~TX3係依序施加複數個觸控感測訊號STX1~STX3且共同電壓電極VCOM之複數個共同電壓電極區域VCOM1~VCOM3係相對應地依序施加與複數個觸控感測訊號STX1~STX3同頻、同幅或同相之複數個觸控相關訊號SVCOM1~SVCOM3(如圖11B所示),或是共同電壓電極VCOM之複數個共同電壓電極區域VCOM1~VCOM3均呈現浮接狀態(如圖11C所示)。 In one embodiment, as shown in FIG. 11A, the common voltage electrode VCOM in the in-cell mutual-capacitive touch panel may have a plurality of common voltage electrode regions VCOM1 VVCOM3, and the common voltage electrode regions VCOM1 VVCOM3 and a plurality of The touch sensing electrodes TX1~TX3 overlap. As shown in FIG. 11B and FIG. 11C, when the in-cell mutual-capacitive touch panel operates in the display mode, the gate driver and the source driver respectively output the gate driving signals G1 to G3 and the source driving signals S1 to S3. In order to drive the pixel display screen of the embedded mutual capacitance touch panel; when the embedded mutual capacitance touch panel operates in the touch mode, the plurality of touch sensing electrodes TX1~TX3 sequentially apply a plurality of touches The plurality of common voltage electrode regions VCOM1 to VCOM3 of the control voltage signals STX1 to STX3 and the common voltage electrode VCOM are sequentially applied with a plurality of the same frequency, the same or the same phase as the plurality of touch sensing signals STX1 to STX3. The touch-related signals SVCOM1 to SVCOM3 (as shown in FIG. 11B) or the plurality of common voltage electrode regions VCOM1 to VCOM3 of the common voltage electrode VCOM are in a floating state (as shown in FIG. 11C).

於另一實施例中,如圖12A所示,內嵌式互電容觸控面板中之共同電壓電極VCOM具有單一個共同電壓電極區域同時與內嵌式互電容觸控面板之複數個觸控感測電極TX1~TX3均重疊。如圖12B及圖12C所示,當內嵌式互電容觸控面板運作於顯示模式時,其閘極驅動器及源極驅動器會分別輸出閘極驅動訊號G1~G3及源極驅動訊號S1~S3,以驅動內嵌式互電容觸控面板的畫素顯示畫面;當內嵌式觸控面板運作於觸控模式時,複數個觸控感測電極TX1~TX3係依序施加複數個觸控感測訊號STX1~STX3且共同電壓電極VCOM係施加與複數個觸控感測訊號STX1~STX3同頻、同幅或同相之一觸控相關訊號SVCOM(如圖12B所示),或是共同電壓電極VCOM呈現浮接狀態(如圖12C所示)。 In another embodiment, as shown in FIG. 12A, the common voltage electrode VCOM in the in-cell mutual-capacitive touch panel has a single common voltage electrode region and a plurality of touch senses of the in-cell mutual-capacitive touch panel. The electrodes TX1~TX3 overlap. As shown in FIG. 12B and FIG. 12C, when the in-cell mutual-capacitive touch panel operates in the display mode, the gate driver and the source driver respectively output the gate driving signals G1 to G3 and the source driving signals S1 to S3. To drive the pixel display of the in-cell mutual-capacitive touch panel; when the in-cell touch panel operates in the touch mode, the plurality of touch sensing electrodes TX1~TX3 sequentially apply a plurality of touch senses The test signals STX1~STX3 and the common voltage electrode VCOM are applied with a plurality of touch sensing signals STX1~STX3 at the same frequency, same or in phase one touch related signal SVCOM (as shown in FIG. 12B), or a common voltage electrode. The VCOM assumes a floating state (as shown in Figure 12C).

相較於先前技術,根據本發明之內嵌式觸控面板具有下列優點及功效: Compared with the prior art, the in-cell touch panel according to the present invention has the following advantages and effects:

(1)觸控感應電極及其走線之設計簡單。 (1) The design of the touch sensing electrode and its routing is simple.

(2)佈局方式不影響內嵌式觸控面板原有的開口率。 (2) The layout method does not affect the original aperture ratio of the in-cell touch panel.

(3)降低共同電壓電極本身的電阻電容負荷。 (3) Reduce the resistance and capacitance load of the common voltage electrode itself.

(4)當內嵌式觸控面板運作於觸控模式時,同時控制共同電壓電極以降低內嵌式觸控面板整體之電阻電容負荷。 (4) When the in-cell touch panel operates in the touch mode, the common voltage electrode is simultaneously controlled to reduce the overall resistance and capacitance load of the in-cell touch panel.

(5)將觸控模式與顯示模式分時驅動以提升訊號-雜訊比。 (5) Time-division driving of the touch mode and the display mode to enhance the signal-to-noise ratio.

由以上較佳具體實施例之詳述,係希望能更加清楚描述本發明之特徵與精神,而並非以上述所揭露的較佳具體實施例來對本發明之範疇加以限制。相反地,其目的是希望能涵蓋各種改變及具相等性的安排於本發明所欲申請之專利範圍的範疇內。藉由以上較佳具體實施例之詳述,係希望能更加清楚描述本發明之特徵與精神,而並非以上述所揭露的較佳具體實施例來對本發明之範疇加以限制。相反地,其目的是希望能涵蓋各種改變及具相等性的安排於本發明所欲申請之專利範圍的範疇內。 The features and spirits of the present invention are intended to be more apparent from the detailed description of the preferred embodiments. On the contrary, the intention is to cover various modifications and equivalents within the scope of the invention as claimed. The features and spirit of the present invention will be more apparent from the detailed description of the preferred embodiments. On the contrary, the intention is to cover various modifications and equivalents within the scope of the invention as claimed.

3‧‧‧疊層結構 3‧‧‧Laminated structure

30‧‧‧基板 30‧‧‧Substrate

31‧‧‧薄膜電晶體元件層 31‧‧‧Thin-film transistor component layer

32‧‧‧液晶層 32‧‧‧Liquid layer

33‧‧‧彩色濾光層 33‧‧‧Color filter layer

34‧‧‧玻璃層 34‧‧‧ glass layer

35‧‧‧第二導電層 35‧‧‧Second conductive layer

310‧‧‧第一導電層 310‧‧‧First conductive layer

312‧‧‧共同電壓電極 312‧‧‧Common voltage electrode

314‧‧‧導電層 314‧‧‧ Conductive layer

330‧‧‧黑色矩陣光阻 330‧‧‧Black matrix photoresist

332‧‧‧彩色濾光片 332‧‧‧Color filters

LC‧‧‧液晶單元 LC‧‧‧Liquid Crystal Unit

G‧‧‧閘極 G‧‧‧ gate

S‧‧‧源極 S‧‧‧ source

D‧‧‧汲極 D‧‧‧汲

Claims (21)

一種內嵌式觸控面板,包含:複數個像素(Pixel),每個像素之一疊層結構包含:一基板;一薄膜電晶體元件層,設置於該基板上,該薄膜電晶體元件層內係設置有一第一導電層(M3)及一共同電壓電極(Common Electrode),其中該第一導電層係以網格狀(Mesh type)排列;一液晶層,設置於該薄膜電晶體元件層上方;一彩色濾光層,設置於該液晶層上方;一玻璃層,設置於該彩色濾光層上方;以及一第二導電層(ITO),設置於該玻璃層上方;其中該第一導電層係形成於該共同電壓電極之後。 An in-cell touch panel comprising: a plurality of pixels (Pixel), one of the stacked structures of each pixel comprises: a substrate; a thin film transistor component layer disposed on the substrate, the thin film transistor component layer A first conductive layer (M3) and a common voltage electrode (Common Electrode) are disposed, wherein the first conductive layer is arranged in a mesh type; a liquid crystal layer is disposed above the thin film transistor element layer a color filter layer disposed above the liquid crystal layer; a glass layer disposed above the color filter layer; and a second conductive layer (ITO) disposed over the glass layer; wherein the first conductive layer It is formed after the common voltage electrode. 如申請專利範圍第1項所述之內嵌式觸控面板,係為一內嵌式互電容(Mutual Capacitance)觸控面板,該內嵌式互電容觸控面板之觸控電極包含一第一方向電極及一第二方向電極,其中該第一方向電極係由網格狀排列的該第一導電層所形成且該第二方向電極係由該第二導電層所形成。 The in-cell touch panel as described in claim 1 is an in-line Mutual Capacitance touch panel, and the touch electrode of the in-cell mutual-capacitive touch panel includes a first a directional electrode and a second directional electrode, wherein the first directional electrode is formed by the first conductive layer arranged in a grid shape and the second directional electrode is formed by the second conductive layer. 如申請專利範圍第1項所述之內嵌式觸控面板,其中該第二導電層係由透明導電材料構成。 The in-cell touch panel of claim 1, wherein the second conductive layer is made of a transparent conductive material. 一種內嵌式觸控面板,包含:複數個像素(Pixel),每個像素之一疊層結構包含:一基板;一薄膜電晶體元件層,設置於該基板上,該薄膜電晶體元件層內係設置有一第一導電層(M3)及一共同電壓電極(Common Electrode),其中該第一導電層係以網格狀(Mesh type)排列; 一液晶層,設置於該薄膜電晶體元件層上方;一彩色濾光層,設置於該液晶層上方;一玻璃層,設置於該彩色濾光層上方;以及一第二導電層(ITO),設置於該玻璃層上方;其中當該內嵌式觸控面板運作於一觸控模式時,該共同電壓電極係切換為一浮接(Floating)狀態或施加一觸控相關訊號。 An in-cell touch panel comprising: a plurality of pixels (Pixel), one of the stacked structures of each pixel comprises: a substrate; a thin film transistor component layer disposed on the substrate, the thin film transistor component layer The first conductive layer (M3) and a common voltage electrode (Common Electrode) are disposed, wherein the first conductive layer is arranged in a mesh type; a liquid crystal layer disposed above the thin film transistor element layer; a color filter layer disposed above the liquid crystal layer; a glass layer disposed above the color filter layer; and a second conductive layer (ITO), The common voltage electrode is switched to a floating state or a touch-related signal is applied when the in-cell touch panel operates in a touch mode. 一種內嵌式觸控面板,包含:複數個像素(Pixel),每個像素之一疊層結構包含:一基板;一薄膜電晶體元件層,設置於該基板上,該薄膜電晶體元件層內係設置有一第一導電層(M3)及一共同電壓電極(Common Electrode),其中該第一導電層係以網格狀(Mesh type)排列;一液晶層,設置於該薄膜電晶體元件層上方;一彩色濾光層,設置於該液晶層上方;一玻璃層,設置於該彩色濾光層上方;以及一第二導電層(ITO),設置於該玻璃層上方;其中該第一導電層係形成於該共同電壓電極之前。 An in-cell touch panel comprising: a plurality of pixels (Pixel), one of the stacked structures of each pixel comprises: a substrate; a thin film transistor component layer disposed on the substrate, the thin film transistor component layer A first conductive layer (M3) and a common voltage electrode (Common Electrode) are disposed, wherein the first conductive layer is arranged in a mesh type; a liquid crystal layer is disposed above the thin film transistor element layer a color filter layer disposed above the liquid crystal layer; a glass layer disposed above the color filter layer; and a second conductive layer (ITO) disposed over the glass layer; wherein the first conductive layer It is formed before the common voltage electrode. 一種內嵌式觸控面板,包含:複數個像素(Pixel),每個像素之一疊層結構包含:一基板;一薄膜電晶體元件層,設置於該基板上,該薄膜電晶體元件層內係設置有一第一導電層(M3)及一共同電壓電極(Common Electrode),其中該第一導電層係以網格狀(Mesh type)排列;一液晶層,設置於該薄膜電晶體元件層上方;一彩色濾光層,設置於該液晶層上方; 一玻璃層,設置於該彩色濾光層上方;以及一第二導電層(ITO),設置於該玻璃層上方;其中該彩色濾光層包含一彩色濾光片(Color Filter)及一黑色矩陣光阻(Black Matrix Resist),該黑色矩陣光阻具有良好的光遮蔽性,該第一導電層係位於該黑色矩陣光阻之下方。 An in-cell touch panel comprising: a plurality of pixels (Pixel), one of the stacked structures of each pixel comprises: a substrate; a thin film transistor component layer disposed on the substrate, the thin film transistor component layer A first conductive layer (M3) and a common voltage electrode (Common Electrode) are disposed, wherein the first conductive layer is arranged in a mesh type; a liquid crystal layer is disposed above the thin film transistor element layer a color filter layer disposed above the liquid crystal layer; a glass layer disposed above the color filter layer; and a second conductive layer (ITO) disposed above the glass layer; wherein the color filter layer comprises a color filter and a black matrix Black Matrix Resist, which has good light shielding properties, and the first conductive layer is located below the black matrix photoresist. 一種內嵌式觸控面板,包含:複數個像素(Pixel),每個像素之一疊層結構包含:一基板;一薄膜電晶體元件層,設置於該基板上,該薄膜電晶體元件層內係設置有一第一導電層(M3)及一共同電壓電極(Common Electrode),其中該第一導電層係以網格狀(Mesh type)排列;一液晶層,設置於該薄膜電晶體元件層上方;一彩色濾光層,設置於該液晶層上方;一玻璃層,設置於該彩色濾光層上方;以及一第二導電層(ITO),設置於該玻璃層上方;其中該薄膜電晶體元件層中還包含一原有導電層,該原有導電層係電性連接該共同電壓電極,以作為該共同電壓電極之走線並降低該共同電壓電極之電阻電容負荷(RC loading)。 An in-cell touch panel comprising: a plurality of pixels (Pixel), one of the stacked structures of each pixel comprises: a substrate; a thin film transistor component layer disposed on the substrate, the thin film transistor component layer A first conductive layer (M3) and a common voltage electrode (Common Electrode) are disposed, wherein the first conductive layer is arranged in a mesh type; a liquid crystal layer is disposed above the thin film transistor element layer a color filter layer disposed above the liquid crystal layer; a glass layer disposed above the color filter layer; and a second conductive layer (ITO) disposed over the glass layer; wherein the thin film transistor component The layer further includes an original conductive layer electrically connected to the common voltage electrode to serve as a trace of the common voltage electrode and reduce a RC loading of the common voltage electrode. 一種內嵌式觸控面板,包含:複數個像素(Pixel),每個像素之一疊層結構包含:一基板;一薄膜電晶體元件層,設置於該基板上,該薄膜電晶體元件層內係設置有一第一導電層(M3)及一共同電壓電極(Common Electrode),其中該第一導電層係以網格狀(Mesh type)排列;一液晶層,設置於該薄膜電晶體元件層上方; 一彩色濾光層,設置於該液晶層上方;一玻璃層,設置於該彩色濾光層上方;以及一第二導電層(ITO),設置於該玻璃層上方;其中該內嵌式觸控面板係為一內嵌式互電容觸控面板,該內嵌式互電容觸控面板之觸控電極包含一第一方向電極及一第二方向電極,該第一方向電極係由網格狀排列的該第一導電層所形成且該第二方向電極係由該第二導電層所形成,該第一方向電極與該第二方向電極分別為驅動電極(TX)與感測電極(RX)或該第一方向電極與該第二方向電極分別為感測電極(RX)與驅動電極(TX)。 An in-cell touch panel comprising: a plurality of pixels (Pixel), one of the stacked structures of each pixel comprises: a substrate; a thin film transistor component layer disposed on the substrate, the thin film transistor component layer A first conductive layer (M3) and a common voltage electrode (Common Electrode) are disposed, wherein the first conductive layer is arranged in a mesh type; a liquid crystal layer is disposed above the thin film transistor element layer ; a color filter layer disposed above the liquid crystal layer; a glass layer disposed above the color filter layer; and a second conductive layer (ITO) disposed above the glass layer; wherein the in-cell touch The touch panel of the in-cell mutual-capacitive touch panel includes a first direction electrode and a second direction electrode, and the first direction electrode is arranged in a grid shape. The first conductive layer is formed by the second conductive layer, and the first directional electrode and the second directional electrode are respectively a driving electrode (TX) and a sensing electrode (RX) or The first direction electrode and the second direction electrode are a sensing electrode (RX) and a driving electrode (TX), respectively. 一種內嵌式觸控面板,包含:複數個像素(Pixel),每個像素之一疊層結構包含:一基板;一薄膜電晶體元件層,設置於該基板上,該薄膜電晶體元件層內係設置有一第一導電層(M3)及一共同電壓電極(Common Electrode),其中該第一導電層係以網格狀(Mesh type)排列;一液晶層,設置於該薄膜電晶體元件層上方;一彩色濾光層,設置於該液晶層上方;一玻璃層,設置於該彩色濾光層上方;以及一第二導電層(ITO),設置於該玻璃層上方;其中該內嵌式觸控面板係為一內嵌式互電容觸控面板,該內嵌式互電容觸控面板之觸控電極包含一第一方向電極及一第二方向電極,該第一方向電極係由網格狀排列的該第一導電層所形成且該第二方向電極係由該第二導電層所形成,該觸控電極之區域劃分係根據該第一導電層之相連或斷開來決定。 An in-cell touch panel comprising: a plurality of pixels (Pixel), one of the stacked structures of each pixel comprises: a substrate; a thin film transistor component layer disposed on the substrate, the thin film transistor component layer A first conductive layer (M3) and a common voltage electrode (Common Electrode) are disposed, wherein the first conductive layer is arranged in a mesh type; a liquid crystal layer is disposed above the thin film transistor element layer a color filter layer disposed above the liquid crystal layer; a glass layer disposed above the color filter layer; and a second conductive layer (ITO) disposed over the glass layer; wherein the in-line touch The control panel is an in-cell mutual-capacitive touch panel, and the touch electrode of the in-cell mutual-capacitive touch panel includes a first direction electrode and a second direction electrode, and the first direction electrode is meshed The first conductive layer is formed by the second conductive layer, and the second conductive layer is formed by the second conductive layer. The area division of the touch electrode is determined according to the connection or disconnection of the first conductive layer. 一種內嵌式觸控面板,包含: 複數個像素(Pixel),每個像素之一疊層結構包含:一基板;一薄膜電晶體元件層,設置於該基板上,該薄膜電晶體元件層內係設置有一第一導電層(M3)及一共同電壓電極(Common Electrode),其中該第一導電層係以網格狀(Mesh type)排列;一液晶層,設置於該薄膜電晶體元件層上方;一彩色濾光層,設置於該液晶層上方;一玻璃層,設置於該彩色濾光層上方;以及一第二導電層(ITO),設置於該玻璃層上方;其中該內嵌式觸控面板係為一內嵌式互電容觸控面板,該內嵌式互電容觸控面板之觸控電極包含一第一方向電極及一第二方向電極,該第一方向電極係由網格狀排列的該第一導電層所形成且該第二方向電極係由該第二導電層所形成,未形成該第一方向電極之部分的該第一導電層係電性連接該共同電壓電極,以作為該共同電壓電極之走線並降低該共同電壓電極之電阻電容負荷(RC loading)。 An in-cell touch panel comprising: a plurality of pixels (Pixel), one of the stacked structures of each of the pixels comprises: a substrate; a thin film transistor element layer disposed on the substrate, wherein the first layer of the transistor layer is provided with a first conductive layer (M3) And a common voltage electrode (Common Electrode), wherein the first conductive layer is arranged in a mesh type; a liquid crystal layer is disposed above the thin film transistor element layer; and a color filter layer is disposed on the layer Above the liquid crystal layer; a glass layer disposed above the color filter layer; and a second conductive layer (ITO) disposed above the glass layer; wherein the in-cell touch panel is an in-line mutual capacitor The touch panel of the in-cell mutual-capacitive touch panel includes a first direction electrode and a second direction electrode, wherein the first direction electrode is formed by the first conductive layer arranged in a grid pattern and The second directional electrode is formed by the second conductive layer, and the first conductive layer not forming the portion of the first directional electrode is electrically connected to the common voltage electrode to serve as a trace of the common voltage electrode and is reduced Common voltage electrode Resistive load capacitance (RC loading). 如申請專利範圍第10項所述之內嵌式觸控面板,其中未形成該第一方向電極之該部分的該第一導電層係設置於該觸控電極間之一空缺區域,以與該共同電壓電極電性連接。 The in-cell touch panel of claim 10, wherein the first conductive layer that does not form the portion of the first direction electrode is disposed in a vacant area between the touch electrodes to The common voltage electrode is electrically connected. 一種內嵌式觸控面板,包含:複數個像素(Pixel),每個像素之一疊層結構包含:一基板;一薄膜電晶體元件層,設置於該基板上,該薄膜電晶體元件層內係設置有一第一導電層(M3)及一共同電壓電極(Common Electrode),其中該第一導電層係以網格狀(Mesh type)排列;一液晶層,設置於該薄膜電晶體元件層上方;一彩色濾光層,設置於該液晶層上方; 一玻璃層,設置於該彩色濾光層上方;以及一第二導電層(ITO),設置於該玻璃層上方;其中該薄膜電晶體元件層中之一閘極與另一閘極係彼此相鄰排列於該像素之同一側。 An in-cell touch panel comprising: a plurality of pixels (Pixel), one of the stacked structures of each pixel comprises: a substrate; a thin film transistor component layer disposed on the substrate, the thin film transistor component layer A first conductive layer (M3) and a common voltage electrode (Common Electrode) are disposed, wherein the first conductive layer is arranged in a mesh type; a liquid crystal layer is disposed above the thin film transistor element layer a color filter layer disposed above the liquid crystal layer; a glass layer disposed above the color filter layer; and a second conductive layer (ITO) disposed over the glass layer; wherein one of the gate and the other gate of the thin film transistor element layer The neighbors are arranged on the same side of the pixel. 如申請專利範圍第12項所述之內嵌式觸控面板,其中該像素之另一側係設置有未形成該第一方向電極之部分的該第一導電層或該薄膜電晶體元件層中之一原有導電層並與該共同電壓電極電性連接,以作為該共同電壓電極之走線並降低該共同電壓電極之電阻電容負荷(RC loading)。 The in-cell touch panel of claim 12, wherein the other side of the pixel is provided with the first conductive layer or the thin film transistor element layer in a portion where the first direction electrode is not formed. One of the original conductive layers is electrically connected to the common voltage electrode to serve as a trace of the common voltage electrode and reduce the RC loading of the common voltage electrode. 一種內嵌式觸控面板,包含:複數個像素(Pixel),每個像素之一疊層結構包含:一基板;一薄膜電晶體元件層,設置於該基板上,該薄膜電晶體元件層內係設置有一第一導電層(M3)及一共同電壓電極(Common Electrode),其中該第一導電層係以網格狀(Mesh type)排列;一液晶層,設置於該薄膜電晶體元件層上方;一彩色濾光層,設置於該液晶層上方;一玻璃層,設置於該彩色濾光層上方;以及一第二導電層(ITO),設置於該玻璃層上方;其中該內嵌式觸控面板係為一內嵌式互電容觸控面板,該內嵌式互電容觸控面板之觸控電極包含一第一方向電極及一第二方向電極,該第一方向電極係由網格狀排列的該第一導電層所形成且該第二方向電極係由該第二導電層所形成,當該疊層結構具有半源極驅動(Half Source Driving,HSD)架構時,該疊層結構會額外多空出一源極線之空間。 An in-cell touch panel comprising: a plurality of pixels (Pixel), one of the stacked structures of each pixel comprises: a substrate; a thin film transistor component layer disposed on the substrate, the thin film transistor component layer A first conductive layer (M3) and a common voltage electrode (Common Electrode) are disposed, wherein the first conductive layer is arranged in a mesh type; a liquid crystal layer is disposed above the thin film transistor element layer a color filter layer disposed above the liquid crystal layer; a glass layer disposed above the color filter layer; and a second conductive layer (ITO) disposed over the glass layer; wherein the in-line touch The control panel is an in-cell mutual-capacitive touch panel, and the touch electrode of the in-cell mutual-capacitive touch panel includes a first direction electrode and a second direction electrode, and the first direction electrode is meshed The first conductive layer is formed and the second directional electrode is formed by the second conductive layer. When the laminated structure has a half source driving (HSD) architecture, the laminated structure Extra space is left for a source line. 如申請專利範圍第14項所述之內嵌式觸控面板,其中該薄膜電晶體元件層中之一原有導電層係利用額外多空出的該源極線之空間與該第一導電層電性連接,以作為該第一方向電極之走線。 The in-cell touch panel of claim 14, wherein one of the original conductive layers of the thin film transistor element layer utilizes an extra space of the source line and the first conductive layer. Electrically connected to serve as a trace of the first direction electrode. 如申請專利範圍第14項所述之內嵌式觸控面板,其中該薄膜電晶體元件層還包含一原有導電層,該原有導電層係利用額外多空出的該源極線之空間與該共同電壓電極電性連接,以作為該共同電壓電極之走線並降低該共同電壓電極之電阻電容負荷(RC loading)。 The in-cell touch panel of claim 14, wherein the thin film transistor component layer further comprises an original conductive layer, wherein the original conductive layer utilizes an extra space of the source line The common voltage electrode is electrically connected to serve as a trace of the common voltage electrode and reduce a RC loading of the common voltage electrode. 一種內嵌式觸控面板,包含:複數個像素(Pixel),每個像素之一疊層結構包含:一基板;一薄膜電晶體元件層,設置於該基板上,該薄膜電晶體元件層內係設置有一第一導電層(M3)及一共同電壓電極(Common Electrode),其中該第一導電層係以網格狀(Mesh type)排列;一液晶層,設置於該薄膜電晶體元件層上方;一彩色濾光層,設置於該液晶層上方;一玻璃層,設置於該彩色濾光層上方;以及一第二導電層(ITO),設置於該玻璃層上方;其中該內嵌式觸控面板係為一內嵌式互電容觸控面板,該內嵌式互電容觸控面板之觸控電極包含一第一方向電極及一第二方向電極,該第一方向電極係由網格狀排列的該第一導電層所形成且該第二方向電極係由該第二導電層所形成,該第二導電層所形成之該第二方向電極之間係設置有一虛設電極(Dummy electrode),並且該虛設電極係呈現一浮接(Floating)狀態。 An in-cell touch panel comprising: a plurality of pixels (Pixel), one of the stacked structures of each pixel comprises: a substrate; a thin film transistor component layer disposed on the substrate, the thin film transistor component layer A first conductive layer (M3) and a common voltage electrode (Common Electrode) are disposed, wherein the first conductive layer is arranged in a mesh type; a liquid crystal layer is disposed above the thin film transistor element layer a color filter layer disposed above the liquid crystal layer; a glass layer disposed above the color filter layer; and a second conductive layer (ITO) disposed over the glass layer; wherein the in-line touch The control panel is an in-cell mutual-capacitive touch panel, and the touch electrode of the in-cell mutual-capacitive touch panel includes a first direction electrode and a second direction electrode, and the first direction electrode is meshed An array of the first conductive layer is formed, and the second direction electrode is formed by the second conductive layer, and a dummy electrode is disposed between the second direction electrodes formed by the second conductive layer. And the dummy electrode is A floating (Floating) state. 一種內嵌式觸控面板,包含:複數個像素(Pixel),每個像素之一疊層結構包含: 一基板;一薄膜電晶體元件層,設置於該基板上,該薄膜電晶體元件層內係設置有一第一導電層(M3)及一共同電壓電極(Common Electrode),其中該第一導電層係以網格狀(Mesh type)排列;一液晶層,設置於該薄膜電晶體元件層上方;一彩色濾光層,設置於該液晶層上方;一玻璃層,設置於該彩色濾光層上方;以及一第二導電層(ITO),設置於該玻璃層上方;其中該內嵌式觸控面板之一觸控模式與一顯示模式係分時驅動,並且該內嵌式觸控面板係利用顯示週期之一空白區間(Blanking interval)運作於該觸控模式。 An in-cell touch panel comprising: a plurality of pixels (Pixel), and one of the stacked structures of each pixel comprises: a substrate; a thin film transistor element layer disposed on the substrate, wherein the thin film transistor element layer is provided with a first conductive layer (M3) and a common voltage electrode (Common Electrode), wherein the first conductive layer is a liquid crystal layer disposed above the thin film transistor element layer; a color filter layer disposed above the liquid crystal layer; a glass layer disposed above the color filter layer; And a second conductive layer (ITO) disposed above the glass layer; wherein the touch mode of the in-cell touch panel is driven by a display mode, and the in-cell touch panel is displayed by using One of the cycles, the blanking interval, operates in the touch mode. 如申請專利範圍第18項所述之內嵌式觸控面板,其中該共同電壓電極具有單一個共同電壓電極區域同時與該內嵌式觸控面板之複數個觸控感測電極均重疊,當該內嵌式觸控面板運作於該觸控模式時,該複數個觸控感測電極係施加一觸控感測訊號且該共同電壓電極係施加與該觸控感測訊號同頻、同幅或同相之一觸控相關訊號,或是該共同電壓電極係呈現浮接(Floating)狀態。 The in-cell touch panel of claim 18, wherein the common voltage electrode has a single common voltage electrode region and overlaps with a plurality of touch sensing electrodes of the in-cell touch panel. When the in-cell touch panel is operated in the touch mode, the plurality of touch sensing electrodes apply a touch sensing signal, and the common voltage electrode is applied with the same frequency and the same amplitude as the touch sensing signal. Or one of the in-phase touch-related signals, or the common voltage electrode system is in a floating state. 如申請專利範圍第18項所述之內嵌式觸控面板,其中該空白區間係包含一垂直空白區間(Vertical Blanking Interval,VBI)、一水平空白區間(Horizontal Blanking Interval,HBI)及一長水平空白區間(Long Horizontal Blanking Interval)中之至少一種,該長水平空白區間的時間長度等於或大於該水平空白區間的時間長度,該長水平空白區間係重新分配複數個該水平空白區間而得或該長水平空白區間包含該垂直空白區間。 The in-cell touch panel of claim 18, wherein the blank interval comprises a Vertical Blanking Interval (VBI), a Horizontal Blanking Interval (HBI), and a long horizontal level. At least one of a blank horizontal interval (Long Horizontal Blanking Interval), the length of the long horizontal blank interval being equal to or greater than a length of time of the horizontal blank interval, the long horizontal blank interval being redistributed by the plurality of horizontal blank intervals The long horizontal blank interval contains the vertical blank interval. 如申請專利範圍第18項所述之內嵌式觸控面板,其中該共同電壓電 極具有複數個共同電壓電極區域分別與該內嵌式觸控面板之複數個觸控感測電極重疊,當該內嵌式觸控面板運作於該觸控模式時,該複數個觸控感測電極係依序施加複數個觸控感測訊號且該共同電壓電極係相對應地依序施加與該複數個觸控感測訊號同頻、同幅或同相之複數個觸控相關訊號,或是該共同電壓電極係呈現浮接(Floating)狀態。 The in-cell touch panel of claim 18, wherein the common voltage is electrically The plurality of common voltage electrode regions overlap with the plurality of touch sensing electrodes of the in-cell touch panel, and the plurality of touch sensing electrodes are used when the in-cell touch panel operates in the touch mode. The electrode system sequentially applies a plurality of touch sensing signals, and the common voltage electrode sequentially applies a plurality of touch-related signals in the same frequency, same-sense, or in-phase as the plurality of touch sensing signals, or The common voltage electrode is in a floating state.
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