TWI610404B - Method of manufacture semiconductor package - Google Patents

Abstract

A semiconductor package is provided by first providing a package structure, comprising a carrier member, a semiconductor component disposed on the carrier member, and a package formed on the carrier member and covering the semiconductor component, and forming a barrier layer thereon. The encapsulating material is arranged to block moisture, and then a bearing structure is bonded to the barrier layer, and the carrier is removed, and the barrier layer is designed to block the package when performing a high temperature process. The water in the material overflows to the load-bearing structure, so that the problem of peeling of the load-bearing structure can be avoided. The present invention provides the semiconductor package.

Description

Semiconductor package manufacturing method

The present invention relates to a method of fabricating a semiconductor package, and more particularly to a semiconductor package for preventing delamination and a method of fabricating the same.

With the rapid development of the electronics industry, electronic products are gradually moving towards multi-functional and high-performance trends. In order to meet the packaging requirements for semiconductor package miniaturization, Wafer Level Packaging (WLP) technology was developed.

1A to 1E are schematic cross-sectional views showing a conventional method of fabricating a wafer-level semiconductor package 1.

As shown in FIG. 1A, a thermal release tape 11 is formed on a carrier 10.

Next, a plurality of semiconductor elements 12 are disposed on the thermal release adhesive layer 11, the semiconductor elements 12 having opposite active planes 12a and inactive surfaces 12b, each of which has a plurality of electrode pads 120 thereon, and Each of the active faces 12a is adhered to the thermal release adhesive layer 11.

As shown in FIG. 1B, an encapsulant 13 is formed on the thermal release layer 11 to coat the semiconductor element 12.

As shown in FIG. 1C, the encapsulant 13 is cured, and the encapsulant 13 is further polished to expose the inactive surface 12b of the semiconductor element 12 to the encapsulant 13.

As shown in FIG. 1D, a support member 17 is attached to the encapsulant 13 and the inactive surface 12b of the semiconductor device 12 by a bonding layer 170, and the encapsulant 13 is baked to harden the thermal release type. The adhesive layer 11 removes the thermal release adhesive layer 11 and the carrier 10 to expose the active surface 12a of the semiconductor component 12. Thereafter, the encapsulant 13 is cured.

As shown in FIG. 1E, a circuit redistribution layer (RDL) process is performed to form a line redistribution structure 14 on the encapsulant 13 and the active surface 12a of the semiconductor component 12, so that the circuit is re-wired. The electrode pad 120 of the semiconductor element 12 is electrically connected.

Next, an insulating protective layer 15 is formed on the circuit redistribution structure 14, and the insulating protective layer 15 exposes a portion of the surface of the circuit redistribution structure 14 for bonding the conductive elements 16 such as solder balls.

However, in the manufacturing method of the conventional semiconductor package 1, the process of removing the carrier 10 and the RDL process are both high-temperature processes, and since the encapsulant 13 absorbs moisture, the encapsulant 13 evaporates during the high-temperature process. The water gas causes an out gassing phenomenon, causing the interface between the support member 17 and the encapsulant 13 to leak moisture, which causes the bonding layer 170 to be damaged to peel the support member 17. Therefore, in the structures of FIGS. 1D and 1E, unevenness, warpage, and the like may occur, so that the line redistribution structure 14 cannot be efficiently fabricated, for example, the line redistribution structure 14 and the semiconductor element 12 The alignment between the electrode pads 120 will be offset (due to Drilling error), or the production of uneven lines, resulting in low yield and poor product reliability.

Therefore, how to overcome the various problems of the above-mentioned prior art has become a problem that is currently being solved.

In view of the above-mentioned various deficiencies of the prior art, the present invention provides a semiconductor package comprising: at least one semiconductor component; a package material covering the semiconductor component; and a barrier layer formed on the package to block steam.

In the foregoing semiconductor package, a supporting structure disposed on the barrier layer includes a bonding layer disposed on the barrier layer and a support member disposed on the bonding layer.

The invention provides a method for fabricating a semiconductor package, comprising: providing a package structure, comprising: a carrier member, at least one semiconductor component disposed on the carrier member, and forming on the carrier member and covering the semiconductor component a packaging material; forming a barrier layer on the package material of the package structure to block moisture; bonding a load-bearing structure on the barrier layer, the load-bearing structure comprising a bonding layer disposed on the barrier layer, and being disposed on the bonding layer a support on the layer; and a carrier that removes the package structure.

In the above method, the process of the package structure includes: providing the carrier having an adhesive layer; placing the semiconductor component on the adhesive layer; and forming the package on the adhesive layer to encapsulate the semiconductor element. Further included when the carrier is removed, the adhesive layer is removed. Also included is heating the encapsulant prior to removing the adhesive layer to render the adhesive layer viscous.

In the above method, the encapsulant is formed on the carrier by press molding or molding.

In the above method, the barrier layer is attached thereto by the semi-molten state of the package.

In the above method, the barrier layer is formed on the package by press bonding, sputtering or coating.

In the foregoing method, the package is cured after the carrier is removed.

In the foregoing semiconductor package and method of fabricating the same, the semiconductor device has opposite active and inactive surfaces, the active surface having a plurality of electrode pads, and the semiconductor component is bonded to the carrier with its active surface. After the removal of the carrier, a line redistribution structure is formed on the package and the semiconductor component, and the circuit redistribution structure is electrically connected to the electrode pad of the semiconductor component.

In the above semiconductor package and method of manufacturing the same, the barrier layer is a metal material, an organic material or an inorganic material.

In the foregoing semiconductor package and the method of manufacturing the same, the barrier layer has a thickness of 1 to 15 um.

It can be seen that the semiconductor package of the present invention and the method for manufacturing the same are disposed between the package and the supporting structure by the barrier layer, so that the barrier layer can block the water in the package during any high temperature process. The gas overflows to the load-bearing structure, so that the present invention can avoid the problem of peeling of the support member compared to the prior art.

1,2‧‧‧Semiconductor package

10,20‧‧‧Carrier

11‧‧‧heating release layer

12,22‧‧‧Semiconductor components

12a, 22a‧‧‧ active surface

12b, 22b‧‧‧ inactive surface

120,220‧‧‧electrode pads

13‧‧‧Package colloid

14,24‧‧‧Line redistribution structure

15,25‧‧‧Insulation protective layer

16,26‧‧‧ conductive elements

17,271‧‧‧Support

170, 270‧‧‧ bonding layer

2a‧‧‧Package structure

21‧‧‧Adhesive layer

23‧‧‧Package

240‧‧‧ dielectric layer

241‧‧‧Line layer

242‧‧‧ Conductive blind holes

243‧‧‧Electrical contact pads

27‧‧‧Loading structure

28‧‧‧Barrier

T‧‧‧thickness

S‧‧‧ cutting path

X, Y‧‧‧ arrow direction

1A to 1E are schematic cross-sectional views showing a method of fabricating a conventional semiconductor package; and 2A to 2E are schematic cross-sectional views showing a method of fabricating the semiconductor package of the present invention; and 3A to 3C are diagrams showing a semiconductor package of the present invention; A schematic cross-sectional view of a subsequent process of the process; 3A' is another embodiment of FIG. 3A.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "lower" and "one" are used in the description for convenience of description, and are not intended to limit the scope of the invention, and the relative relationship may be changed or Adjustments, where there is no material change, are considered to be within the scope of the invention.

2A to 2E are schematic cross-sectional views showing a method of fabricating the semiconductor package 2 of the present invention.

As shown in FIG. 2A, a plurality of semiconductor elements 22 are disposed on a carrier 20, the encapsulating material 23 is further formed on the adhesive layer 21 on the carrier 20 to cover the semiconductor elements 22 to form a package structure 2a.

In this embodiment, the carrier 20 is a semiconductor substrate such as a wafer or a silicon plate or a glass substrate, and the carrier 20 is bonded to the semiconductor elements 22 by an adhesive layer 21 on the surface thereof.

Furthermore, the adhesive layer 21 is a thermal release tape.

Moreover, the semiconductor element 22 has an opposite active surface 22a and a non-active surface 22b. The active surface 22a has a plurality of electrode pads 220, and the semiconductor element 22 is bonded to the adhesive layer 21 by its active surface 22a.

In addition, the package material 23 is formed on the carrier 20 by a lamination method or a molding method, and the material of the package material 23 is a dry film type epoxy resin (Epoxy). ) or a fluid epoxy resin, or an organic material such as ABF (Ajinomoto Build-up Film) resin.

As shown in FIG. 2B, a barrier layer 28 is formed on the package 23 (above the inactive surface 22b of the semiconductor component 22), and the barrier layer 28 is used to block moisture.

In the present embodiment, since the package material 23 assumes a semi-molten state (ie, B-stage), the barrier layer 28 can be provided by press-bonding or attaching.

Furthermore, if the package material 23 has no adhesiveness, the barrier layer 28 may be formed on the package material 23 by sputtering or other coated metal material, organic polymer material or inorganic insulating material.

Therefore, the material forming the barrier layer 28 is, for example, a metal material, a liquid organic material such as polyimide (PI), or other materials such as cerium oxide (SiO ₂ ) or tantalum nitride (SiN _{x ).} ) an inorganic material, preferably a metal material.

Further, the barrier layer 28 has a thickness t of from 1 to 15 μm, preferably from 3 to 11 μm.

As shown in FIG. 2C, a supporting structure 27 is bonded to the barrier layer 28, and the supporting structure 27 includes a bonding layer 270 disposed on the barrier layer 28, and a support member 271 disposed on the bonding layer 270. .

In this embodiment, the material of the support member 271 is an inorganic material or an organic material, such as glass, bismuth (Si), ceramic, tantalum carbide (SiC), cerium oxide (SiO ₂ ), arsenic. Gallium arsenide (GaAs), gallium arsenide phosphide (GaAsP), indium phosphide (InP), gallium aluminum arsenide (GaAlAs) or indium gallium phosphide , InGaP), etc., the organic material is, for example, plastic, glass fiber reinforced resin (such as bismaleimide-triazine, BT for short), fiberglass reinforced epoxy resin (such as FR-4) or epoxy resin (epoxy) )Wait.

Furthermore, the bonding layer 270 is a viscous material such as a dry film epoxy resin.

Moreover, the bonding layer 270 is first formed on the support member 271 by spin coating, and the carrier structure 27 is bonded to the barrier layer 28.

In addition, the bonding layer 270 may be formed on the barrier layer 28, and then The support member 271 is bonded to the bonding layer 270.

As shown in FIG. 2D, the carrier 20 and the adhesive layer 21 are removed, and the active surface 22a of the semiconductor element 22 is exposed. Thereafter, the package 23 is cured.

In this embodiment, since the adhesive layer 21 is a thermal release tape, a heating process such as baking is performed to harden the package 23, and the adhesive layer 21 is heated together. The adhesive is lost, thereby removing the adhesive layer 21 and the carrier 20.

As shown in FIG. 2E, a circuit redistribution layer (RDL) process is performed, that is, a line redistribution structure 24 is formed on the package material 23 and the semiconductor elements 22, and the line redistribution structure 24 is electrically Each of the semiconductor elements 22 is connected.

In this embodiment, the circuit redistribution structure 24 includes at least one circuit layer 241 and at least one dielectric layer 240 stacked on each other. The dielectric layer 240 is formed on the package 23, and the circuit layer 241 is The electrode pads 220 of the semiconductor component 22 are electrically connected by a plurality of conductive vias 242.

Then, an insulating protective layer 25 is formed on the circuit redistribution structure 24, and the insulating protective layer 25 exposes a part of the surface of the circuit layer 241, and serves as an electrical contact pad 243 to obtain the semiconductor package 2.

In the manufacturing method of the present invention, after the carrier 20 and the adhesive layer 21 are removed, when the package 23 is cured, part of the moisture in the package 23 will be directed toward the active surface 22a of the semiconductor component 22 (ie, the pattern). The downward arrow direction X) overflows, but another portion of the moisture in the package 23 overflows toward the inactive surface 22b of the semiconductor element 22 (ie, the direction of the upward arrow Y). Therefore, by the design of the barrier layer 28, the upward moisture can be blocked from overflowing to the supporting structure 27 to avoid the failure of the bonding layer 270 to be affected by the moisture, thereby preventing the support member 271 from being peeled off. (peeling) problem.

Therefore, the structure of the semiconductor package 2 does not cause unevenness, warpage, etc., so that the line redistribution structure 24 can be effectively fabricated. For example, when the circuit redistribution structure 24 is fabricated, the conductive blind hole The electrical connection between the 242 and the electrode pads 220 of the semiconductor component 22 can be effectively docked, thereby avoiding problems such as low yield and poor product reliability.

Further, in the subsequent process, as shown in Fig. 3A, the carrier structure 27 and the barrier layer 28 are removed; or, as shown in Fig. 3A', only the carrier structure 27 is removed. Following the process of FIG. 3A, as shown in FIG. 3B, a plurality of conductive elements 26, such as solder balls, are formed on the electrical contact pads 242 of the line redistribution structure 24. Finally, as shown in Fig. 3C, the singulation process is performed along the cutting path S shown in Fig. 3B.

The present invention further provides a semiconductor package 2 comprising: a plurality of semiconductor elements 22, a package material 23, and a barrier layer 28.

The semiconductor component 22 has an opposite active surface 22a and a non-active surface 22b. The active surface 22a has a plurality of electrode pads 220 thereon.

The package material 23 covers the semiconductor elements 22 , and the active surfaces 22 a of the semiconductor elements 22 are exposed to the package 23 .

The barrier layer 28 is formed on the package 23, and the barrier layer 28 is a water blocking layer, such as a metal material, an organic material or an inorganic material.

In one embodiment, the semiconductor package 2 includes a carrier Structure 27. The supporting structure 27 is disposed on the barrier layer 28, and the supporting structure 27 includes a bonding layer 270 disposed on the barrier layer 28 and a support member 271 disposed on the bonding layer 270.

In one embodiment, the semiconductor package 2 includes a circuit redistribution structure 24 formed on the package 23 and the active surface 22a of the semiconductor component 22, and the circuit redistribution structure 24 is electrically connected. The electrode pad 220 of the semiconductor element 22.

In summary, the semiconductor package of the present invention and the manufacturing method thereof are mainly disposed between the package material and the load-bearing structure by the barrier layer, so that when the high-temperature process is performed, the moisture overflow of the package material can be avoided. The bearing structure can avoid the problem that the support member is peeled off.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

2a‧‧‧Package structure

20‧‧‧Carrier

21‧‧‧Adhesive layer

22‧‧‧Semiconductor components

23‧‧‧Package

27‧‧‧Loading structure

270‧‧‧ bonding layer

271‧‧‧Support

28‧‧‧Barrier

Claims (11)

A method for fabricating a semiconductor package, comprising: providing a package structure, comprising: a carrier member, at least one semiconductor component disposed on the carrier member, and a package material formed on the carrier member and covering the semiconductor component; forming a barrier layer is disposed on the package of the package structure to block moisture, wherein the barrier layer is attached to the package by a semi-molten state of the package; and a load-bearing structure is bonded to the barrier layer, the load-bearing structure And comprising a bonding layer disposed on the barrier layer and a support member disposed on the bonding layer; and a carrier for removing the package structure. The method of manufacturing the semiconductor package of claim 1, wherein the process of the package structure comprises: providing the carrier having an adhesive layer; placing the semiconductor component on the adhesive layer; and forming the A package material is on the adhesive layer to encapsulate the semiconductor component. The method of fabricating a semiconductor package according to claim 2, wherein the removing of the carrier is performed, and the adhesive layer is removed. The method of fabricating a semiconductor package according to claim 2, further comprising heating the package before removing the adhesive layer to make the adhesive layer lose its viscosity. For example, the method for manufacturing a semiconductor package as described in claim 1 is Wherein, the semiconductor component has opposite active and non-active surfaces, the active surface has a plurality of electrode pads, and the semiconductor component is bonded to the carrier with its active surface. The method of fabricating a semiconductor package according to claim 1, wherein the package is formed on the carrier by press-bonding or molding. The method of fabricating a semiconductor package according to claim 1, wherein the barrier layer is formed of a metal material, an organic polymer material or an inorganic insulating material. The method of fabricating a semiconductor package according to claim 1, wherein the barrier layer has a thickness of 1 to 15 um. The method of fabricating a semiconductor package according to claim 1, wherein the barrier layer is formed on the package by press bonding, sputtering or coating. The method for manufacturing a semiconductor package according to claim 1, further comprising curing the package after removing the carrier. The method for manufacturing a semiconductor package according to claim 1, further comprising: after removing the carrier, forming a line redistribution structure on the package and the semiconductor component, and the circuit is re-wired. The semiconductor element is connected.