TWI597786B - Semiconductor package structure and manufacturing method thereof - Google Patents
Semiconductor package structure and manufacturing method thereof Download PDFInfo
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- TWI597786B TWI597786B TW102147136A TW102147136A TWI597786B TW I597786 B TWI597786 B TW I597786B TW 102147136 A TW102147136 A TW 102147136A TW 102147136 A TW102147136 A TW 102147136A TW I597786 B TWI597786 B TW I597786B
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- package structure
- semiconductor package
- encapsulant
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- 239000004065 semiconductor Substances 0.000 title claims description 102
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000008393 encapsulating agent Substances 0.000 claims description 33
- 239000000758 substrate Substances 0.000 claims description 30
- 239000010410 layer Substances 0.000 claims description 24
- 239000012790 adhesive layer Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 239000011521 glass Substances 0.000 claims description 6
- 239000004033 plastic Substances 0.000 claims description 4
- 229910052797 bismuth Inorganic materials 0.000 claims 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 claims 1
- 210000003298 dental enamel Anatomy 0.000 claims 1
- 239000000853 adhesive Substances 0.000 description 7
- 230000001070 adhesive effect Effects 0.000 description 7
- 239000000084 colloidal system Substances 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 239000000047 product Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 238000003825 pressing Methods 0.000 description 2
- 239000000565 sealant Substances 0.000 description 2
- 239000012812 sealant material Substances 0.000 description 2
- 239000003566 sealing material Substances 0.000 description 2
- 239000012780 transparent material Substances 0.000 description 2
- SZUVGFMDDVSKSI-WIFOCOSTSA-N (1s,2s,3s,5r)-1-(carboxymethyl)-3,5-bis[(4-phenoxyphenyl)methyl-propylcarbamoyl]cyclopentane-1,2-dicarboxylic acid Chemical compound O=C([C@@H]1[C@@H]([C@](CC(O)=O)([C@H](C(=O)N(CCC)CC=2C=CC(OC=3C=CC=CC=3)=CC=2)C1)C(O)=O)C(O)=O)N(CCC)CC(C=C1)=CC=C1OC1=CC=CC=C1 SZUVGFMDDVSKSI-WIFOCOSTSA-N 0.000 description 1
- 229940126543 compound 14 Drugs 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
本發明係有關一種半導體封裝結構及其製法，尤指一種可避免載體破裂之半導體封裝結構及其製法。 The present invention relates to a semiconductor package structure and a method of fabricating the same, and more particularly to a semiconductor package structure and a method for fabricating the same.
隨著半導體技術的演進，半導體產品已開發出不同封裝產品型態，而為追求半導體封裝件之輕薄短小，因而發展出一種晶片尺寸封裝件(chip scale package,CSP)，其特徵在於此種晶片尺寸封裝件僅具有與晶片尺寸相等或略大的尺寸。 With the evolution of semiconductor technology, semiconductor products have developed different package product types, and in pursuit of thinness and thinness of semiconductor packages, a chip scale package (CSP) has been developed, which is characterized by such a wafer. The size package only has dimensions that are equal or slightly larger than the size of the wafer.
第7,202,107號美國專利揭露一種CSP封裝結構及其製法。如第1A至1C圖所示，該製法首先提供一基板10；接者於該基板10上形成一熱感性黏著材12後，貼合複數半導體元件14於熱感性黏著材12上。 U.S. Patent No. 7,202,107 discloses a CSP package structure and method of making the same. As shown in FIGS. 1A to 1C, the method first provides a substrate 10; after forming a heat-sensitive adhesive 12 on the substrate 10, the plurality of semiconductor elements 14 are bonded to the heat-sensitive adhesive 12.
之後，如第1D圖所示，灌膠於半導體元件14未接置於熱感性黏著材12之一側，及其半導體元件14之側表面，使該封膠材料16完全包覆該半導體元件14。 Thereafter, as shown in FIG. 1D, the potting compound 14 is not attached to one side of the thermally sensitive adhesive 12, and the side surface of the semiconductor element 14 thereof, so that the encapsulant 16 completely covers the semiconductor element 14. .
如第1E圖所示，加熱該半導體元件14及封膠材料16，俾與該熱感性黏著材12分離。 As shown in FIG. 1E, the semiconductor element 14 and the sealant 16 are heated, and the crucible is separated from the heat-sensitive adhesive 12.
如第1F圖所示，於半導體元件14之主動面14a及同側之封 膠材料16表面形成金屬線路層18。最後，可進行切單作業(圖略)。 As shown in FIG. 1F, the active surface 14a of the semiconductor element 14 and the same side are sealed. A metal wiring layer 18 is formed on the surface of the adhesive material 16. Finally, a singulation operation can be performed (figure omitted).
惟，如第1D圖所示之製程，由於灌膠時，封膠材料16為液態，如以側面進行灌膠，則基板10中間區域會有填充厚度較邊緣厚度薄之情況，故於該半導體元件14及封膠材料16與該熱感性黏著材12分離後，封膠材料16容易發生翹曲，導致形成金屬線路層18時，產生線路不平整等問題，進而影響最終產品之產品可靠度。 However, as shown in FIG. 1D, since the sealing material 16 is in a liquid state during the filling, if the side is filled with glue, the intermediate portion of the substrate 10 may have a thinner thickness than the edge thickness, so the semiconductor is used. After the component 14 and the sealant material 16 are separated from the heat-sensitive adhesive material 12, the sealant material 16 is likely to warp, which causes problems such as unevenness of the wiring when the metal wiring layer 18 is formed, thereby affecting product reliability of the final product.
為解決前述問題，業界遂開發出如第2A至2C圖所示以模壓封裝材料於半導體元件上之技術，期可避免封裝封裝結構中間薄邊緣厚所致之翹曲問題。然而，在如第2A圖設置半導體元件24後，操作此製程之壓合步驟時，如第2B圖所示，因為外圍半導體元件24與基板20邊緣仍有一段距離，故靠近邊緣處之封膠材料26與半導體元件24設置區域之封膠材料26會產生約200um之垂直段差d，故而在壓合另一載體25時，造成如第2C圖圖右虛線所示，載體25之邊緣破裂，而導致載體25報廢，無法重複使用。 In order to solve the aforementioned problems, the industry has developed a technique of molding a packaging material on a semiconductor element as shown in FIGS. 2A to 2C, thereby avoiding the warpage caused by the thin edge of the package package structure. However, after the semiconductor element 24 is disposed as shown in FIG. 2A, when the pressing step of the process is performed, as shown in FIG. 2B, since the peripheral semiconductor element 24 is still at a distance from the edge of the substrate 20, the sealant near the edge is provided. The material 26 and the encapsulating material 26 in the region where the semiconductor element 24 is disposed will produce a vertical step d of about 200 um, so that when the other carrier 25 is pressed, the edge of the carrier 25 is broken as shown by the broken line on the right side of FIG. 2C. This causes the carrier 25 to be scrapped and cannot be reused.
因此，如何克服上述是種問題，實已成目前亟欲解決的課題。 Therefore, how to overcome the above problems is a problem that is currently being solved.
鑑於上述習知技術之種種缺失，本發明係揭露一種半導體封裝結構之製法，係包括：提供一表面上設有複數半導體元件之基板，且該基板表面之周圍復設有複數塊體；以及於該基板上壓合封裝膠體，以包覆該複數半導體元件及塊體。 In view of the above-mentioned various deficiencies of the prior art, the present invention discloses a method for fabricating a semiconductor package structure, comprising: providing a substrate having a plurality of semiconductor elements on a surface thereof, and a plurality of blocks are disposed around the surface of the substrate; The encapsulant is laminated on the substrate to coat the plurality of semiconductor components and the bulk.
前述之製法中，該基板表面具有半導體元件設置區，且該複數塊體係位於該基板邊緣與半導體元件設置區之間。 In the above manufacturing method, the substrate surface has a semiconductor element mounting region, and the plurality of block systems are located between the substrate edge and the semiconductor element setting region.
本發明半導體封裝結構之製法中，復可包括移除該基板，以 令該複數半導體元件及塊體外露出該封裝膠體。此外，復可於該外露出該複數半導體元件及塊體之封裝膠體表面形成線路重佈層。 In the method of fabricating the semiconductor package structure of the present invention, the method further comprises removing the substrate to The encapsulant colloid is exposed outside the plurality of semiconductor components and the block. In addition, a circuit redistribution layer is formed on the surface of the encapsulant on which the plurality of semiconductor elements and the bulk are exposed.
於另一具體實施例中，復包括於該線路重佈層表面上設置複數導電元件，以藉該線路重佈層電性連接該複數半導體元件。 In another embodiment, a plurality of conductive elements are disposed on the surface of the circuit redistribution layer to electrically connect the plurality of semiconductor elements by the circuit redistribution layer.
本發明復提供一種半導體封裝結構，係包括：具有相對之第一表面及第二表面之封裝膠體；嵌埋於該封裝膠體中，並外露出該第一表面之複數半導體元件；以及嵌埋於該封裝膠體周圍之封裝膠體中，並外露出該第一表面之複數塊體。 The present invention further provides a semiconductor package structure comprising: an encapsulant having a first surface and a second surface; a plurality of semiconductor elements embedded in the encapsulant and exposing the first surface; and embedded in The encapsulating colloid around the encapsulant and exposing the plurality of blocks of the first surface.
前述之半導體封裝結構中，復可包括線路重佈層，係形成於該封裝膠體之第一表面，以電性連接該複數半導體元件。此外，復可包括複數導電元件，係設於該線路重佈層表面上，以藉該線路重佈層電性連接該複數半導體元件。 In the foregoing semiconductor package structure, the circuit may include a circuit redistribution layer formed on the first surface of the encapsulant to electrically connect the plurality of semiconductor components. In addition, the complex includes a plurality of conductive elements disposed on the surface of the circuit redistribution layer to electrically connect the plurality of semiconductor elements by the circuit redistribution layer.
由上可知，本發明利用該些塊體之設置，減小壓合封裝膠體後，封裝膠體在基板中央與周圍處之段差，俾免載體破裂，以提升其使用壽命，並改善產品良率。 As can be seen from the above, the present invention utilizes the arrangement of the blocks to reduce the difference between the center of the substrate and the surrounding portion of the package after the pressure-bonding of the package, and to prevent the carrier from being broken, thereby improving the service life and improving the product yield.
3‧‧‧半導體封裝結構 3‧‧‧Semiconductor package structure
10,20,30‧‧‧基板 10,20,30‧‧‧substrate
12‧‧‧熱感性黏著材 12‧‧‧Thermal adhesive
14,24,34‧‧‧半導體元件 14,24,34‧‧‧Semiconductor components
14a,34a‧‧‧主動面 14a, 34a‧‧‧ active face
16,26‧‧‧封膠材料 16,26‧‧‧ Sealing materials
18‧‧‧金屬線路層 18‧‧‧Metal circuit layer
25,35‧‧‧載體 25,35‧‧‧ Carrier
31‧‧‧離型層 31‧‧‧ release layer
32,32’‧‧‧黏著層 32,32’‧‧‧Adhesive layer
341‧‧‧電極墊 341‧‧‧electrode pads
37‧‧‧塊體 37‧‧‧ Block
301‧‧‧半導體元件設置區 301‧‧‧Semiconductor component setting area
30a‧‧‧邊緣 30a‧‧‧ edge
36‧‧‧封裝膠體 36‧‧‧Package colloid
36a‧‧‧第一表面 36a‧‧‧ first surface
36b‧‧‧第二表面 36b‧‧‧second surface
38‧‧‧線路重佈層 38‧‧‧Line redistribution
39‧‧‧導電元件 39‧‧‧Conducting components
d‧‧‧段差 D‧‧‧ paragraph difference
第1A至1F圖係為習知CSP封裝結構及其製法的剖面示意圖；第2A至2C圖係為另一習知封裝結構及其製法的剖面示意圖；以及第3A至3G圖係為本發明之半導體封裝結構之製法剖面示意圖，其中，第3C’圖係第3C圖之俯視圖。 1A to 1F are schematic cross-sectional views of a conventional CSP package structure and a method of manufacturing the same; FIGS. 2A to 2C are schematic cross-sectional views of another conventional package structure and a method of manufacturing the same; and FIGS. 3A to 3G are diagrams of the present invention A schematic cross-sectional view of a semiconductor package structure, wherein the 3C' is a plan view of FIG. 3C.
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此 技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The embodiments of the present invention are described below by way of specific embodiments, and are familiar with this. Other advantages and effects of the present invention will be readily apparent to those skilled in the art from this disclosure.
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“第一”、“第二”“上”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。 It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "first", "second", "upper" and "one" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments to the relative relationship are considered to be within the scope of the invention without departing from the scope of the invention.
第3A至3G圖係為本發明之半導體封裝結構之製法示意圖。 3A to 3G are schematic views showing the manufacturing method of the semiconductor package structure of the present invention.
首先，提供一表面上設有複數半導體元件之基板，且該基板表面之周圍復設有複數塊體，其步驟可如第3A至3C圖所示。 First, a substrate having a plurality of semiconductor elements on its surface is provided, and a plurality of blocks are disposed around the surface of the substrate, and the steps may be as shown in FIGS. 3A to 3C.
如第3A圖所示，提供一基板30，該基板30可為透明材質，如玻璃，且其表面依序設有離型層31及黏著層32。 As shown in FIG. 3A, a substrate 30 is provided. The substrate 30 may be a transparent material such as glass, and the surface thereof is provided with a release layer 31 and an adhesive layer 32 in this order.
如第3B圖所示，於該黏著層32上設置複數如晶片之半導體元件34，其中，該半導體元件34之主動面34a係接觸設置於該黏著層32上，且該主動面34a具有複數電極墊341。 As shown in FIG. 3B, a plurality of semiconductor elements 34, such as a wafer, are disposed on the adhesive layer 32, wherein the active surface 34a of the semiconductor element 34 is in contact with the adhesive layer 32, and the active surface 34a has a plurality of electrodes. Pad 341.
如第3C圖所示，於設置該複數半導體元件34後，再設置該複數塊體37於該黏著層32上。此外，如第3C’圖所示，該基板30表面具有半導體元件設置區301，且該複數塊體37係位於該基板30邊緣30a與半導體元件設置區301之間。 As shown in FIG. 3C, after the plurality of semiconductor elements 34 are disposed, the plurality of blocks 37 are disposed on the adhesive layer 32. Further, as shown in Fig. 3C', the surface of the substrate 30 has a semiconductor element mounting region 301, and the plurality of blocks 37 are located between the edge 30a of the substrate 30 and the semiconductor element mounting region 301.
然而，可瞭解的是除了在設置該複數半導體元件34後，再設置該複數塊體37的方式，亦可改為先設置該複數塊體37，再設置該複數半導體元件34(圖略)。 However, it can be understood that, in addition to the manner in which the plurality of semiconductor elements 34 are disposed, the plurality of blocks 37 are disposed, and the plurality of blocks 37 may be disposed first, and the plurality of semiconductor elements 34 may be disposed (not shown).
另外，該複數塊體37係金屬、塑膠或含矽材，其中，該含矽材係玻璃或虛設晶片。 In addition, the plurality of blocks 37 are metal, plastic or coffin-containing, wherein the coffin-containing glass or dummy wafer.
於其他具體實施例中，該複數塊體之高度除了與該複數半導體元件高度相等之外，該複數塊體之高度係可高於或低於該複數半導體元件之高度。 In other embodiments, the height of the plurality of blocks may be higher or lower than the height of the plurality of semiconductor elements except that the height of the plurality of semiconductor elements is equal.
如第3D圖所示，於該基板30上壓合封裝膠體36，以包覆該複數半導體元件34及塊體37，接著，可透過加熱或照光使原先為半固化(B-stage)之封裝膠體36完全固化。由於該些塊體之設置，使得基板各處受壓的條件較為均衡，且該些塊體之間的間隙亦可經調整為與複數半導體元件的配置相仿，再者，該些間隙亦可做為封裝膠體之導流溝槽，使封裝膠體流動更為均勻，進而減小封裝膠體在基板中央與周圍處之段差。該形成之封裝膠體36具有相對之第一表面36a及第二表面36b。 As shown in FIG. 3D, the encapsulant 36 is press-bonded onto the substrate 30 to cover the plurality of semiconductor elements 34 and the bulk 37, and then the package may be originally B-staged by heating or illumination. The colloid 36 is fully cured. Due to the arrangement of the blocks, the conditions for pressing the substrate are relatively balanced, and the gap between the blocks can be adjusted to be similar to the configuration of the plurality of semiconductor components. Further, the gaps can also be made. In order to encapsulate the guiding groove of the colloid, the encapsulation colloid is more evenly flowed, thereby reducing the difference between the encapsulant and the periphery of the encapsulant. The formed encapsulant 36 has opposing first and second surfaces 36a, 36b.
如第3E圖所示，於該封裝膠體36上藉由黏著層32’結合載體35。該載體35可為透明材質，如玻璃板。 As shown in Fig. 3E, the carrier 35 is bonded to the encapsulant 36 by an adhesive layer 32'. The carrier 35 can be a transparent material such as a glass plate.
之後，如第3F圖所示，移除該基板30，以令該複數半導體元件34及塊體37外露出該封裝膠體36之第一表面36a。 Thereafter, as shown in FIG. 3F, the substrate 30 is removed to expose the plurality of semiconductor elements 34 and the bulk 37 to the first surface 36a of the encapsulant 36.
此外，如第3G圖所示，於該外露出該複數半導體元件34及塊體37之封裝膠體36表面形成線路重佈層38，並於該線路重佈層38表面上設置複數導電元件39，以藉該線路重佈層38電性連接該複數半導體元件34。 In addition, as shown in FIG. 3G, a circuit redistribution layer 38 is formed on the surface of the encapsulant 36 on which the plurality of semiconductor elements 34 and the bulk 37 are exposed, and a plurality of conductive elements 39 are disposed on the surface of the circuit redistribution layer 38. The plurality of semiconductor elements 34 are electrically connected by the line redistribution layer 38.
最後，可視需要進行切單製程，以獲得晶片尺寸級封裝件。 Finally, a singulation process can be performed as needed to obtain a wafer size package.
根據本發明之製法，本發明復提供一種半導體封裝結構3，係包括：封裝膠體36、複數半導體元件34以及複數塊體37。 According to the method of the present invention, the present invention provides a semiconductor package structure 3 comprising: an encapsulant 36, a plurality of semiconductor elements 34, and a plurality of blocks 37.
該封裝膠體36係具有相對之第一表面36a及第二表面36b，而該複數半導體元件34係嵌埋於該封裝膠體36中，並外露出該第一表面36a。 The encapsulant 36 has a first surface 36a and a second surface 36b opposite to each other, and the plurality of semiconductor elements 34 are embedded in the encapsulant 36 and expose the first surface 36a.
該複數塊體37係嵌埋於該封裝膠體36周圍之封裝膠體36中，並外露出該第一表面36a，再者，該複數塊體37係與該複數半導體元件34及封裝膠體36之第一表面36a齊平。具體實施上，該複數塊體37係金屬、塑膠或含矽材，其中，該含矽材可為玻璃或虛設晶片，且該複數塊體37之高度係高於、低於該複數半導體元件34之高度或與該複數半導體元件34高度相等。 The plurality of blocks 37 are embedded in the encapsulant 36 around the encapsulant 36, and the first surface 36a is exposed. Further, the plurality of blocks 37 are combined with the plurality of semiconductor elements 34 and the encapsulant 36. A surface 36a is flush. In a specific implementation, the plurality of blocks 37 are metal, plastic or containing materials, wherein the containing material may be a glass or a dummy wafer, and the height of the plurality of blocks 37 is higher than or lower than the plurality of semiconductor elements 34. The height is either equal to the height of the plurality of semiconductor elements 34.
另一方面，該半導體封裝結構3復可包括線路重佈層38，係形成於該封裝膠體36之第一表面36a，以電性連接該複數半導體元件34，且復可包括複數導電元件39，係設於該線路重佈層38表面上，以藉該線路重佈層38電性連接該複數半導體元件34之電極墊341。 On the other hand, the semiconductor package structure 3 may include a circuit redistribution layer 38 formed on the first surface 36a of the encapsulant 36 to electrically connect the plurality of semiconductor elements 34, and may include a plurality of conductive elements 39. It is disposed on the surface of the circuit redistribution layer 38 to electrically connect the electrode pads 341 of the plurality of semiconductor elements 34 by the circuit redistribution layer 38.
該半導體封裝結構3復可包括黏著層32’及載體35，係藉由該黏著層32’結合至該封裝膠體36之第二表面36b上。 The semiconductor package structure 3 further includes an adhesive layer 32' and a carrier 35 bonded to the second surface 36b of the encapsulant 36 by the adhesive layer 32'.
由上可知，本發明利用該些塊體之設置，減小壓合封裝膠體後，封裝膠體在基板中央與周圍處之段差，俾免載體破裂，以提升其使用壽命，並改善產品良率。 As can be seen from the above, the present invention utilizes the arrangement of the blocks to reduce the difference between the center of the substrate and the surrounding portion of the package after the pressure-bonding of the package, and to prevent the carrier from being broken, thereby improving the service life and improving the product yield.
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明 之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Anyone familiar with the art may not violate the invention The above embodiments are modified in the spirit and scope. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
3‧‧‧半導體封裝結構 3‧‧‧Semiconductor package structure
32’‧‧‧黏著層 32'‧‧‧Adhesive layer
34‧‧‧半導體元件 34‧‧‧Semiconductor components
35‧‧‧載體 35‧‧‧ Carrier
36‧‧‧封裝膠體 36‧‧‧Package colloid
36a‧‧‧第一表面 36a‧‧‧ first surface
36b‧‧‧第二表面 36b‧‧‧second surface
37‧‧‧塊體 37‧‧‧ Block
38‧‧‧線路重佈層 38‧‧‧Line redistribution
39‧‧‧導電元件 39‧‧‧Conducting components
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| CN110299289A (en) * | 2019-05-14 | 2019-10-01 | 南通通富微电子有限公司 | A kind of fan-out-type wafer-level packaging method |
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| US11004803B2 (en) | 2018-07-02 | 2021-05-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy dies for reducing warpage in packages |
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