TWI594251B - Memory control method, controller and electronic device - Google Patents

Description

Memory control method, controller and electronic device

The present invention relates to error handling apparatus and methods for flash memory, and more particularly to error handling apparatus and methods for multi-dimensional flash memory.

Non-volatile memory such as flash memory has developed rapidly in recent years and has appeared in a wide variety of electronic devices. At present, it seems that the next step will continue to strengthen regardless of the development of capacity or technology. Once more and more data is placed in such non-volatile memory, it is increasingly important to provide effective and reliable error detection and error management in order to ensure the correctness and security of stored data.

According to an embodiment of the present invention, a memory control method for controlling a flash memory is provided. The flash memory includes a first memory element and a second memory element, the second memory element comprising a plurality of blocks, each of the blocks comprising a plurality of data pages. In this memory control method, first, an original material is written to the first memory element. And reading the original data from the first memory element to obtain an input data, the input data comprising a plurality of input data columns. In addition, the complex input data column is divided into a plurality of data sets. Each of the input data columns corresponding to each of the data sets is written to one of the data pages corresponding to the second memory element. And writing a check column corresponding to each of the data groups to the data page corresponding to the second memory element, wherein the number of the data columns corresponding to each of the data groups is smaller than each of the second memory elements The number of pages of this material that the block has.

According to another embodiment of the present invention, a memory controller is provided. For controlling a flash memory. The flash memory includes a first memory element and a second memory element, the second memory element includes a plurality of blocks, each block includes a plurality of data pages, and the memory controller includes a first memory element writer , the reader and the second memory component writer. The first memory element writer writes an original material to the first memory element. The reader reads the raw data from the first memory storage element and generates an input data comprising a plurality of input data columns.

The second memory element writer divides the plurality of input data columns into a plurality of data sets, and writes the input data columns corresponding to each of the data sets to the data pages corresponding to the second memory elements, and corresponding each a check column corresponding to the data set is written to the data page corresponding to the second memory element, wherein the number of the input data columns corresponding to each of the data sets is smaller than each of the second memory elements The number of this information page.

According to another embodiment of the present invention, an electronic device having a flash memory and a controller is provided. The flash memory includes a first memory element and a second memory element, the second memory element comprising a plurality of blocks, each block comprising a plurality of data pages.

A memory controller for controlling the flash memory. The memory controller has a first memory element writer, a reader, and a second memory element writer. The first memory element writer writes an input data to the first memory element. The reader reads the data to be input from the first memory storage element, the input data comprising a plurality of input data columns. The second memory element writer divides the plurality of input data columns into a plurality of data groups, and writes the input data columns corresponding to each data group to the data pages corresponding to the second memory element, and corresponding data a check column of the group is written to the data page corresponding to the second memory element, wherein the number of the input data columns corresponding to each of the data groups is smaller than the number of data pages of each block of the second memory device Head.

According to another embodiment of the present invention, a memory control method for controlling a flash memory is provided. The flash memory includes a memory component, the memory The component contains a plurality of blocks, each block containing a plurality of data pages. The memory control method includes the following steps.

Reading a data set setting, indicating the number of the plurality of data columns included in one data group, each data column being stored in a corresponding one of the data pages, and the number of the plural input data columns of the data group is small The number of multiple data pages owned by each block. According to the data set setting, the complex data column corresponding to one of the data groups and a check column are read from the memory element. In addition, the check column is used to perform error detection and correction on the read complex data column.

701‧‧‧Application Circuit

702‧‧‧Driver

703‧‧‧ Controller

704‧‧‧ buffer memory

705‧‧‧Flash memory

80‧‧‧Flash memory

804‧‧‧Memory interface circuit

SLC 806‧‧‧Single-layer storage unit flash memory body module

MLC A 807, MLC B 808‧‧‧Multilayer storage storage unit flash memory module

82‧‧‧ Controller

820‧‧‧First Memory Component Writer

824‧‧‧Reader

824‧‧‧Second memory component writer

Figure 1 illustrates a block of a memory element of a NAND structured flash memory.

Figure 2 is a schematic diagram of the storage capacity and operating voltage of a flash memory storage unit of a three-layer storage unit (TLC).

Fig. 3 illustrates a situation that may occur if an operating voltage VT_1 is applied to the storage unit.

Figure 4 illustrates the sequential read operation of the memory cell using seven different voltages during a single read operation.

Figure 5 illustrates the method used to find the CSB.

Figure 6 illustrates the method used to find the MSB.

Fig. 7 illustrates an example of an electronic device using a flash memory.

Figure 8 illustrates a flash memory architecture including a hierarchical memory component architecture.

Figure 9 illustrates the data storage format in the flash memory of the multi-layer storage unit.

Figure 10 illustrates the second method of pairing data and verifying data.

Figure 11 illustrates the third method of pairing data and checksums.

Figure 12 is a flow chart.

Figures 13 to 16 are schematic views.

Figure 17 illustrates a flow chart of an embodiment of a memory control method.

Figure 18 illustrates a schematic diagram of the logical allocation of a block of a flash memory module.

Figure 19 to Figure 20 are schematic diagrams of the debugging of the flash memory module.

Embodiments of the present invention include a memory control method implemented by software, hardware, or software plus hardware for controlling flash memory. In an embodiment of the memory control method, the controlled flash memory has one or more first type memory elements and one or more second type memory elements, and is also a flash memory module. For example, they are packaged together in a bare crystal manner, or are connected in a wafer manner through a connection line or other fabrication methods. The first type of memory element is relatively stable relative to the second type of memory element and has a low error rate. When the original data is to be written to the flash memory, the original data is first written into the first type of memory element. Then, at the appropriate time, the original data is again read from the first type of memory element as input data for writing to the second type of memory element.

The second type of memory element has a plurality of blocks, each block including a certain number of pages. The above input data is divided into a plurality of data groups, each of which has a certain number of input data columns. The data set has a number of input data columns that is smaller than the number of data pages that can be carried by each block of the second type of memory element. In other words, each block of the second type of memory element can store input data columns of multiple data sets.

As described above, since the stability of the second type of memory element may be poor, each data set to be stored in the second type of memory element may pass through a low density parity-check (LDPC), A known parity generation method such as Bose-Chaudhuri-Hocquenghem (BCH) calculates a parity row corresponding to each data group. In addition, each input data column itself can also contain a row parity code corresponding to the input data column.

The use of the above data set method in the entire block as a unit can reduce the risk of write interruption due to power failure during writing or other reasons.

In addition, the number of input data columns corresponding to each data group can be set and adjusted, and each data group can be set corresponding to one or more check columns. Such a design can be adjusted for the characteristics of the second memory element.

In addition, in different blocks, the data set can be set to contain a different number of input data columns. In fact, different data sets can have different numbers of input data columns in the same block.

For example, the first type of memory component can be a single level memory flash memory, that is, the potential stored in each storage unit represents one bit, and the second type of memory element can be multi-layered. Multiple Layer Cell Flash Memory, such as Triple Layer Cell Flash Memory, can store information representing multiple bits in a storage unit, for example, a storage unit can be stored. Three bits of information. Under such a configuration, as semiconductor processes continue to develop toward high density miniaturization, coupled with the need for cost reduction, the stability of each storage unit has become increasingly problematic.

Through the above design concept, the same set of memory control circuit design can be used for different stability flash memories. For example, when it is determined that a second type of memory element with lower stability is used under a certain design, the number of check columns used by each data group can be increased, and the number of input data columns corresponding to each data group can be reduced. Etc., or increase the proportion of the column check code in the total data.

Conversely, if the error rate of the second type of memory element is relatively small, it can be set to increase the number of input data columns included in each data group, or to reduce the ratio of the check column and the column check code to the total data.

In addition to the above settings, the dynamic detection mechanism can also be set in the control circuit. If the stability of the second type of memory element is found to be gradually degraded during the use of the product, the proportion of the input data column corresponding to each data set can be dynamically adjusted. Thereby, even if the electronic device is used for a long time, the stability of the data does not decrease rapidly.

It should be noted that although the first type of memory element and the second type of memory element exemplified herein are circuits in the flash memory, the introduction of the present description by the technical personnel in the field should be able to apply the same concept to A storage device other than flash memory.

Embodiments of the present invention also include a memory controller as described above, and an electronic device equipped with the memory controller and flash memory.

In addition, embodiments of the present invention also include a memory control method for reading data of a flash memory. It reads the data set settings to know how the data set is included in each block of the flash memory, such as how many input data columns and how many check columns are included in each data set.

After knowing the data set of the flash memory, the data column of the data group is sequentially read out by using each data group as a unit. After reading the data column, the column of the data column is used to perform an error detection operation on the data column. If you find that you can correct the error by using the checksum code, you will correct the error in the data column.

If it is found that the data cannot be corrected by the column check code, for example, the error that the column check code can bear is only two bits, and if the actual data has more than three errors, the error check is continued through the check column of the data group. Test and correction. On the other hand, if the error detection and correction cannot be performed through the column check code, it is recorded which of the data columns are uncorrectable.

Further, as described above, each data group has a plurality of data columns which, when arranged in order, constitute an array having columns and rows. For each line of data, there is a parity data for the corresponding check column. If an error detection and correction method such as LDPC or BCH is used to generate the check column, the check column can be calculated through the check column and the data column of the data group to obtain the symptom corresponding to each line (syndrome). In these methods, the symptoms can indicate that there may be errors in those data columns.

If the error data column indicated by the symptom coincides with the record of the data record that cannot be corrected and the error is recorded, the error indicated by the symptom is reliable. this When correcting the error content of the data column through the verification data of the verification column.

As the above methods are performed sequentially, errors can be further reduced. At this time, the calculation of the column check code can be performed again. Originally, it may be impossible to correct because one data column has more than three bit errors. Since these three bits have corrected one bit and the error is reduced to two bits, the column check code can already be used. correct the mistake.

As the column check code further reduces the error bit, the calculation of the above symptoms can be performed again. If necessary, you can perform multiple iterations, find out the errors step by step, and correct all errors as much as possible to ensure the correctness and stability of the data.

Such characteristics are extremely important for preserving user data. Although it is necessary to use a second memory unit with lower stability in order to reduce the cost, the above method can minimize the risk of loss of valuable data of the user.

The actual fabrication method of the embodiment of the present invention will be described in more detail below by way of illustration.

Please refer to FIG. 1, which illustrates a block of a memory element of a NAND structure flash memory. There are a certain number of pages in this block, namely P_0, P_1, P_2, and P_N. Each data page has M_0, M_1, M_2, and M_K memory cells. By setting the appropriate voltages VG_0, VG_1, VG_2, and VG_N for each data page, the potential of the floating gate stored in each storage unit can be read, and the data stored in each storage unit can be obtained.

For single-layer storage unit (SLC) flash memory, each storage unit stores only one bit of data, which is 0 or 1. At this time, in theory, as long as the appropriate set voltage VG_0, VG_1, VG_2, and VG_N for each data page, the amount of power stored in the storage unit can be detected, and the corresponding data value is obtained.

In contrast, if it is a multi-layer storage unit (MLC) flash memory, A single read operation requires the application of a plurality of different set voltages to determine exactly what amount of power stored in the storage unit is, and to convert the actual stored data content.

Figure 2 is a schematic diagram of the storage capacity and operating voltage of a flash memory storage unit of a three-layer storage unit (TLC). As can be seen in this diagram, a storage unit falls within the L0, L1, L2, ... L7 interval according to the stored power, and the stored bit data is 111, 011, 001, ... 110, respectively.

For such a storage unit, in theory, when the operating voltage of VT_1 is applied, the detecting circuit can determine whether the amount of electricity stored in the storage unit belongs to the side of L0, that is, the data 111, or L1, L2, L3, L4, L5. On the side of L6, L7, that is, the data is 111, 011, 001, 101, 100, 000 or 110.

By sequentially applying a plurality of different voltage combinations, it is theoretically possible to determine the data of all three bits, that is, the Most Significant Bit (MSB), the Central Significant Bit (CSB), and the LSB (Least Significant Bit). ) the content of the information.

However, as described above, as the semiconductor process continues to develop toward miniaturization and miniaturization, and the flash memory is used to reduce cost or use time, the related circuits and the stability of the memory storage unit are The problem is getting bigger and bigger.

Fig. 3 illustrates a possible situation, that is, if the operating voltage VT_1 is applied to the storage unit, there is a possibility that the read data is incorrect due to partial overlap or even displacement between the bit states. In such a case, it is necessary to solve the problem of inaccurate data judgment through various error verification methods or dynamically adjusting the operating voltage.

Figure 4 illustrates the reading operation of the storage unit using seven different voltages in sequence during a single read operation. The power of the floating gate in the storage unit is detected to determine the LSB value of the data stored in the storage unit. 0 or 1.

It can be clearly seen from Figure 4 that if the amount of electricity stored in the storage unit falls On the left side of the VLSB, L0, L1, L2, L3, the content representing the LSB is 0. Conversely, if it falls on the right side of the VLSB, L4, L5, L6, and L7, the content representing the LSB is 1.

Due to the overlap between states, different voltages VLSB, VLSB+D, VLSB-D, VLSB+2D, VLSB-2D, VLSB+3D, VLSB-3D can be applied sequentially. Thereby, if the power distribution of the storage unit falls just between, for example, VLSB+D and VLSB, certain information can be obtained from the detection result.

Each time a voltage is applied, one bit result can be obtained, so 7 voltages can get 7 bits. There are a total of eight possible combinations of these seven bits. The bit sequence corresponding to the 7 bits can be combined with the decoding circuit and method of the LDPC to calculate the check code and find the correct bit data, that is, to use the obtained soft information. (soft information) with LDPC and BCH and other methods for error checking.

Figure 5 illustrates the method used to find the CSB. Since CSB represents the second bit, it can be seen in Figure 5 that if the power of the storage unit falls to L2, L3, L4, and L5, the CSB stored in the storage unit is 0. On the other hand, if the power of the storage unit falls within the L0, L1, L6, and L7 intervals, the CSB stored on behalf of the storage unit is 1. Under such a configuration, it can be understood that it is necessary to use the two operating voltages of VCSB1 and VCSB2 to filter out which area the power of the storage unit falls.

Similar to the above description, VCSB1 and VCSB2 can also apply a plurality of step adjustment amounts, and sequentially perform reading operations with different voltages. The result of each reading produces a bit sequence, which can be used with LDPC and BCH to perform error checking.

Figure 6 illustrates the method used to find the MSB. Since the MSB represents the highest bit, it can be seen in Fig. 6 that if the power of the storage unit falls within the L0, L3, L4, and L7 intervals, the MSB bit stored in the storage unit is 1. relatively, If the power of the storage unit falls within the L1, L2, L5, and L6 intervals, the MSB bit stored in the storage unit is 0.

Similar to the above description, VMSB1, VMSB2, VMSB3, and VMSB4 can also apply a plurality of step adjustment amounts, and sequentially perform reading operations with different voltages in sequence. The result of each reading produces a bit sequence, which can be used with LDPC and BCH to perform error checking.

Fig. 7 illustrates an example of an electronic device using a flash memory. The electronic device includes an application circuit 701, a driver 702, a controller 703, a buffer memory 704, and a flash memory 705. Such electronic devices can be designed with various hardware and software, with additional sensors and input and output devices to form various electronic devices on the market, such as notebook computers, cameras, cameras, SSD hard disks, and mobile phones. , flash drives, multimedia players, TV sets, set-top boxes, and more.

According to different design requirements, the application circuit 701 can be composed of one or more custom collective circuit chips, or a general processor, a controller, a corresponding firmware and software, and a circuit board and related components to form a required energy. An application circuit 701 for a particular application is reached.

In this example, the application circuit 701 accesses the data stored in the flash memory 705 via the controller 703 through the execution of the instructions of the driver 702 when the flash memory 705 needs to be accessed. The flash memory 705 referred to herein may be the above-described flash memory architecture or other storage hardware. In an embodiment, the application circuit 701 and the driver 702 can be regarded as a host, but not limited thereto.

When it is necessary to write data to the flash memory 705, the controller 703 is responsible for coordinating communication with the flash memory 705, and transferring the data to the flash memory 705 in accordance with the architecture of the flash memory 705. Typically, controller 705 uses some buffer memory 704 for buffering or caching. These buffer memories The 704 can be packaged with the controller 703, made into the same module, or designed into two different modules. For example, some flash memory 705 needs to have a certain amount of data per access, such as a block or a data page. At this time, the data to be written into the flash memory 705 is ready to be placed. In the buffer memory 704. In addition, in order to avoid excessive use of the flash memory 705, a different algorithm can be used to design a cache mechanism to speed up the overall access speed of the data.

Application circuit 701 can be of many different types. For example, a mobile phone or a circuit board inside a camera, a photographic lens, a processor, and the like. The application circuit 701 can also be a processor in a digital television or a processor in a computer. The controller can be fabricated as a separate integrated circuit chip, or embedded in the processing circuit 701, or the relevant control flow can be written as a code, and executed by the general controller to generate a controller corresponding to the control function. Sometimes, the communication between the application circuit 701 and the controller 703 may also be written as a code to form a driver, and then the application circuit 701 executes the driver to complete the communication with the controller.

Which functions are performed by the controller 703 and which functions are executed by the driver 702, or even the application circuit 701 itself, can be adjusted differently depending on the system and design requirements. For example, the functions related to error management described below may be performed by the narrow controller 703, or some or all of the error management mechanisms may be performed by the driver 702 in conjunction with the application circuit 701. At this point, the completion of all aspects of these error management mechanisms constitutes the concept of a generalized controller.

Figure 8 illustrates a flash memory 80 architecture including a hierarchical memory component architecture. In this example, the flash memory 80 includes a memory interface circuit 804, a single-layer storage unit flash memory block module SLC 806, and two multi-layer storage storage unit flash memory modules MLC A 807 and MLC. B 808. In actual design, a larger number of multi-layer storage unit flash memory can be configured.

The controller 82 includes a first memory element writer 820, a reader 824, and a second memory element writer 824. Controller 82 is used to control flash memory 80. The controller 82 transmits the control command and the data signal to the memory interface circuit 804 of the flash memory 80. The memory interface circuit 804 of the flash memory 804 can simply execute the command of the controller 82 according to different design requirements. The following data access and error management processing can also be shared with the controller 82.

Single-layer storage unit flash memory and multi-layer storage unit flash memory have different advantages and disadvantages. In simple terms, the single-layer storage unit flash memory is simple in structure, faster in access speed and less error-prone data, but multi-layer storage unit flash memory can store more than two bits per storage unit. Yuan, so the unit cost will be much cheaper than the single-layer storage unit flash memory, but the circuit is more complicated.

In the architecture of Figure 8, the single-layer storage unit flash memory can be used as a buffer mechanism for the flash memory of the multi-layer storage unit. In other words, if the data is to be written to the flash memory 80, it can be specified to be written to the flash memory of the single-layer storage unit. For example, the user is taking a picture or recording, because there is time limit, the data is first written to the single-layer storage unit flash memory.

Then, the controller 82 writes the data of the single-layer storage unit flash memory to the corresponding multi-layer storage by using the neutral or the memory interface circuit 804 of the flash memory 80 to synchronize or pipeline. Unit flash memory.

In the example of Figure 8, the single-layer storage unit flash memory is only one, while the multi-layer storage unit flash memory is only two, but in the actual design, the single-layer storage unit flashes. The number of flash memory in memory and multi-layer storage unit can be adjusted according to actual needs. Moreover, the flash memory of single-layer storage unit may not only be used as a buffer cache, but also can be used as data according to requirements. Long-term storage use. The following error management mechanisms can also be based on the needs of the design, or the user Corresponding adjustments are made to the use of the flash memory 80. For example, when the data is almost full and you have to use the single-layer storage unit flash memory to store data, you can also dynamically turn on, turn off or adjust the following error adjustment mechanism.

In addition, the single-layer memory flash memory in Figure 8 can also be replaced by a multi-layer memory flash memory with better quality or faster access speed, and even volatile memory can be used. For example, random access memory is used instead. For example, if there is a backup power supply, even if the power is suddenly turned off or the main battery runs out, the backup power supply can maintain the ability of the random access memory to save data for a certain period of time. During this period, the controller or the memory interface circuit stores the data as soon as possible. Into non-volatile memory. Alternatively, the MLC of FIG. 8 may be changed to TLC (the same storage stores three or more bits of information), or the SLC of FIG. 8 may be changed to MLC at the same time. The following error management mechanisms are applicable to this type of change.

Figure 9 illustrates the data storage format in the flash memory of the multi-layer storage unit. As described above, the flash memory is usually grouped for reading, writing or deleting, and FIG. 9 shows the first data arrangement in the flash memory of the multi-layer memory unit of FIG. Example.

In the data arrangement configuration illustrated in Fig. 9, the entire array constitutes a block in which each column constitutes a data page, and each square in each column represents a bit for storing a bit. A tuple or a storage unit of a bit. The data page can be regarded as a logical data page or as a physical data page. Those skilled in the art can freely choose to use it under the teaching of the present invention. In general, standards for flash memory, such as JDEC, require that the size of the block be a fixed value, and the size of the data page is also a fixed value, which cannot be arbitrarily changed, so that products made by different manufacturers have certain The degree of compatibility to facilitate the research and development of the overall industry. However, the practices described below can be applied even when the block size is fixed and the data page size is fixed. Of course, the practice of the present invention can also be used in special blocks. The size and size of the data page.

In addition, as described above, in order to achieve error detection and the ability to correct errors, an error handling coding method currently known or under development may be used. For example, LDPC, BCH or Reed Soloman. Since such a calculation method performs operations on the data to be stored to generate parity data, the check code data can be generated by the corresponding calculation by the controller 82 of FIG. And stored in the memory unit of the MLC of FIG.

In the example in Figure 9, each data page, that is, the column check code for each column, is placed at the end of each of the last columns (labeled as a diagonal block of the column check code). Although only one block is used as an example here, how many memory cells should be reserved to place the check code, it is related to the high fault tolerance rate, and which algorithm is used, and can be adjusted accordingly. The skilled artisan will use the check code of the appropriate number of bits in conjunction with the teachings of the present invention.

In addition, in addition to the error detection or error correction coding for each column of data, it is also possible to perform error detection or error correction coding processing for each line of data. In the example of Figure 9, one or more check columns resulting from error correction coding for each row are stored at the bottom of the block (labeled as a diagonal block of the check column). In an embodiment, a check column may be placed on the last page of the block, but is not limited thereto. Similarly, how much space is reserved to place the checksum data (check column) is related to the selected error correction algorithm and the required fault tolerance, and can be adjusted accordingly.

In this example, the generation of the check column and the column check code, although the same algorithm can be used, does not necessarily use the same algorithm. For example, the check column corresponds to the state of the memory cells in the vertical direction, and the vertical direction memory cells may have a common signal line, and have different correlation characteristics with the horizontal memory cells. At this time, each of the different algorithms can be used to perform the error management processing more efficiently.

In addition, in Figure 9, you can see that there is an intersection between the checksum column and the checksum code. local. The information in this place can be used in another algorithm or an algorithm that produces a check column and a checksum code, or all of them use the same algorithm. In some algorithms, whether it is to calculate the column check code before calculating the check column or vice versa, the final check data will be the same.

In Figure 9, all the data pages in the same block are jointly calculated in the vertical direction (check column), but this is not a necessary limitation. Figure 10 and Figure 11 illustrate the difference. The configuration relationship between the data and the verification data, and these configurations can be applied to the method of this embodiment.

Figure 10 illustrates the second method of pairing data and verifying data. In the example in Fig. 10, each of the three columns (data pages) provides a corresponding column (data page) for storing the check column data (check column), which constitutes a data group as a whole. In other words, in such a configuration, the same block can have multiple data sets. Of course, the three columns of data configuration 1 column check column exemplified here can also be changed to, for example, 50 columns of data configuration 3 check columns or various other numbers.

Similarly, in the horizontal direction, the pairing relationship between data and column check code can also be dynamically adjusted. In the end, how many column check codes and column check codes should be placed, whether the column check code and the data are to be staggered, or whether the column check code is uniformly placed at the front or the end can be based on actual needs. Make adjustments.

Figure 11 illustrates the third method of pairing data and checksums. Figure 11 illustrates another possibility. In Figure 11, the ratio of data to calibration data does not need to be a fixed ratio, but can be dynamically adjusted according to demand. For example, after determining the matching flash memory, the controller can set the error management mode to be used through the driver or setting the scratchpad, the ratio between the data and the check code, and how to arrange the storage location. Wait.

In fact, the embodiment of the present invention can also dynamically adjust or select different algorithms after the product is shipped, after statistical actual error occurrence, and the setting is not The ratio between the same data and the check code and how to arrange the storage location. These possible variations are covered by the concepts of the present invention.

The flowchart of Fig. 12 and the diagrams of Fig. 13, Fig. 14, Fig. 15, and Fig. 16 illustrate the processing flow of the Fig. 8 data read from the SLC and written to the MLC.

In this processing example, the second memory element writer 824 of the controller groups the blocks of the MLC. In the example of Fig. 13, for the convenience of explanation, every three data columns (data pages) are combined with a check column (data page) to form a data group. Of course, in practical applications, the ratio of the data column to the check column will be relatively small. For example, in a block with 100 data pages, it can be divided into five groups, that is, each group of 19 data columns with a check. Column.

Then please use Figure 12 and Figure 13 to Figure 16 to understand the practices exposed in this example.

First, the controller first reads a data page from the SLC and puts it into the buffer (step 1202). Since the data page itself may be in error, once the controller finds an error (step 1204), it uses the data read by the SLC. The check code corrects the data (step 1206). The corrected data, or the correct data, is then transferred to the memory interface circuit of the flash memory, and the data of the data page is written to the data page location of the corresponding MLC (step 1208).

In addition, the checked data is also passed to the error correction code generating unit in the controller (step 1210) for generating the column check code (step 1211). To generate such information, in this example, the data column that has been inspected is cumulatively calculated with the previously calculated verification column data to update the contents of the verification column.

For example, the check column of Fig. 14 uses the check column calculated in Fig. 13 and the second column data read in Fig. 14, and is generated by, for example, LDPC, BCH, or the like. The check column of Fig. 15 is updated by using the check column updated in Fig. 14 and the third column data read in Fig. 15.

Wait until the data column of this group has been processed, that is, the check column of this data group has been completely obtained, and the check column is written into the corresponding position of the MLC (step 1212), please also Refer to Figure 16.

In this way, even if there is a power outage during the operation, such as the user pulling the plug or temporarily pulling the memory card out of the computer, or removing the battery of the mobile phone, the affected area will not be the entire area. Block data, and at most only the affected group of data needs to be rewritten to the MLC.

Next, please refer to Figs. 17 to 20 for explaining another embodiment of the present invention.

Figure 17 illustrates a flow chart of an embodiment of a memory control method. This control method is used to control a flash memory to read data in the flash memory.

The flash memory has a memory component, such as a multi-layer storage component flash memory (MLC), and the memory component has a plurality of blocks. Each block has a plurality of data pages, and the memory control method includes the following steps.

First, the data set setting is read to know the configuration relationship between the block of the memory element and the data column, for example, how many data columns and how many check columns are included in a data group, and those data pages in a block store data. Columns, those are the check columns. A data column of the data set is then read (step 170). The column check code of the data column is used to determine whether the data column data has an error (step 171). If an error is found to occur and the error can be corrected (step 172), the error is corrected (step 173).

If the error cannot be directly corrected by the check code, for example, the error that the check code can bear is 3 bits, and when more than 3 bits occur, the data column cannot be corrected for error status, for example, The address of the data column is recorded in an error correction table (step 174).

Next, continue to read the other data columns and check columns of the data group. Using the verification method corresponding to the check column, such as LDPC or BCH or other related verification methods The corresponding symptoms of each row in the data set are calculated (step 175). That is, when the data columns of the data group are arranged in an array, the data is combined with the relative position data.

Taking Figure 18 as an example, it illustrates a logical component of a memory component, such as a block of a flash memory module. In this block, there are two data sets 182 and 184. The first data set 182 consists of seven data columns 1821 and two check columns 1822. In addition to the check column, each data column in data column 1821 has its own column check code 1823. These data are arranged in a graphical array, the same column refers to the logical data unit formed by the horizontal data unit, and the same row refers to the logical data unit formed by the vertical data unit. For example, the representation 186 represents the block. The first line of information.

Due to the calibration methods such as LDPC and BCH, after calculating the symptoms according to the contents of the checklist and the data group, it can be pointed out which columns may be wrong and corresponding corrections. For example, according to the first row data 1823 of the first data group 182 and the check column portion 1824 of the first row data, an error correction operation (such as calculating symptoms, etc.) can be used to know whether the first line of data has an error, and Determining whether the error state is within a correctable range (step 176), for example, the check column portion 1824 of the first row of data can provide a 3-bit correction capability, and the first row of data 1823 has only a 2-bit error. The error status is correctable. If the error status can be corrected, a correction is made (step 178). Conversely, if the error status cannot be corrected, no correction will be made.

For example, the data set 192 in Fig. 19 has 7 data columns and two columns of check columns (hatched below). First, each data column is first verified with its own column check code, and if an error is found, it is corrected. If an error is found but cannot be corrected, it is recorded in table 194 (the data column corresponding to the hatched line). In this example, each column checksum can correct up to two errors, and each check column can correct an error. Table 194 indicates that the second column and the fourth column found an error, and this error cannot be directly corrected by its column check code (more than two errors).

Next, the check columns are used line by line to assist in the correction. First, the first row of data 1921 and the corresponding check column 1922 of the data set 192 are used to perform error checking on the first row of data 1921 and it is found that no error occurs in the row of data. Next, using the second row of data 1923 of the data set 192 and its corresponding check column 1924, the second row of data 1923 is error checked and it is found that the row of data has an error (marked at the asterisk), in this embodiment, Each check column corrects an error, so correct it immediately. And so on. Then, using the fourth row of data 1925 of the data set 192 and its corresponding check column 1926, the fourth row of data 1925 is error-checked and found that the row of data has two errors (marked at the asterisk), in this embodiment Each check column corrects two errors, so this error cannot be corrected.

By analogy, after error checking of the data set 192 by using the check column row by row, it is possible to correct an error pattern having an error in each data line. Thus, the error state of the data set can be represented by Figure 20, wherein the data unit indicating the asterisk indicates the data unit in which the error occurred. It can be found from Fig. 20 that in each data column of the data group 192, there are no more than two erroneous data units, so the corresponding column check code can be reused for the second column and the fourth column data. Error checking, you can get the correct second and fourth columns.

In summary, if the original error is too many to correct with the column check code, it may be corrected by using the check column after the error check, so that the error can be reduced and the column check code can be corrected. For example, in Figure 20 Depicted, the star symbol representing the error is reduced. Once corrected, fewer errors, and repeated use of the previous vertical symptoms can continue to reduce errors.

Through repeated iterations of the iteration, although not all errors can be corrected, there are indeed a higher percentage of errors that can be corrected by these methods.

In summary, the present invention displays both in terms of purpose, means, and efficacy. It is different from the characteristics of the prior art. You are kindly asked to review the examination and express the patent as soon as possible. It should be noted that the various embodiments described above are merely illustrative for ease of explanation, and the scope of the invention is intended to be limited by the scope of the claims.

701‧‧‧Application Circuit

702‧‧‧Driver

703‧‧‧ Controller

704‧‧‧ buffer memory

705‧‧‧Flash memory

Claims (22)

A memory control method for controlling a flash memory, the flash memory comprising a first memory element and a second memory element, the second memory element comprising a plurality of blocks, each of the blocks comprising a plurality of blocks a data page, the memory control method comprising: writing an original data to the first memory element; reading the original data from the first memory element to obtain an input data, the input data comprising a plurality of input data columns; The plurality of input data columns are divided into a plurality of data groups; each of the input data columns corresponding to each of the data groups is written to one of the data pages corresponding to the second memory element; and a check column corresponding to each of the data groups is Write to the data page corresponding to the second memory element, wherein the number of the data columns corresponding to each of the data groups is smaller than the number of the data pages of each of the second memory elements. The memory control method according to claim 1, wherein when the plurality of input data columns are divided into the plurality of data groups, the number of the input data columns corresponding to each of the data groups is referenced to the second The rate of error in the memory component is determined. The memory control method according to claim 2, wherein the higher the error occurrence rate of the second memory element, the smaller the number of the input data columns corresponding to each of the data groups. The memory control method according to claim 1, wherein at least two of the data sets correspond to the number of the input data columns, and the at least two of the data sets correspond to two of the second memory elements. A different block. The memory control method according to claim 1, wherein the number of the input data columns corresponding to at least two of the data groups is different, and the at least two data sets correspond to the same of the second memory element. The block. The memory control method of claim 1, further comprising providing a setting mechanism for setting the number of the input data columns corresponding to each of the data groups. The memory control method according to claim 1, further comprising dynamically adjusting the number of the input data columns included in each of the data groups according to an error occurrence rate during detecting the operation of the second memory element . The memory control method according to claim 1, further comprising updating the data belonging to the data by using the content accumulation calculation of the input data column each time before writing the input data column to the second memory element. The content of the check column corresponding to the group. The memory control method of claim 6, further comprising calculating a column check code corresponding to the input data column, and writing the column check code together with the input data column to the Second memory element. The memory control method according to claim 1, further comprising: when the original data is read from the first memory element, error correction is performed on the original data to obtain the input data columns. The memory control method according to claim 1, wherein the first memory element has a lower error rate than the second memory element. The memory control method according to claim 1, wherein the first memory element is a single-layer storage flash memory, and the second memory element is a multi-layer storage flash memory. A memory controller for controlling a flash memory, the flash memory comprising a first memory element and a second memory element, the second memory element comprising a plurality of blocks, each block comprising a plurality of data a memory controller comprising: a first memory element writer for writing an original data to the first memory element; a reader for reading the original data from the first memory element and generating a Entering data, the input data includes a plurality of input data columns; and a second memory component writer, dividing the plurality of input data columns into a plurality of data groups, and writing the input data columns corresponding to each of the data groups to the first And the data pages corresponding to the two memory elements, and the one verification column corresponding to each of the data groups is written to the data page corresponding to the second memory element, wherein the input data corresponding to each of the data groups The number of columns is less than the number of pages of material that each block of the second memory element has. The memory controller of claim 13 further comprising a setter for setting the number of the input data columns included in each of the data sets. The memory controller of claim 13, wherein the second memory element writer further comprises dynamically adjusting each of the data sets according to detecting an error occurrence rate of the second memory element during operation The number of input data columns included. The memory controller according to claim 13 of the patent application, further comprising a a column check code generator, each time before writing the input data column to the second memory element, the column check code generator cumulatively updates the input data column by using the content of the input data column The content of the check column corresponding to the data group. An electronic device comprising: a flash memory comprising a first memory element and a second memory element, the second memory element comprising a plurality of blocks, each block comprising a plurality of data pages; and a memory controller For controlling the flash memory, the memory controller includes: a first memory element writer for writing an input data to the first memory element; and a reader from the first memory element Reading the input data, the input data includes a plurality of input data columns; and a second memory component writer, dividing the plurality of input data columns into a plurality of data groups, and writing the input data columns corresponding to each data group to The data pages corresponding to the second memory element, and a check column corresponding to each data group is written to the data page corresponding to the second memory element, wherein the input data corresponding to each of the data groups The number of columns is less than the number of data pages each of the blocks of the second memory element has. The electronic device of claim 17, wherein the first memory component is a single-layer storage flash memory, and the second memory component is a multi-layer storage flash memory. A memory control method for controlling a flash memory, the flash memory comprising a memory component, the memory component comprising a plurality of blocks, each block comprising a plurality of data pages, the memory control method comprising: reading Take a data group setting that indicates the plural number included in a data group a number of data columns, each of which is stored in a corresponding one of the data pages, and the number of the plural data columns of the data group is less than the number of plural data pages owned by each of the blocks; Setting, reading the complex data column corresponding to the data group and a check column from the memory element; and performing error detection and correction on the read multiple data column by using the check column. The method for controlling a memory according to claim 19, further comprising: determining, for each of the data columns of the data set, a check code of the data column to determine whether an error occurs; and when using the column check When the code finds an error and the error can be corrected, the column is corrected with the column check code. The memory control method according to claim 20, further comprising: when the error is found by using the column check code and the error cannot be corrected, the data column that cannot be corrected by the check code is recorded; Each row of the group uses a check column to calculate a corresponding symptom; and if the corresponding symptom matches the column check code to find that the record of the data column that cannot correct the error is enough to indicate the location where the error occurred, the check column pair is utilized. The data set is corrected for errors. The memory control method according to claim 21, further comprising: after the error correction is performed by using the check column, recalculating the column check codes in the data group by using the error corrected data, Perform error detection and correction again.