TWI587141B - Storage device and data access method thereof - Google Patents

Description

Memory device and data reading method

The present invention relates to a memory device, and more particularly to a memory device for performing a read operation based on a read state in a state table.

In general, memory can be divided into volatile memory and non-volatile memory. Non-volatile memory retains its stored data without a power supply, while volatile memory retains its stored data only when there is a power supply. The memory is usually arranged in a memory device for storing data for the host. For example, a memory device typically has a processor and one or more memories. The memory system of the memory device is purely for storing data, and the processor of the memory device accesses the data in the memory for the host according to the command of the host.

The invention provides a memory device comprising a plurality of non-volatile memories, a volatile memory and a processor. Volatile memory has a command queue. The processor reads the non-volatile memory through the plurality of channels and generates a state table according to at least one command in the command queue. The status table records the complex tasks and a read status and a channel number for each task. The processor picks a plurality of specific tasks in the tasks as a first set of tasks and simultaneously executes all of the tasks in the first set of tasks. The channel numbers of all tasks in the first task set are different. When the read status of the first task in one of the first task sets is a first In the preset state, the processor reads one of the non-volatile memories to read a logical-to-entity conversion table associated with the logical address of the first task. When the read status of the first task is a second preset state, the processor reads one of the non-volatile memory to read the data associated with the logical address of the first task.

The invention further discloses a data reading method suitable for a memory device. The memory device includes a plurality of non-volatile memories and a processor. The processor reads non-volatile memory through a plurality of channels. The data reading method of the present invention comprises: generating a state table according to at least one command in a command queue, the state table recording a plurality of tasks, a read state of each task, and a channel number; selecting a plurality of tasks as one The first task set, and simultaneously execute all the tasks in the first task set, wherein the channel numbers of all the tasks in the first task set are different; when the read status of the first task in the first task set is Reading, in a first preset state, at least one of the non-volatile memories, for reading a logical-to-entity conversion table associated with the logical address of the first task; when the first task is When the read state is a second preset state, at least one of the non-volatile memories is read to read the data associated with the logical address of the first task.

In order to make the features and advantages of the present invention more comprehensible, the preferred embodiments are described below, and are described in detail with reference to the accompanying drawings.

100‧‧‧Access system

110‧‧‧Host device

120‧‧‧ memory device

130‧‧‧Processor

140‧‧‧ volatile memory

150‧‧‧Non-volatile memory unit

141~143‧‧‧ Block

160_1~160_4‧‧‧ channel

150_1~150_4‧‧‧Non-volatile memory

S511~S515‧‧‧Steps

Figure 1 is a schematic illustration of an access system of the present invention.

Figure 2 is a schematic diagram of the state table after initialization of the present invention.

Figure 3 is a schematic diagram of the updated state table of the present invention.

Figure 4 is a schematic diagram of another state table after updating of the present invention.

Fig. 5 is a flow chart showing a method of reading data according to the present invention.

Figure 1 is a schematic illustration of an access system of the present invention. As shown, the access system 100 includes a host device 110 and a memory device 120. When the host device 110 transmits a write command, the memory device 120 stores the data according to the write command. When the host device 110 issues a read command, the memory device 120 provides the data to the host device 110 in accordance with the read command. In this embodiment, the memory device 120 includes a processor 130, a volatile memory 140, and a non-volatile memory unit 150.

The processor 130 receives a plurality of commands from the host device 110 and sequentially stores the commands in a command queue of the volatile memory 140. For convenience of explanation, it is assumed that the block 141 of the volatile memory 140 serves as a command queue. In this embodiment, the processor 130 establishes a state table according to at least one command in the command queue. In one possible embodiment, the status table is stored in block 142 of volatile memory 140, but is not intended to limit the invention. In other embodiments, the status table may be stored in another memory, such as non-volatile memory unit 150 or other memory. The information recorded in this status table will be explained later.

In one possible embodiment, block 143 of volatile memory 140 stores a logical-to-physical address mapping table. The logical-to-entity conversion table includes complex logical addresses and complex physical addresses associated with the logical addresses. The processor 130 learns, according to the logical-to-physical conversion table, which non-volatile memory of the non-volatile memory unit 150 is actually stored in the logical block address (LBA) provided by the host device 110. In the body.

In some embodiments, the volatile memory 140 further stores a conversion address table for indicating that a specific logical-to-physical conversion table corresponding to the logical address provided by the host device 110 is stored in the non-volatile memory unit 150. Which non-volatile memory is in it. For example, when the processor 130 cannot find the physical address corresponding to the logical address provided by the host device 110 from a first logic to entity conversion table stored in the volatile memory 140, the processor 130 changes From a conversion address table stored in the volatile memory 140, it is found out which non-volatile memory unit 150 of the second logical-to-physical conversion table corresponding to the logical address provided by the host device 110 is stored. In the volatile memory, the second logical-to-physical conversion table is loaded into the volatile memory 140, and the second logic-to-physical conversion table stored in the volatile memory 140 is used to find the provided by the host device 110. The data corresponding to the logical address is stored in the non-volatile memory unit 150.

The volatile memory 140 can be a dynamic random access memory (DRAM) or a static random access memory (SDRAM), but is not intended to limit the present invention. In other embodiments, the volatile memory 140 can be other types of volatile memory. In a possible embodiment, the processor 130 and the volatile memory 140 can be integrated into a controller for accessing the non-volatile memory unit 150 according to commands provided by the host device 110.

The non-volatile memory unit 150 can be a NAND type flash memory. As shown, the non-volatile memory unit 150 includes non-volatile memory 150_1~150_4, but is not intended to limit the invention. In other embodiments, Non-volatile memory unit 150 includes other quantities of non-volatile memory. In this embodiment, the processor 130 accesses different non-volatile memories through different channels. For example, the processor 130 accesses the non-volatile memory 150_1 through the channel 160_1, the non-volatile memory 150_2 through the channel 160_2, the non-volatile memory 150_3 through the channel 160_3, and the non-volatile memory 150_4 through the channel 160_4. Volatile memory 150_4. In one possible embodiment, the non-volatile memory 150_1~150_4 stores data and a complex logic to entity conversion table. In this embodiment, the processor 130 reads and outputs the data stored in the non-volatile memory 150_1~150_4 to the host device 110, but does not output a logical-to-physical conversion table to the host device 110.

Figure 2 is a schematic view of the state table of the present invention. As shown, the status table records the complex tasks and a read status of each task and the channel number corresponding to the task. For convenience of explanation, the state table of FIG. 2 shows only eight tasks, but is not intended to limit the present invention. In other embodiments, the state table records other numbers of tasks.

In a possible embodiment, the processor 130 learns the tasks 1-8 according to at least one command in a command queue of the volatile memory 140, and establishes a state table according to the tasks 1-8. The processor 130 initializes the read status of tasks 1-8. In this embodiment, the processor 130 initializes the read status of each of the tasks 1-8 to a preset state a. Since the processor 130 does not know which channel to access which non-volatile memory, the channel numbers corresponding to tasks 1-8 are indicated by question marks.

Next, the processor 130 decodes the tasks 1-8 to obtain the logical addresses of the tasks 1-8, and according to the logical addresses of the tasks 1-8 and the volatile memory 140. The stored information updates the read status of task 1 to task 8 and the channel number. Figure 3 shows the updated status table. Taking task 1 as an example, it is assumed that the logical address of task 1 is not recorded in the logical-to-entity conversion table of the volatile memory 140. Therefore, the processor 130 updates the read status of task 1 from the preset state a to Preset state b. The preset state b indicates that the processor 130 first needs to find out in which non-volatile memory a logical-to-physical conversion table corresponding to the logical address of the task 1 is stored, and then learns the task according to the found logical-to-entity conversion table. The data corresponding to the logical address of 1 is stored in which non-volatile memory.

For example, during a read, the processor 130 learns that a specific logical-to-entity conversion table corresponding to the logical address of the task 1 is stored in the non-transition address table stored in the volatile memory 140. Volatile memory 150_1. Since the processor 130 accesses the non-volatile memory 150_1 through the channel 160_1, the processor 130 sets the channel number corresponding to the task 1 to zero.

Referring again to FIG. 3, it is assumed that the logical address of task 3 has been recorded in the logical-to-entity conversion table stored in the volatile memory 140. In this example, the processor 130 sets the read status of task 3 to the preset state c. Since the data of the logical position of task 3 is stored in the non-volatile memory 150_3, the processor 130 updates the channel number of task 3 to 2. In this embodiment, channel numbers 0~3 correspond to channels 160_1~160_4, respectively.

After updating the read status and the channel number of all tasks in FIG. 2, the processor 130 selects a plurality of tasks as a first task set from the updated status table (as shown in FIG. 3), and simultaneously Execute all tasks in the first task set. In this embodiment, the channel numbers of all the tasks in the first task set are different.

For example, the channel numbers of tasks 1-3 and 8 shown in FIG. 3 are all different, so the processor 130 may select tasks 1-3 and 8 in FIG. 3 as a first task set. In this example, the read status of at least one of tasks 1-3 and 8 is different from the other. In another possible embodiment, processor 130 picks tasks that have the same read status but different channel numbers. For example, the processor 130 selects tasks 1-2 and 7 as a first task set, or selects tasks 3 and 8 as a first task set. In other embodiments, the processor 130 selects tasks based on the channel number to cause the channels 160_1~160_4 to be in the busy recording state. In other words, during each read, the processor 130 reads the non-volatile memory 150_1~150_4 through the channels 160_1~160_4.

For convenience of explanation, the following assumes that the processor 130 selects the tasks 1-3 of FIG. 3 as a first task set. In this example, the processor 130 simultaneously reads the non-volatile memory 150_1~150_3 through the channels 160_1~160_3 according to the channel number of the task 1-3. Taking task 1 as an example, since the read state of task 1 is the preset state b, the processor 130 reads a first logical-to-entity conversion table stored by the non-volatile memory 150_1 through the channel 160_1. After the processor 130 obtains the first logical-to-entity conversion table, the processor 130 updates the read status of the task 1 to the preset state c. In one possible embodiment, processor 130 loads the first logical-to-physical conversion table into volatile memory 140. The processor 130 learns that the data corresponding to the logical address of the task 1 is stored in the non-volatile memory 150_3 according to the first logic to entity conversion table. Therefore, the channel number of task 1 of processor 130 is updated to 2, as shown in FIG. In a possible embodiment, if the data corresponding to the logical address of task 1 is also storing non-volatile memory 150_1, then processor 130 maintains the channel number of task 1 at zero.

For task 2, in FIG. 3, since the channel number of task 2 is 1, the processor 130 reads a second logical-to-entity conversion table stored in the non-volatile memory 150_2 through the channel 160_2, and the task 2 The read status is updated to the preset status c, as shown in Figure 4. For task 3, since the read state of task 3 in FIG. 3 is the preset state c, the processor 130 reads the data stored in the non-volatile memory 150_3 through the channel 160_3, and reads the state of the task 3. Updated to state d as shown in Figure 4. State d indicates that processor 130 has completed task 3.

In a possible embodiment, the processor 130 stores the read data and the logical-to-physical conversion table in the volatile memory 140, but the processor 130 only outputs the data to the host device 110, and does not logically The entity conversion table is output to the host device 110.

Figure 4 is a schematic diagram of the status table after updating tasks 1-3. As shown, the read status and channel number of status 1-3 have been modified. The processor 130 then selects a plurality of tasks having different channel numbers as a second task set from the state table of FIG. In a possible embodiment, processor 130 may pick tasks having the same read state. For example, the processor 130 may select task 1-2 in FIG. 4 as the second set task, or select tasks 4 and 7 as the second set task. In other embodiments, processor 130 may pick tasks 1-2 and 5 as second set tasks. In this example, the read status of a first task (eg, task 1) in the second set of tasks is different from the read status of a second task (eg, task 5) in the second set of tasks.

In some embodiments, all of the tasks in the second set of tasks have the same read status and are the same or different from the read status of all of the tasks in the first set of tasks. For example, reading of all tasks in the second set of tasks The fetch status is the preset state b, and the read status of all tasks in the first set task is the preset state b or c.

The processor 130 executes the second set task, and updates the read status and the channel number of all the tasks in the second set task, and then re-selects the plurality of tasks from the updated state map as a third task set until the first The read status of tasks 1~8 of Figure 4 is state d. In a possible embodiment, when the processor 130 reads the data associated with the logical addresses of the tasks 1-8, the processor 130 outputs the read data to the host device 110.

Fig. 5 is a data reading method of the present invention, which is applicable to a memory device. The memory device includes a volatile memory, a plurality of non-volatile memories, and a processor. In a possible embodiment, the processor reads the non-volatile memory through a plurality of channels.

First, the processor generates a state table based on at least one command in a command queue (step S511). In one possible embodiment, a memory block of volatile memory 140 in the memory device acts as the command queue. In addition, the status table may also be stored in volatile memory, non-volatile memory or other memory in the memory device. In this embodiment, the status table records a plurality of tasks and a read status of each task and a channel number. After the state table is established, the processor initializes the read status of all tasks in the state table. In a possible embodiment, the processor initializes the read status of all tasks in the status table to a specific state, such as a preset state a. Figure 2 shows a possible initialization result.

Then, the processor updates the read status and the channel number of each task in the status table according to the information stored in the volatile memory (step S512). Therefore, the read status of each task is related to the information stored in the volatile memory. In a possible embodiment, the processor determines whether the logical address of a first task in the status table is recorded in a logical-to-entity conversion table stored in the volatile memory.

When the logical address of the first task is not recorded in the logical-to-physical conversion table stored in the volatile memory, the processor sets the read status of the first task to a preset state b, and according to the volatile memory The stored conversion address table updates the channel number of the first task. However, when the logical address of the first task is recorded in the logical-to-physical conversion table stored by the volatile memory, the processor sets the read status of the first task to a preset state c. At this time, the processor updates the channel number of the first task according to the logical-to-entity conversion table stored in the volatile memory.

Next, the processor selects a plurality of tasks as a first task set from the updated state table, and simultaneously executes all tasks in the first task set (step S513). In this embodiment, the channel numbers of all the tasks in the first task set are different. In a possible embodiment, the read status of all tasks in the first task set is the preset state b or c. In other embodiments, the read status of one of the plurality of tasks in the first set of tasks is different from the other of the plurality of tasks in the first set of tasks.

Taking Figure 3 as an example, assume that the processor picks tasks 1-3 as the first set of tasks. For tasks 1 and 2, since the read states of tasks 1 and 2 are the preset state b, the processor reads at least one of the non-volatile memory for reading the logical addresses associated with tasks 1 and 2. At least one logical to entity conversion table. Next, the processor updates the read status of task 1-2 to the preset state c, and updates the channel numbers of tasks 1 and 2 according to the read at least one logical-to-entity conversion table.

Next, for task 3, since the read state of task 3 is the preset state c, the processor reads at least one of the non-volatile memory for reading the data associated with the logical address of task 3. After reading the data, the processor updates the read status of task 3 to state d, and FIG. 4 shows a schematic diagram of the status table after the first task set is executed.

After updating the read status of all tasks in the first task set, the processor determines whether all read states in the status table of FIG. 4 are state d. If so, it indicates that the processor has completed a read command in the command queue (step S515). Therefore, the processor outputs all the read data to a host device. If all the reading states in the state table of Fig. 4 are not the state d, the process returns to step S513, and the selection and simultaneous execution of the plurality of tasks in Fig. 4 are continued. At this time, the selected task constitutes a second task set.

The processor executes the second task set and updates the read status of each task in the second task set according to the execution result. After the processor executes all the tasks in the second task set, if there are still some tasks whose reading state is not the state d, the processor selects multiple tasks again as a third task set, and simultaneously executes the third Multiple tasks in the task set until the read status of tasks 1-8 in the status table of Figure 4 is state d.

The processor performs multiple tasks in different sets of tasks during different reads. In a possible embodiment, all channels are in a busy state during each read. When the read status of the tasks 1-8 in the correspondence table of FIG. 4 is the state d, the processor outputs the data of the logical address associated with the tasks 1-8 to the host device. In this example, the processor does not output a logical-to-physical conversion table to the host device.

In a possible embodiment, the reading states of all the tasks in the second task set are the same and are the same or different from the reading states of all the tasks in the first task set. In another possible implementation, the second task set has a first task and a second task, wherein the read status of the first task is different from the read status of the second task. In this example, the processor can simultaneously read the table (logical to physical conversion table) and read the data.

Unless otherwise defined, all terms (including technical and scientific terms) are used in the ordinary meaning Moreover, unless expressly stated, the definition of a vocabulary in a general dictionary should be interpreted as consistent with the meaning of an article in its related art, and should not be interpreted as an ideal state or an overly formal voice.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

S511~S515‧‧‧Steps

Claims (20)

A memory device comprising: a plurality of non-volatile memory; a volatile memory having a command queue; and a processor for reading the non-volatile memory through the plurality of channels and arranging according to the command At least one command generates a state table that records a plurality of tasks and a read state and a channel number of each task, wherein the processor selects a plurality of specific tasks in the tasks as a first task Collecting, performing all the tasks in the first task set at the same time, the channel numbers of all the tasks in the first task set are different; wherein when the read status of the first task in the first task set is one a predetermined state, the processor reading one of the non-volatile memories, for reading a logical-to-entity conversion table associated with the logical address of the first task; when the first task is When the read state is a second preset state, the processor reads one of the non-volatile memories to read the data associated with the logical address of the first task. The memory device of claim 1, wherein during a first reading, the processor executes the first task set, and the read status of each task in the first task set is a first a specific state; during a second reading, the processor again selects a plurality of specific tasks from the tasks to serve as a second task set, and simultaneously executes all tasks in the second task set, the first The channel numbers of all the tasks in the second task set are different, and the read status of each task in the second task set is a second specific state, and the second specific state is different from the first special state. Set the state. The memory device of claim 2, wherein when the first specific state is the first preset state, and the second specific state is the second preset state, the processor executes the After the first task is set, the processor updates the read status of each task in the first task set to the second preset state, and when the processor executes the second task set, the processor will The read status of each task in the second set of tasks is updated to a third state, the third status indicating that the processor has completed a particular task in the second set of tasks. The memory device of claim 2, wherein when the first specific state is the second preset state, and the second specific state is the first preset state, the processor executes the After the first task is set, the processor updates the read status of each task in the first task set to a third state, and when the processor executes the second task set, the processor uses the second The read status of each task in the task set is updated to the second preset state, the third status indicating that the processor has completed a particular task in the first task set. The memory device of claim 4, wherein during a third reading, the processor again selects a plurality of specific tasks from the tasks as a third task set and simultaneously executes the third task. All the tasks in the set, the channel numbers of all the tasks in the third task set are different, and the read status of each task in the third task set is the second preset state, when the processor executes After completing the third task set, the processor updates the read status of each task in the third task set to the third shape. State, and continue to select multiple tasks in the tasks until the read state of each of the tasks is the third state. The memory device of claim 1, wherein the processor simultaneously executes the first task and the second task in the first task set, the read status of the first task is different from the second task Read status. The memory device of claim 6, wherein when the processor performs the first task, the processor reads one of the first non-volatile memory stored in the non-volatile memory. a logic-to-physical conversion table, when the processor performs the second task, the processor reads a specific data stored in the second non-volatile memory of one of the non-volatile memories, and the memory device outputs the The specific data is given to a host device, but the logical-to-physical conversion table is not output to the host device. The memory device of claim 1, wherein the processor determines a read status of each task based on information stored in the volatile memory. The memory device of claim 8, wherein the volatile memory stores a specific logical-to-entity conversion table, the specific logical-to-entity conversion table including a plurality of logical addresses and a plurality of entities associated with the logical addresses a location, the processor determining whether a logical address associated with the first task is recorded in the specific logical-to-entity conversion table, when a logical address associated with the first task is not recorded in the specific logical-to-entity In the conversion table, the processor sets the read status of the first task to the first preset state, and when the logical address associated with the first task is recorded in the specific logical-to-entity conversion table, the processor Setting the read status of the first task to the second preset status. The memory device of claim 1, wherein the processor reads the non-volatile memory through all channels during a read. A data reading method is applicable to a memory device. The memory device includes a plurality of non-volatile memory and a processor. The processor reads the non-volatile memory through a plurality of channels. The data reading method includes: Generating a state table according to at least one command in a command queue, the state table records a plurality of tasks, a read state of each task, and a channel number; and selecting a plurality of tasks in the tasks as a first task set And simultaneously executing all the tasks in the first task set, wherein the channel numbers of all the tasks in the first task set are different; when the read status of the first task in the first task set is one At least one of the non-volatile memories for reading a logical-to-entity conversion table associated with the logical address of the first task; and reading the first task When the state is a second preset state, at least one of the non-volatile memories is read to read the data associated with the logical address of the first task. The data reading method of claim 11, wherein during the first reading, the first task set is executed, and the read status of each task of the first task set is a first specific a state; during a second reading, selecting a plurality of tasks in the tasks as a second task set, and simultaneously executing all tasks in the second task set, wherein all tasks in the second task set The channel number is not the same Similarly, the read status of all tasks in the second task set is a second specific state, and the second specific state is different from the first specific state. The data reading method of claim 12, wherein when the first specific state is the first preset state, and the second specific state is the second preset state, After a task is set, the read status of each task of the first task set is updated to the second preset state, and after the second task set is executed, each task in the second task set is The read status is updated to a third status indicating that the corresponding task has been completed. The data reading method of claim 12, wherein when the first specific state is the second preset state, and the second specific state is the first preset state, After a task is set, the read status of each task in the first task set is updated to a third state, and after the second task set is executed, the read status of each task of the second task set is performed. Updated to the second preset state, the third state indicating that the corresponding task has been completed. The data reading method of claim 14, wherein in a third reading period, a plurality of tasks in the tasks are selected as a third task set, and simultaneously executed in the third task set All the tasks, the channel numbers of all the tasks in the third task set are different, and the reading status of each task in the third task set is the second preset state, and the third task is executed. After the collection, the read status of each task in the third task set is updated to the third state, and other tasks are continued until the read status of all tasks is the third state. The data reading method of claim 11, wherein the first task set includes at least the first task and a second task, and the read status of the first second task is different. The data reading method of claim 16, wherein when performing the first task, reading a logical to physical conversion stored by the first non-volatile memory of one of the non-volatile memories a table, when performing the second task, reading a specific data stored by the second non-volatile memory of one of the non-volatile memories, wherein the specific data is output to a host device, but the logic is The entity conversion table is not output to the host device. The method of reading data according to claim 11, wherein the reading status of each task is related to information stored in a volatile memory of the memory device. The method for reading data according to claim 18, further comprising: reading the volatile memory, wherein the volatile memory stores a specific logical-to-entity conversion table, the specific logical-to-entity conversion table including a plurality a logical address and a complex physical address associated with the logical address; determining whether a logical address associated with the first task is recorded in the specific logical-to-entity conversion table, when associated with a logical bit of the first task The address is not recorded in the specific logical-to-entity conversion table, and the read status of the first task is set to the first preset state, and the logical address associated with the first task is recorded in the specific logical-to-entity In the conversion table, the read state of the first task is set to the second preset state. The data reading method of claim 11, wherein each of the channels is in a busy state during a reading period.