TWI571064B - Time domain switched analog-to-digital converter apparatus and methods - Google Patents

Description

Analog to digital converter device and method for time domain switching [Priority and related applications]

The present application claims priority to U.S. Provisional Patent Application Serial No. 61/525,596, the entire disclosure of which is incorporated herein by reference.

The present application is also related to U.S. Patent Application Serial No. 13/168,603, filed on Jan.

The present invention relates generally to oscillating methods and apparatus for signal conversion applications, and more particularly to an exemplary aspect of a time domain switching analog to digital converter device, and methods of implementing and utilizing the same.

Analog to digital converters (ADCs), a device that converts continuous quantities into discrete time digital representations, are commonly used for signal measurement and other applications. In general, an ADC is an electronic device that converts an input analog signal (eg, voltage or current) into a digital value that is proportional to the amount of input signal.

The performance of an analog-to-digital converter is generally based on the sampling rate (usually chosen to be twice the maximum frequency wanted to be detected according to Nyquist's theorem); resolution (bit): used to represent the analog input signal value The number of bits in the digitized bit stream; and the least significant bit (LSB): the lowest weight bit in the digitized bit stream is depicted. The analog signal value (eg, voltage or current) corresponding to the ADC LSB is also referred to as signal resolution, or ADC electrical resolution. LSB represents the minimum change in the input voltage required to change the output code level of the ADC. With regard to state-of-the-art ADC technology, the resolution of modern ADCs typically ranges from 8 bits to 24 bits.

The existing ADC techniques are summarized in Table 1 and include: delta-sigma converters; delta modulation converters; step-by-step approximation (SAR) converters, direct conversion or flash ADCs, Wilkinson ADCs, integral ADCs (eg dual slope, Four slopes); and pipelined ADCs. Table 1 presents a selection of performance summaries and value metrics for some typical ADC technologies.

Various sources of error affect the performance of existing commercially available ADCs depending on the primary source of error in the technology used by the converter. In general, all types of ADCs have nonlinear quantization errors and clock jitter that affect the choice of ADC technology for a particular application. These sources of noise generally reduce the number of effective bits (ENOB) defined for the original sinusoidal input waveform: ENOB=(SINAD-1.76)/6.02, (Equation 1) where the signal is noise and distortion Ratio (SINAD) (generally in dB table Shown is the ratio of the root mean square (RMS) value of the sine wave ADC input to the RMS value of the converter noise plus distortion (no sine wave). In addition to the basic and DC offsets, RMS noise plus distortion includes all spectral components close to the Nyquist frequency.

Thus, a 24-bit ADC can, for example, only have meaningful data included in 21 or 22 bits (ie, ENOB=21) before each sample.

Most existing ADC implementations have several drawbacks, such as fixed dynamic range and resolution. In particular, the prior art is not well suited for measuring signals having a wide dynamic range and a non-uniform signal amplitude distribution (i.e., when high amplitude or low amplitude signals are not as common as average signals). When measuring such signals, the user must usually compromise the high-amplitude signal portion (limiter) or the low-amplitude signal portion (resolution), or separate the portions of the ADC with a range of signal amplitudes to implement a dedicated multi-channel. The solution. Such implementations add cost and complexity and thus limit their wider use. In addition, the accuracy of existing commercially available low cost ADCs is generally not too high, and higher accuracy ADCs are typically quite expensive, thus limiting their wide applicability.

Therefore, there is a clear need for an improved high accuracy and high resolution analog to digital converter device that has an increased dynamic range compared to existing solutions while reducing cost and complexity and can be used in a variety of ways. A variety of sensing and measurement applications.

The invention is particularly disclosed based on time domain clamping by a cyclic carrier waveform Analog to digital converter devices and methods.

In a first aspect of the invention, an analog to digital converter device is disclosed. The analog to digital converter device in an embodiment comprises: (i) a first interface configured to receive an input signal and a carrier signal, and (ii) processing logic. The processing logic is configured to: (i) identify one or more reference levels, (ii) generate a modulated signal based on the input signal and the carrier signal, and (iii) detect one or more reference levels by the modulated signal Intersection of bits, (iv) determining a plurality of timing periods based on the detected intersections, and (v) generating one or more estimates of the input signal based at least in part on the timing period.

In a second aspect of the invention, a method of converting an analog waveform into a digital signal is disclosed. In one embodiment, the method comprises: (i) receiving an analog waveform, (ii) mixing a analog waveform with a cyclic signal to generate a hybrid waveform, (iii) defining a period based on the cyclic signal, and (iv) intersecting based on the mixed waveform At least a predetermined amplitude level to determine one or more timing values, and (v) estimating an amplitude of the analog waveform based at least in part on a comparison of the one or more timing values to the defined period.

In a third aspect of the invention, a non-transitory computer readable device is disclosed that is configured to store one or more programs thereon. In one embodiment, the one or more programs include a plurality of instructions that, when executed, are configured to: (i) receive a modulated waveform derived from an input signal and a carrier, the carrier having a known frequency, (ii) determining the relative timing of the plurality of events, the plurality of events including the intersection of the modulated waveform and a reference level, (iii) comparing the relative timing with a period derived from the known frequency, and (iv) Calculate an estimate of the input signal based at least on the comparison.

In a fourth aspect of the invention, an analog to digital converter device for time domain switching is disclosed. In an embodiment, the analog to digital converter device comprises: (i) a first frame configured to receive a periodic carrier signal having a characteristic of a carrier period, (ii) an input port configured to receive an input analogy Signal, and (iii) logic blocks. The logic block is configured to: (i) generate a modulated signal based on the carrier signal and the input signal, (ii) compare the modulated signal to a first reference signal, and (iii) based at least in part on the comparison, to generate a first plurality of a triggering event, the first plurality of trigger events being associated with the first reference signal, (iv) being based at least in part on the first plurality of trigger events and a reference clock, determining a first time interval, and (v) being based at least in part on the A time interval and carrier period produce a digital representation of the input signal.

In a fifth aspect of the invention, a method of compensating for distortion produced during a analog to digital conversion process is disclosed. In one embodiment, a time varying input waveform is sampled and held at a fixed value for a duration. Compensate for harmonic contributions caused by time variations.

In another embodiment, an input signal is mixed with a carrier to produce a modulated input signal. The modulated input signal triggers a plurality of sampling events. The sampling event is used to generate a suitable curve representing the modulated input signal. The distortion term is quantified using this representation and then removed.

In yet another embodiment, different techniques are utilized to remove contributions from noise.

In a sixth aspect of the invention, a class based on waveform rectification is disclosed Compared to digital converters. In an embodiment, the converter includes processing logic configured to reflect a negative portion of a signal onto the positive axis. This reflection increases the number of reference levels that intersect certain waveforms.

Other features, aspects, and advantages of the invention will be apparent from the drawings and appended claims.

101‧‧‧ front-end processing

103‧‧‧Timing discrimination

109‧‧‧Control logic

111‧‧‧Time to digital conversion

113‧‧‧ algorithm components

115‧‧‧ signal

110‧‧‧Trigger event

112‧‧‧Trigger events

T ₁ ‧‧ ‧ time interval

T ₂ ‧‧ ‧ time interval

V ₁ ‧‧‧ voltage

V ₂ ‧‧‧ voltage

121‧‧‧ Equipment

123‧‧‧ADC block

210‧‧‧Trigger event

212‧‧‧Trigger event

T _r1 ‧‧ ‧ time interval

T _r2 ‧‧ ‧ time interval

131‧‧‧ Curve

133‧‧‧ Curve

139‧‧‧Offset

141‧‧‧ arrow

143‧‧‧ arrow

T ₃ ‧‧ ‧ time interval

T ₄ ‧‧ ‧ time interval

230‧‧‧ Triggering event

232‧‧‧Trigger event

234‧‧‧Trigger event

P‧‧ cycle

T ₅ -T ₁₀ ‧‧ cycle

161‧‧‧ADC equipment

163‧‧‧Combination block

171‧‧‧ Equipment

173‧‧‧ADC block

175‧‧‧ADC block

181‧‧‧ADC equipment

191‧‧‧ADC equipment

193‧‧‧Upper board

195‧‧‧ Lower board

222‧‧‧Signal reference level

224‧‧‧Rectified signal wave

226‧‧‧Rectified signal wave

T ₁₁ ‧‧‧ Timing parameters

T ₁₂ ‧‧‧ Timing parameters

t ₁ ‧‧‧ Timing parameters

t ₂ ‧‧‧ Timing parameters

t ₃ ‧‧‧ Timing parameters

t ₄ ‧‧‧ Timing parameters

t ₅ ‧‧‧ Timing parameters

t ₆ ‧‧‧ Timing parameters

P‧‧ cycle

234‧‧‧Sampling and keeping orders

332‧‧‧ input signal

334‧‧‧Harmonic

350‧‧‧ system

352‧‧‧ analog signal

354‧‧‧Sampling and holding device

356‧‧‧Rectifier/Comparator Block

358‧‧‧Time to digital converter

360‧‧‧TDS ADC algorithm components

370‧‧‧S/H circuit

372‧‧‧Switch

374‧‧‧Switch

376‧‧‧Differential Amplifier

378‧‧‧ Holding capacitors

380‧‧‧ input signal

382‧‧‧Measurement amplifier

386‧‧‧S/H control unit

412‧‧‧Carrier signal input

414‧‧‧Harmonic

602‧‧‧ADC block

604‧‧‧ADC block

610‧‧‧ADC equipment

680‧‧‧ADC equipment

682‧‧‧ADC block

684‧‧‧ADC block

722‧‧‧Signal input

724‧‧‧ even harmonics

726‧‧‧odd harmonics

782‧‧‧ Path

784‧‧‧ Path

786‧‧‧Voltage Adder

788‧‧‧Voltage subtractor

790‧‧‧TDS ADC

902‧‧‧ trigger point

904‧‧‧All modulation signals

906‧‧‧ Carrier

908‧‧‧External signal input

1050‧‧‧Fixed reference level circuit

1302‧‧‧Sawtooth waveform

1304‧‧‧Triangular waveform

1306‧‧‧ waveform

1308‧‧‧ waveform

1402-1420‧‧‧ arrow

The features, objects, and advantages of the present invention will become more apparent from the detailed description of the appended claims. Functional block diagram.

1A is a diagram showing one embodiment of a method of measuring an input modulated signal using a single reference level time domain switching (TDS) analog to digital converter (ADC) in accordance with the present invention.

1B is a block diagram depicting a configuration of a single reference level time domain switching ADC in accordance with an embodiment of the present invention.

1C is a plot showing one embodiment of a method of measuring an input modulated signal using two reference level TDS ADCs in accordance with the present invention.

1D is a function showing the variation of the time interval between the intersections of successive reference levels of an input signal larger than the data shown in FIG. 1 according to an embodiment of the two reference level TDS ADCs of the present invention. Drawing.

Figure 1E is a block diagram showing a second embodiment of the two reference level TDS ADCs of the present invention.

Fig. 1F is a circuit diagram detailing the TDS ADC of Fig. 1E.

The 1G diagram is a block diagram depicting a time-to-digital converter according to the prior art for use with the exemplary ADC implementations of Figures 1E and 1F.

Figure 1H is a block diagram of an implementation of a single channel two reference level TDS ADC embodiment detailing Figure 1E.

Fig. 1I is a timing chart showing an exemplary operational sequence of the time domain switching ADC device of the embodiment shown in Fig. 1E.

The 1J diagram is a diagram showing an example of the effect of modulation on the waveform of a carrier signal waveform in accordance with an embodiment of the present invention.

1K is a plot showing an embodiment of a method of measuring an input modulated signal using a three reference level TDS ADC in accordance with the present invention.

The 1L diagram is a plot showing various embodiments of a method of measuring an input modulated signal using a two reference level TDS ADC in accordance with the present invention.

1M is a block diagram depicting a configuration of a two-channel two-reference level time domain switching ADC including independent carrier measurements in accordance with an embodiment of the present invention.

The 1Nth diagram is a block diagram depicting the configuration of a three reference level time domain switching ADC in accordance with an embodiment of the present invention.

Figure 10 is a block diagram depicting another embodiment of a three reference level time domain switching ADC of the present invention.

1P is a block diagram depicting one embodiment of a reverse carrier three reference level time domain switching ADC of the present invention.

The 1Q diagram is a block diagram depicting another embodiment of a three reference level time domain switching ADC of the present invention.

The 1R diagram is a plot depicting one embodiment of modulated signal waveform measurements consistent with the ADC embodiments of the 1Q and 1R diagrams in accordance with the present invention.

2 is a plot showing one embodiment of a method of measuring an input modulated signal using a single reference level waveform rectified TDS ADC in accordance with the present invention.

Fig. 2A is a detail area showing an embodiment of the method shown in Fig. 2.

Figure 3 is a plot showing one embodiment of a time varying modulated signal waveform measurement in accordance with the present invention.

Figure 3A is a logic flow diagram showing one embodiment of a generalized method of applying a sample and hold technique to a TDS ADC consistent with the present invention.

Figure 3B is a plot showing the simulation results of an exemplary TDS ADC measurement method that does not utilize sampling and hold in accordance with the present invention.

Figure 3C is a plot showing the simulation results of an exemplary TDS ADC measurement method utilizing sampling and holding in accordance with the present invention.

Figure 3D is a block diagram depicting the configuration of a sample and hold waveform rectified TDS ADC consistent with one embodiment of the present invention.

Figure 3E is a functional block diagram showing an exemplary sample and hold circuit consistent with the present invention.

Figure 3F is a circuit diagram of an embodiment of a TDS ADC in accordance with Figure 3D of the present invention.

Figure 3G is a plot showing the simulation results of a TDS ADC measurement method using a time varying input signal for sampling and holding in accordance with the present invention. Figure.

Figure 4 is a logic flow diagram showing one embodiment of a generalized method of applying a polynomial correction to a TDS ADC measurement in accordance with the present invention.

Figure 4A is a plot showing simulation results illustrating the effect of an exemplary TDS ADC measurement method utilizing polynomial correction with a signal carrier input in accordance with the present invention.

4B and 4C are plots showing simulation results illustrating the effects of an exemplary TDS ADC measurement method utilizing polynomial correction with multiple carrier inputs in accordance with the present invention.

Figure 5 is a plot showing the simulation results of an exemplary TDS ADC measurement method utilizing carrier waveform filtering in accordance with the present invention.

Figure 6 is a plot showing the simulation results of an exemplary TDS ADC measurement method utilizing differential signal noise compensation in accordance with the present invention.

6A is a block diagram depicting a configuration of a two-channel single reference level time domain switching ADC including independent carrier measurements in accordance with an embodiment of the present invention.

6B is a block diagram depicting the configuration of a single channel two reference level time domain switching ADC in accordance with an embodiment of the present invention.

6C is a block diagram depicting a configuration of a three-reference level time domain switching ADC including independent carrier measurements in accordance with an embodiment of the present invention.

Figure 7 is a logic flow diagram showing one embodiment of a generalized method of utilizing differential modulation signal measurements in a TDS ADC consistent with the present invention.

Figure 7A is a plot showing the simulation results of an exemplary TDS ADC measurement method utilizing differential ADC skew compensation in accordance with the present invention.

Figure 7B is a functional block diagram showing a differential measurement TDS ADC in accordance with an embodiment of the present invention.

Figure 7C is a functional block diagram showing various exemplary signal and carrier combinations for differential signal measurements consistent with the present invention.

Figure 7D is a plot detailing the effects of various distortion components on various exemplary embodiments of the present invention.

Figure 8 is a plot showing the effect of noise levels on various exemplary TDS ADC averaging techniques based on generating a plurality of uncorrelated measurements of timing intervals consistent with the present invention.

Figure 8A is a plot showing an exemplary averaging method based on the sampling period of a doubled TDS ADC consistent with the present invention.

Figure 8B is a plot showing an exemplary method for changing the sampling period of a TDS ADC consistent with the present invention.

Figure 9 is a drawing showing an exemplary embodiment of a method for implementing a curve fit in a TDS ADC in accordance with the present invention.

Figure 9A is a plot depicting the analog output of an exemplary TDS ADC utilizing a curve fit in accordance with the present invention.

Figure 10 is a functional block diagram showing an exemplary process for utilizing an input signal as a non-fixed reference in a TDS ADC.

Figure 11 is a plot showing one embodiment of a time interval measurement method utilizing varying DC levels of an input modulation signal for use with a two reference level time domain switching ADC in accordance with the present invention.

Figure 12 is a graph showing the invariance of modulated signal measurements to carrier amplitude in accordance with an embodiment of the present invention.

Figure 12A is a diagram showing the invariance of modulated signal measurements to carrier frequency in accordance with an embodiment of the present invention.

Figure 13 is a plot showing various embodiments of carrier signal waveforms for use with the TDS ADC devices and measurement methods of the present invention.

Figures 14-14H are a series of plots depicting a simulation of a two-voltage TDS ADC measuring relative error as a function of the input voltage magnitude of the different values of the modulated amplitude and voltage separation, in accordance with an embodiment of the present invention.

Figure 14I is a plot depicting the jitter performance of the output noise of an exemplary TDS ADC system.

All illustrations disclosed herein are the exclusive ownership of Lumedyne Technologies, Inc. Copyright © 2011-2012.

Reference is now made to the drawings, in which like reference

As used herein, the terms "carrier" and "carrier frequency" mean, but are not limited to, generating periodic signals internally or externally useful, for example, in conjunction with an input signal during measurement of an input signal.

As used herein, the terms "computer", "computing device" and "computer device" include, but are not limited to, large computers, workstations, servers, personal computers (PCs) and microcomputers (whether desktop computers). , laptop or other), personal digital assistant (PDA), handheld computer, embedded computer, programmable logic device, digital signal processing system, personal communication device, tablet computer, portable navigation aid, J2ME equipment Loading A device, a mobile phone, a smart phone, a personal integrated communication or entertainment device, or any other device capable of executing an instruction set and processing incoming data signals.

As used herein, the terms "computer program" or "software" are meant to include any continuous or human or machine-aware step of performing a function. Such programs can virtually include, for example, to any program C / C ++, C #, Fortran, COBOL, MATLAB TM, PASCAL, Python, Verilog, VHDL, assembly language, markup language (eg, HTML, SGML, XML, VoXML ) , etc. Presented in a language or environment, and in an object-oriented environment such as the Common Object Proxy Architecture (CORBA), ^JavaTM (including J2ME, Java Beans, etc.), binary execution environment (eg, BREW).

As used herein, the term "memory" includes any type of integrated circuit or other storage device suitable for storing digital data, including (without limitation) ROM, PROM, EEPROM, DRAM, SDRAM, DDR/2 SDRAM, EDO. /FPMS, RLDRAM, SRAM, "flash" memory (eg NAND/NOR), memristor memory, and PSRAM.

As used herein, the terms "microprocessor" and "digital processor" are generally meant to include all types of digital processing devices, including (without limitation) digital signal processor (DSP), reduced instruction set computer (RISC), general purpose. (CISC) processors, microprocessors, gate arrays (eg FPGAs), PLDs, reconfigurable computing structures (RCFs), array processors, secure microprocessors, and dedicated integrated circuits (ASICs). Such digital processors can be contained on a single IC wafer or distributed across multiple components.

As used herein, the terms "top", "bottom", "side", "upward", "downward", "left", "right" and the like mean only the relative position of one element to another or Geometry does not mean absolute reference standards or any necessary orientation. For example, the "top" of an element may actually be positioned underneath a "bottom" when the component is attached to another device (eg, to the underside of the PCB).

As used herein, the term "reference signal" means (without limitation) internally or externally generated signals used to generate a triggering event, for example, during input signal measurements.

summary

In a significant aspect, the present invention provides a robust, low cost, high resolution analog to digital converter device with an adjustable measurement dynamic range (as may be used in sensing or measurement applications), and implementation And the method of using it.

In one implementation, the device uses a periodic signal of a known period to modulate an analog input and compares the modulated signal to a known reference signal level. In a variant, a single reference level is used with a known carrier frequency and amplitude. In other variations, multiple reference levels are used to enable measurement of input signals with constant carrier amplitude and frequency. When the modulated waveform intersects each reference signal level, the ADC device generates a corresponding trigger event. By merging the modulated waveform corresponding to the position of the continuous trigger event The time interval is used to estimate the period and amplitude of the modulated waveform, thereby obtaining a digital representation of the analog input signal.

In another implementation, additional reference signal levels are used to increase the frequency response and accuracy of the converter device.

The accuracy of the exemplary two reference level time domain switching analog to digital converter device is advantageous not to depend on the carrier signal amplitude or frequency, so that dynamic range adjustment can be sensed instantly. This configuration ensures that the accuracy of the device will only depend on the consistency of the trigger event, the accuracy of the reference signal level difference, and the accuracy of the time measurement of the front and rear trigger events. Moreover, various implementations of the present invention utilize noise and/or distortion compensation techniques to mitigate contributions from various effects that result in reduced accuracy.

The demonstration device is also advantageous for measuring parameter variations over a wide dynamic range. In a variant, the wide dynamic range capability described above is achieved by a change in the amplitude of the carrier signal. Furthermore, by adjusting the carrier period to control the input signal conversion rate, it is easy to adjust the ADC bandwidth and accuracy/resolution immediately.

In this way, a single ADC in accordance with the present invention can be used to measure a wide range of signal values (both amplitude and frequency), thus avoiding the use of multiple ADCs tuned to a specific (narrower) range as in the prior art. .

Detailed Description of Exemplary Embodiments

Detailed descriptions of various embodiments and variations of the apparatus and methods of the present invention are now presented.

Signal conversion

The time domain switching (TDS) ADC concept is based on a measurement time interval corresponding to a modulated signal waveform that intersects a predetermined signal level to reconstruct an input signal. In an embodiment, the modulated signal comprises: (i) a time varying voltage or current input signal (which is unknown and is the target of the measurement); and (ii) a carrier signal (voltage or current) signal. Regarding a DC input signal, the modulation signal V can be expressed as: V ( t ) = V _c ( t ) + V _input = A _c cos ( ω _c t ) + V _input (Equation 2)

Here: V(t) is the modulation signal; V _C (t) is the carrier signal; V _input is the unknown input signal to be measured; A _c is the carrier signal amplitude; and ω _c is the carrier signal radial frequency ω _c = 2πf _c .

To implement the TDS ADC, the input signal V _input is applied to the carrier signal V _C , thereby shifting the offset of the carrier signal. The carrier signal can be supplied from an external source or internally generated by a logic circuit of an ADC device (eg, an FPGA/MCU, a resonant loop circuit, a voltage controlled oscillator, etc.).

Referring now to Figure 1, a block diagram showing a generalized architecture of a time domain switching (TDS) analog to digital converter (ADC) includes front end processing 101, timing discrimination 103, control logic 109, time to digital conversion 111, and definition associated therewith. Algorithmic component 113 of the technology. The system can accept a plurality of analog inputs, including: a signal 115 to be digitized (signal ₁ ... signal _N , also known as a modulated signal), possibly a fixed or time varying reference signal (Ref ₁ ... Ref _M ), and carrier signals (carrier ₁ ... carrier _P ) that normally oscillate in nature. For example, a typical set of input signals includes: an input modulated signal, two or more fixed reference levels, and a sinusoidal carrier signal. The above components can be implemented as a hardware circuit and/or as a software component that is executed on an integrated circuit.

The front end analog signal processing 101 is configured to accept and conform the input signal 115 to its parameters/characteristics (e.g., bandwidth, filtering level, decay, etc.) to ensure proper operation of the subsequent functions of the TDS ADC. Front-end operations can include: amplification, filtering, differential signal conversion, total signal averaging, linear/nonlinear combination, and signal conversion. Exemplary front end processing embodiments include input modulation signal low pass filtering (de-aliasing), sample hold function, signal summing, and band pass filtering of the carrier signal.

Timing discriminator component 103 receives any number of analog and digital signals from the front end processing output. Based on these outputs, the timing discriminator component produces a set of digital pulses having a transition that reflects the intersection of the input modulation signal and the reference signal. By way of example, functional implementations include, but are not limited to, signal comparators, and/or limiting output high gain amplification.

Time-series discrimination can be performed, for example, by a robust and stable device for time domain oscillation measurements, such as the co-pending U.S. patent application filed in the 2011/6/24 application entitled "APPARATUS AND METHODS FOR TIME DOMAIN MEASUREMENT OF OSCILLATION PERTURBATIONS" The equipment described in the book No. 13/168, 603 is incorporated in advance by reference in its entirety. As described herein, in one indication In an exemplary embodiment, the oscillating device includes a control oscillator, a driving circuit coupled to a switching device (having at least one first component and at least one second component forming one (or more) closed switching states) And a sensing circuit. The drive circuit provides a drive signal configured to cause an oscillating action in turn to replace one (or more) of the first element(s) of the second element(s). In one method, the drive signal includes a time-gated (or "砰") signal that is turned on or off (eg, periodically). In another method, the oscillator is driven in a continuous manner, such as by a time varying wave function. When the first component of the switch and the second component are aligned, the sensing circuit generates a trigger signal indicating the closed switch state. In an exemplary implementation, two electron tunneling electrodes (one fixed and one movable) are used as switches, and when the electrodes are arranged in a closed switch position, the signal includes the wear caused by the proximity of the electrodes. Tunnel discharge pulse. The oscillation period is determined by measuring the time interval between consecutive trigger events (indicating that the oscillator passes through a reference position), whereby an external force acting on the device can be obtained.

Control logic 109 provides signal arbitration and digital processing of the digital pulse signals. For example, a function block can convert an input signal into one or more desired digital logic types (LVDS, PECL, etc.), or use combinational logic (AND, OR, XOR, NOT, etc.) for any combination of signals.

Time to digital conversion (TDC) component 111 converts a plurality of input digital pulses into associated time-series events represented by a digital value (integer, floating point number, etc.). By way of example, the components may include dedicated integrated circuit and/or field programmable gate array (ASIC/FPGA) infrastructure and vernier-scale interpolation techniques (eg, ACAM Messelectronic gmbh, Friedrich-List- Strasse 4, 76297 Stutensee-Blankenloch, Germany; installation part number: GP21) commercial solution.

The TDS ADC includes algorithm processing logic 113 that processes the TDC digital timing values and other information determined from other system components and instantly produces digital values representing the input modulation data at a particular point. The user's application can specify the specific algorithm to use. For example, the TDS algorithm may include the application of a particular equation (e.g., the equation of Table 2) that combines the ratios of the various timing intervals to produce a representation of the input modulation source at regular sampling intervals. As an additional example, the TDS algorithm can also take the form of a curve adaptation routine in which timing and reference intersection information can be used to reconstruct a model or representation of the input modulation source.

Referring now to Figure 1A, a time domain switching analog to digital conversion method will be described in detail. To reconstruct the effect of the input signal on the carrier, and thus the input signal, the modulated signal (ie, carrier plus input) is compared to a known reference level. In one embodiment, the reference level includes a preselected voltage V ₁ (indicated by solid line 104) that is within the total voltage range of the modulated signal. A trigger event occurs whenever the modulated signal waveform intersects any of the reference voltage levels. In a variant, each trigger event causes a pulse to be generated and a counter to be turned on or off. This is achieved by any mechanism capable of generating a digital pulse or switching from binary 0 to 1 (and vice versa). The counter can then be triggered on/off by the generated pulse or by the leading edge of the transition from digital 0 to 1 (and vice versa). The TDS measurement method described in Figure 1A requires knowledge of the carrier amplitude and frequency (period) to resolve the input signal as seen from Equation 2.

The exemplary embodiment of Figure 1B includes a combining circuit that combines the input signal and the carrier signal and uses a single reference level. The summed modulation signal is sent to, for example, a comparator or a window detector (as shown and described below with respect to FIG. 1E). Each comparator compares the received modulated signal V (t) and the respective reference signal (e.g. FIG. 1B in V _1). The reference signal V ₁ is arranged at a stable level selected from suitable suitable values and has a level value within the voltage range of the summed modulation signal. The control logic block receives the comparator outputs and generates respective trigger events (such as the trigger event 110 previously described with respect to FIG. 1A). As a reaction to a trigger event, control logic start / stop counter block, which is configured to use the input clock to estimate the time interval of the period T _1. The output of the counter block is sent to the time to digital converter, which provides a digital representation of the time interval between successive trigger pulses. According to Equation 2, the carrier amplitude and frequency required in accordance with a single reference level as shown in FIG. 1B TDS of the implementation of time T ₁ ADC interval measurements to reconstruct the input signal. The carrier amplitude and frequency can be determined in a variety of ways, for example, using calibration data or dedicated measurement channels.

The 1C-1D plot shows a time domain switching analog to digital conversion using two known reference signal levels. In one embodiment, the reference level comprises a preselected voltage V ₁ is and V ₂ (FIG. 1C solid line represents 104, 106), within the range of the total voltage of the modulated signal. A trigger event occurs whenever the modulated signal waveform intersects any of the reference voltage levels. In a variant, each trigger event causes a pulse to be generated and a counter to be turned on or off. This is achieved by any mechanism capable of generating a digital pulse or switching from binary 0 to 1 (and vice versa). The counter can then be triggered on/off by the generated pulse or by the leading edge of the transition from digital 0 to 1 (and vice versa).

The 1C and 1D diagrams show the measurement periods corresponding to the modulation waveforms of the two different input signals V _input1 and V _input2 respectively corresponding to the modulation waveform intersecting the reference level. The first input (as shown in FIG. 1C) produces time intervals T _r1 and T _r2 that respectively correspond to the levels V ₁ and V ₂ and generate trigger events 210, 212, respectively. A second input (as shown on FIG. 1D) to the positive waveform amplitude direction shift key, thus producing a corresponding trigger event 220, 222, respectively, to the time interval T _1> T _r1 and T _2> T _r2. Conversely, shifting the input signal of the modulated waveform down (to the negative amplitude direction, not shown) produces a small time interval (not shown). The time periods corresponding to the modulated waveforms that intersect the reference level are combined to obtain the modulated waveform amplitude (and input signal) as detailed below.

Figure 1E presents a functional block diagram of an embodiment of an exemplary exemplary TDS ADC circuit implemented by the assignee and used in the previously described time domain switching analog to digital conversion method. Device 127 includes an arbitrary waveform generator (e.g., Agilent 33522A) configured to simulate a modulated signal V(t). The modulated signal is sent from the waveform generator to a window detector, which is implemented using an exemplary dual comparator LM319 and configured to detect the intersection of the reference levels and generate a triggering event (eg, a pulse). The output of the window detector is sent to the time-to-digital converter (TDC) ACAM GP21 for the time interval T ₁ , T ₂ , T ₃ , T ₄ measurement.

The output of the TDC is forwarded to a computation block (microchip microcontroller (MCU) PIC24F) on the serial data link, which also receives the high pass filter modulation signal The number is used as a synchronization indicator. The MCU implements an input signal estimate using, for example, any of Equations 5-18 below.

Fig. 1F shows a circuit diagram of a TDS ADC corresponding to the embodiment shown in Fig. 1E.

Figure 1G shows a block diagram of a commercially available time-to-digital converter TDC GP-21 using an exemplary ADC embodiment as part of Figure 1E.

Figure 1H shows an exemplary implementation of a sampling device for use with the ADC device of the embodiment shown in Figure 1E. The time domain switching ADC sampling device includes a programmable logic block (depicted by a polygon filled with a dot pattern in Figure 1E), such as a field programmable gate array FPGA, a programmable logic device (PLD), a microcontroller, or Any other computer device configured to execute machine readable code. In one variation, the control logic is implemented in an FPGA that supports an embedded microprocessor or digital processor.

Referring now to Figure 1I, there is shown a timing diagram showing an exemplary sequence of operations for the time domain switching analog to digital converter configuration of Figure 1H.

FIG. 1J show by the first carrier waveform modulation on the input signal, wherein the input signal is compared to the V _in0 corresponds to curve 133 and curve 131 corresponds to a greater value of the input signal V _in1. In the configuration with V _in0 =0, the offset (139) corresponds to V _in1 . The data in Figure 1J shows the change in the time interval between successive trigger events (for each reference level) due to a change in the input signal (DC offset), as indicated by the horizontal arrows 141, 143 in Figure 1J. Refers to.

In another embodiment, three reference signal levels (V ₁ , V ₂ , and V ₃ ) are used to measure the amplitude of the modulated signal, as shown in FIG. 1K. In one variation, the modulation waveforms of the three reference levels intersect to produce four time intervals T ₁ , T ₂ , T ₃ , and T ₄ , corresponding to trigger events 230, 232, and 234. That is, the time intervals T ₁ , T ₂ , T ₃ , and T ₄ are constructed based on the intersection of each of the reference levels without respect to other reference levels. In another variation (not shown), is based on continuous time interval of the event triggering composition constituted, e.g., by reference to the level of FIG. 1K V _1, V _2, V ₃ intersect modulated waveform 132 produce. That is, the trigger event 122 can be combined with the trigger event 120 to measure the modulated waveform and the like. Although the reference levels V ₁ and V ₃ are shown to be symmetric to the level V ₂ , other reference signals may be used if the reference levels V ₁ , V ₂ , V _{3 are} within the expected maximum amplitude range of the modulated signal. Bit configuration. That is, for the example of the embodiment of FIG. 1K, V ₁ lines smaller (lower) A _max, and V ₃ is greater than the system (above) A _min.

In another implementation that can be applied to unipolar signal measurements, all reference levels must be positive (or negative) and the same as the polarity of the carrier signal. In a variant, a positive carrier voltage with sufficient amplitude can be used in conjunction with a negative input signal if the modulation signal offset is not sufficient to prevent switching under any voltage reference.

In the embodiment of the conversion method shown in Figures 1C, 1D, and 1K, the amplitude of the carrier signal A _c need not be known. The time intervals T ₁ , T ₂ , T ₃ , and T ₄ provide two independent estimates of the amplitude of the modulated signal: one near the waveform maximum A ₊ and the other near the waveform minimum A ₋ .

The carrier amplitude around the oscillation maximum is obtained by combining the rising reference level V ₁ intersecting period T ₁ and the reference level V ₂ intersecting period T ₂ as follows:

Here: d ₀ is the distance between the reference trigger point and the positive trigger point (trigger interval); P is the period of oscillation, defined as P = T ₁ + T ₃ ; A ₊ is the carrier amplitude around the oscillation maximum ; T ₁ is the upward reference level V ₁ intersection period; and T ₂ is the reference level V ₂ intersection period.

Similarly, the carrier amplitude around the oscillation minimum is obtained by combining the falling reference level V ₁ period T ₃ with the reference level V ₃ crossing period T ₄ as follows:

Here: P is the period of oscillation, defined as P = T ₁ + T ₃ ; A _- is the carrier amplitude estimate around the oscillation minimum; T ₃ is the falling reference level V ₁ intersection period; and T ₄ is Reference level V ₃ intersection period.

Combining equations 2 through 4 gives two independent input signal estimates as follows:

Equations 5 and 6 provide the basis for time domain switching analog to digital conversion in accordance with an embodiment of the present invention. The input signal measurement requires an accurate estimate of the time intervals T ₁ , T ₂ , T ₃ , and T ₄ as shown in the previous 1C and Equations 5 and 6. It is understood from Equations 5 and 6 that the accuracy of the TDS ADC measurement depends on the accuracy of the difference between the reference signal levels, rather than on the absolute accuracy of each individual reference level. This feature of the TDS ADC helps to improve the long-term accuracy and stability of the converter by eliminating potential individual reference signal drift due to aging, temperature, or other effects.

In one variant, the period of the carrier frequency is obtained by measuring the voltage difference between two consecutive trigger points and two voltage levels V ₁ and V ₂ (or V ₂ and V ₃ ). Regarding proximity to the DC input signal (as previously described in Equation 2), any two consecutive time intervals (corresponding to the same reference level) can be used to measure the period of the carrier signal. Regarding the time varying input signal (described in Equations 20 and 21 below), a zero crossing method is used to determine the carrier period. This is necessary because the time interval corresponding to the reference level (except 0) will be "skewed" due to the time variation of the input signal.

In another variation, the carrier period is measured by modulating the signal by any two consecutive reference levels (which are equivalent to the same reference level) over an average time period (ie, 10 to 100 times longer than the carrier period). Got it. The above method provides an accurate estimate of the carrier period for the DC and time varying input signals.

Referring now to Figure 1L, the sampling parameters for the sine wave are shown. These parameters are used to construct an estimate of the amplitude of the signal input combined with the carrier. These estimates are then used to derive the signal input amplitude without using the relationship in Equation 2. In various embodiments of the invention, an alternative and independent formulation of the estimate of the input voltage ( _Vinput ) signal is used. Such equations include, but are not limited to, the equations in Table 2 below:

Here: V _input is the input voltage

P is the oscillation period of the carrier (151 of the 1st L diagram, equal to T ₅ +T ₈ )

V ₄ is the amount of the upper or lower reference voltage level (152 of 1L)

The T ₅ -T ₁₀ system is the period between the intersections of the levels (153-158 of Figure 1L)

The equation of Table 2 can be used in conjunction with Equations 5 and 6, or used therebetween to produce a separate estimate of the input signal voltage.

The programmable logic block includes a comparator state register coupled to the output channels of the two comparators corresponding to the V ₁ and V ₂ reference signals. The logic state of the comparator is sent to the counter finite state machine (FSM), and the control of the 1D map corresponds to the second half of the operation of the four cycle counters of the periods T ₁ to T ₄ , respectively. The counter output is coupled to four registers configured to store the period periods T ₁ through T _{4 , respectively} . During operation, the modulated waveform changes due to the influence of the input signal V _input , thus generating a triggering event corresponding to the reference signal level (as shown in Figures 1C and 1D). The sensing block is configured to measure the time interval between successive trigger events (eg, trigger events (210 and 212) in Figure 1A) and to determine the input signal using Equations 2-6 above. The TDC and MCU blocks of Figure 1M correspond to the digital portion of the ADC shown in Figure 1N.

Figure 1N presents an exemplary embodiment of a TDS ADC device incorporating three reference signals in accordance with the present invention. The use of two reference levels (as shown in Figures 1C and 1D) provides additional trigger events (trigger events 114 in Figure 1C), thus doubling the number of sample points in the time interval (i.e., 2 samples per cycle). Three voltage methods are useful when dealing with shaking or time varying inputs.

Referring again to FIG. 1N, ADC device 161 includes a combining block 163 that combines the input signal with the carrier and produces a summed modulated signal. The modulated signal is sent to a row of comparators or window detectors, or to any device capable of generating pulses or changing from 1 to 0 or 0 to 1. Each comparator compares the received modulation signal V(t) with a respective reference signal (eg, V ₁ , V ₂ , V ₃ ). The voltages V ₁ , V ₂ , and V ₃ should ideally be stable and can be set to any suitable value within the voltage range of the summed signal. The control logic blocks receive the comparator outputs and generate respective trigger events (such as the trigger events 210, 212, 214 previously described with respect to FIG. 1K). As a reaction to a trigger event, control logic start / stop counter block, which is configured to be estimated using the reference clock during a time interval _{T 1, T 2, T 3} , and T ₄ in. The output of the counter block is sent to a time to digital converter that provides time period measurements using various applicable implementations (eg, FPGA or MCU implementation).

In another embodiment, shown in FIG. 10, ADC block 173 of device 171 is configured to receive and measure an unmodified input signal, while ADC block 175 of device 171 is configured to receive and measure the summed modulated signal. .

FIG. 1P depicts another embodiment of a TDS ADC device in which ADC block 175 of ADC device 181 receives the inverted carrier signal and ADC block 173 receives the aggregated modulated signal.

Figure 1Q depicts yet another embodiment of a TDS ADC device similar to the ADC embodiment of Figure 1P. In the embodiment of Figure 1Q, ADC block 175 of ADC device 191 receives the carrier signal and ADC block 173 receives the inverted summed modulation signal.

The ADC device configuration of the 1P and 1Q diagrams can directly reconstruct the input signal according to the method shown in Figure 1R. The method shown in FIG. 1R uses the time interval (eg, intervals T ₁ , T ₂ , T ₃ , T ₄ ) measured by two ADC blocks (eg, blocks 173, 175 of ADC 181 of FIG. 1P). Differentiate to get a digital representation of the input signal. The upper board 193 in FIG. 1R shows the signal waveforms sent to the ADC blocks 173, 175 of the ADC device 181 with respect to the input signal V _input being 0V. The lower panel 195 in FIG. 1R shows the signal waveforms sent to the ADC blocks 173, 175 of the ADC device 181 with respect to the input signal V _input being 0.3V.

Those skilled in the art will appreciate that when three level TDS ADCs are used to implement the embodiment shown in the 1N-1Q diagram. However, any conversion device that utilizes a single level, two levels (e.g., an ADC embodiment of the 1B, 1M map), or any other reference level that can implement a number can also be used.

Various implementations of the invention utilize full wave rectification. Full-wave rectification is the process of partially reflecting the negative of a signal to a corresponding positive value (ie, the absolute value of the signal). This process is applied to the TDS ADC to reduce the required number of signal comparisons, thus reducing the hardware used for reference intersection time discrimination. Figures 2 and 2A show graphs featuring full rectified waves. Both the reflection and the positive wave intersect the signal reference level (222, V _Reference ). From the portion in which the detail is enlarged (220 in Fig. 2), it can be seen that the timing parameter (T ₁₁ , T is obtained by measuring the period between the reference levels intersecting the rectified signal wave (224, 226 of Fig. 2A). ₁₂ , t ₁ , t ₂ , t ₃ , t ₄ , t ₅ , t ₆ ). In these embodiments, a single reference level may be used instead of an increased number of two or more levels for a given possible level of intersection. In an exemplary embodiment, the input signal can be estimated using the following:

Here: V _input is the input voltage

P is the oscillation period of the carrier (228 of Figure 2A)

V _Reference is the amount of reference voltage level (222 of Figures 2 and 2A)

T ₁₁ and T ₁₂ are periods as defined in Figure 2A (230, 232)

It should be noted that Equation 19 is presented by way of example, and other separate estimates of the input voltage may be used, including but not limited to those that are modified according to Equations 5-18 using a single reference voltage. In addition, a full-wave rectification system may use two or more reference levels to generate an increased number of individual signal level estimates (eg, increase measurement accuracy, implement averaging techniques, or perform noise compensation methods as described below) ). The full wave rectification basic system also simplifies/reduces electronics requirements. This reduces the associated noise contribution. In addition, the reference level drift effect can be reduced by reducing the number of required reference levels. In the embodiment shown in Figures 2 and 2A, the sample and hold command 234 is used to maintain the amount of rectified wave constant during the sampling period. Use this process to slow down some of the distortion during waveform sampling, as described below.

Distortion and noise compensation

In various implementations, output harmonic distortion is mitigated by using the sample and hold (S/H) function. The S/H function specifies that a particular sampling level lasts for a minimum time interval without returning to a predetermined level (eg, zero level) or as a single point sample. The sampling level continues to produce a piecewise constant output from the constantly changing input. In some variations, the minimum duration is tuned with reference to the sampling period. Alternatively, the duration may be based on other factors (such as time constants for the sampled signal, TDS carrier period, or system noise components, etc.). Given a purely sinusoidal carrier signal, when the input modulated signal is not fixed during a particular sampling interval, some TDS will be used The ADC algorithm equation (such as Equation 7) processes the timing data to cause distortion. The S/H operation produces a piecewise constant output from a particular input signal and sampling clock (S/H is also referred to as zero-order hold, and/or tracking and holding device). Some implementations of S/H can completely eliminate harmonic distortion results for time-varying input modulation signals.

The time domain switching analog to digital conversion methodology described above assumes a virtual fixed (near DC) input signal V _input (see Equation 2). In an implementation, in order to adapt the above method to measure a time varying input signal (which varies over a time scale comparable to the carrier signal period), the time varying input signal is modeled to vary linearly with a period P of the carrier signal. as follows:

Here: V(t) is the modulation signal; V _{DC_input} is the DC component of the input signal to be measured; V _{AC _input} ( t ) is the time dependent (AC) component of the input signal to be measured; φ _c is the reference clock Carrier signal phase; A _c is the carrier signal amplitude; and ω _c is the carrier signal radial frequency ω _c = 2πf _c .

Given a small time increment dt, the continuous equation 20 will appear as a discrete form, as follows:

Where: t _i, t _i-1 is a discrete time instances _{continuous, t i> t i-1} ; V i time t modulated signal at _i; A _ci is the time the carrier signal amplitude at the time _i t; V _{DC_input} Is the DC component of the input signal; V _{AC _input_i} is the time dependent (AC) component of the input signal at time t _i ; P is the carrier period; φ _ci is the carrier signal phase at time t _i .

ω _ci is the carrier signal radial frequency at time t _i .

For time varying input signals, equations 20 and 21 illustrate input signals with time V _input (t) changes to change all modulated signal V (t) due.

Figure 3 shows an embodiment of a time varying input signal measurement method using discrete equation 21. The green line is the carrier signal and is used only for comparison. The blue signal is a modulated signal that displays the time varying input signal. This effect "skews" the time period and must be solved using more general equations 21 (or sample and hold circuits with equations 5 and 6).

In another embodiment of the invention, the sample and hold circuit in conjunction with Equations 5 and 6 is used to accurately measure the time varying input signal. The purpose of the sample and hold block is to generate a quasi-DC level between successive ADC samples, making Equations 5 and 6 valid. It is assumed that the input signal does not substantially change between any two consecutive samples (eg, exceeding the time interval Δt = t _i - t _i-1 ). Note that solving equations 20 and 21 does not require a sample and hold circuit.

Referring now to Figure 3A, an embodiment of a generalized method 320 for implementing S/H techniques is shown. At step 322, an analog signal comprising an input signal modulated by a carrier is received in the S/H circuit. At step 324, a trigger event occurs (eg, reference voltage level intersection, etc.). Once a trigger event occurs, the analog signal level is measured (step 326) and the measurement waveform is maintained at the measurement level for the duration of the S/H circuit (eg, until another sample, portion of the carrier cycle, etc.) (step 326) ). The measurement waveform is then passed to other other TDC circuits for further analysis (step 328). Once the TDC output is obtained, the timing value is converted from the time domain to a voltage level equivalent using a known value of the reference level and carrier frequency. The generalized method 320 can be utilized, for example, in conjunction with the exemplary circuit 370 of FIG. 3E below.

Referring now to Figures 3B and 3C, the efficacy of an exemplary embodiment of the sample and hold technique 320 is shown. Figure 3B shows a simulation of a non-realistic S/H technique. Both input signal 332 and harmonic 334 are in the output signal. In the simulation results shown in FIG. 3C, method 320 is implemented and harmonics 334 are completely suppressed, while input signal 332 still exists.

Another embodiment 350 of the TDS ADC is shown in Figure 3D. An external analog signal 352 is provided to system 350. Applying the sample and hold means 354 to the input signal causes the piecewise constant value to be maintained at a fixed interval (with twice the period of the carrier signal). A sinusoidal carrier signal synchronized with the sampling interval (for convenience) is added to the sampled input signal. This result is a full waveform that is rectified using rectifier/comparator block 356 and compared to a fixed reference level to produce a digital timing pulse. The pulses are received by time to digital conversion device 358 (eg, ACAM Messelectronic gmbh, Friedrich-List-Strasse 4, 76297 Stutensee-Blankenloch, Germany; part number: GP21) and converted into a set of equal digit time values (t ₁ , t ₂ , t ₃ , t ₄ , t ₅ , t ₆ ); the measured time series is processed using the TDS ADC algorithm component 360 represented by Equation 19 to produce an output digit value. In this example, the algorithm is implemented in software and the output values are floating point numbers.

The high signal authenticity of the S/H device ensures maximum signal to noise ratio and low distortion conversion. Referring to Figure 3E, an exemplary S/H circuit 370 is shown. The S/H circuit shown in FIG. 3E can be used, for example, with the exemplary method 320 of FIG. 3A described above or others.

The differential amplifier 376 differentially drives the hold capacitor 378 load through the two closed switches (372 and 374) (the open relationship in Figure 3E is depicted in the open position). The input signal 380 is tracked with minimal distortion and noise due to the differential amplifier and the holding capacitor is added. The measurement amplifier 382 delivers the charge of the capacitor with little or no voltage drop distortion to the low impedance output driver of the circuit.

Through the two open switches (372 and 374), the charge on the holding capacitor 378 is maintained due to the high dissipation rate of the holding capacitor 378 and the high impedance input of the measuring amplifier. The charge held on the capacitor is continuously transmitted by the measuring amplifier to the output drive (also with little or no voltage drop).

In an exemplary embodiment, it is turned on by S/H control device 386 or The switches (372 and 374) are turned off to generate a frequency cut signal. The use of a holding capacitor to integrate the result of the cut signal results in a differential summation of the signal.

Figure 3F shows a circuit diagram of an embodiment of the TDS ADC device shown in Figure 3D.

Figure 3G presents data on a TDS ADC simulation using a sample and hold method to generate a quasi-static DC modulation signal in each oscillation cycle. The data in the 3G graph is obtained as follows: modulation (20% of the amplitude of 50 Hz), carrier signal: 1.5 V peak, 1.5 V DC, frequency 500 Hz. Signal samples are calculated every two carrier cycles (corresponding to a dual reference level ADC configuration) as described in Figure 1B above.

In one variation, two sample and hold circuits are implemented, one for positive and the other for negative oscillation periods, thereby doubling the sampling rate of the TDS ADC.

S/H technology can be used to deal with the distortion caused by the measured signal or in the measurement itself. However, other distortions can be caused by the carrier waveform itself. Any unwanted distortion of the carrier will result in a corresponding distortion of the calculated signal. By eliminating the distortion of the algorithm, polynomial compensation with specific coefficients on the distortion of the carrier can be used to eliminate distortion from the carrier. For example, the correction signal V' is related to the distortion value V by the following equation: V ' = Va ₁ V ² - a ₂ V ³ - a ₃ V ⁴ - a ₄ V ⁵ ... - a _n V ⁿ⁺¹ ( Equation 22)

The correction factor can be estimated from the measurement of carrier distortion. Carrier distortion and correction coefficients may be initially set and calibrated, or carrier distortion may be monitored during use of the device to periodically correct to change carrier distortion over time. In addition, the correction factor is decisively related to the carrier amplitude. When the carrier amplitude is monitored, the coefficients can be updated accordingly. The carrier amplitude can be calculated, for example, as:

Let R denote the change in carrier amplitude from the initial amplitude A ₀ :

The first three harmonics of the carrier can be compensated for in the measured input signal value by including the relationship of R in the correction equation. As an example, the three harmonics of the carrier are corrected and the change in carrier amplitude is taken into account:

To correct the four harmonics of the carrier, the following correction equations can be used:

As long as the distortion of the carrier (the number and magnitude of carrier harmonics) is known, the distortion produced by the calculated signal can be corrected.

Referring now to Figure 4, an embodiment of a generalized method 400 for carrier distortion compensation is shown. At step 402, a modulation signal is received at the input. The time varying amplitude is estimated and used in turn to estimate the input voltage (step 404, i.e., the input signal to which no carrier is added). The time variation added to the carrier component of the signal can cause harmonic distortion during the estimation of the input voltage. This illustrates the distortion caused by the time variation in the input voltage itself or its measurement as compared to the sample and hold method 320. Therefore, in step 406, the measured signal application to mitigate the effects of the harmonic components of the carrier has A polynomial expression of the carrier of the predetermined correction factor (see Equation 26).

Exemplary results of this method of distortion correction are shown in Figures 4A-4C. Figure 4A shows two analog outputs, one with no corrected distortion and one with distortion corrected by a carrier with a single input frequency. In both analog outputs, a carrier signal input contribution 412 is presented. However, harmonics 414 will exist in the original output but cannot be seen in the compensation output. Figures 4B and 4C show pairs of data sets that exhibit distortion at multiple input carrier frequencies (multiple peaks 412) and to change the carrier amplitude.

In some implementations, methods 320 and 400 can be combined to estimate with compensation for both input/measure distortion and carrier waveform distortion.

The resolution of the analog to digital conversion is related to the spectral saturation and noise characteristics of the carrier. The uncertainty of the frequency of the carrier (eg, due to spectral and noise components) results in reduced accuracy, where the parameters used in estimating the amplitude of the input signal are based on this accuracy. One method of reducing this factor is to pass the filtered carrier, which is the process of attenuating the frequency components outside the predetermined bandwidth of the filter. In general, the pass band of the selection filter overlaps with the intermediate frequency of the carrier. Bandpass filtering reduces the amplitude (and distortion contribution) of the frequency components that are separated from the fundamental frequency of the carrier.

Figure 5 shows the simulated reduction in the amplitude resolution of the measured input signal in a system implemented with bandpass filtering. The calculated input signal is simulated using the measured carrier input noise as an analog input. Digital filtering is applied to the carrier input.

Multiple input signals can be implemented by adding a common carrier waveform to each input signal. The input signal of the common carrier can be, for example, time, Phase, or frequency multiplexing. Alternatively, multiple phase or frequency offset carriers can be used. Each input signal/carrier combination can each be measured as a separate ADC or time interleaved with a single ADC device.

Using multiple ADC channels can facilitate measurement accuracy of the signal. For example, multiple simultaneously measured carriers are combined with input signals, channels that measure carriers of different phases. Alternatively, multiple phase shifting examples of the input signal can be added to a common carrier. Multiple ADC channels are capable of differential signaling techniques and subtracting carrier noise. Multiple ADC channels also allow for additional averaging, which improves the measurement accuracy of certain types of input signals.

The effect of carrier noise on the conversion resolution can be reduced by implementing two or more simultaneous ADC measurement channels. In an exemplary embodiment, the measurement of the time interval produced by the input signal plus the carrier is measured on one channel and the second channel is used to measure the same carrier without the input signal. The uncertainty measured in the time interval between the two ADC channels can be related to the common mode noise from the carrier. Once quantified, this uncertainty can be removed. The conversion resolution improvement for an exemplary simulation system is shown in FIG. In this example, the actual carrier waveform is sampled and used as the basis for the simulation results. For this example, it is clear that the benefits of carrier uncertainty subtraction are associated with appropriate pre-filtered carrier waveforms.

Figure 6A presents an embodiment of a TDS ADC configured to provide measurements of carrier frequency and amplitude simultaneously and independently of input signal measurements. The ADC device of Figure 6A includes two ADC blocks 602 and 604 (as in the ADC block 123 shown in the previous Figure 1B). ADC block 602 is configured to receive and measure the summed modulated signal, and block 604 is configured to receive only Carrier signal. The ADC device 610 further includes a TDS ADC processing block that is used for common mode noise estimation and rejection and input signal estimation algorithms (e.g., according to Equations 5 and 6). The ADC configuration as shown in Figure 6A facilitates providing a convenient means of measuring the period and amplitude of the carriers used in Equations 5 and 6.

Figure 6B shows a block diagram of one embodiment of a time domain analog to digital conversion device using two reference signal levels. The device 121 of Figure 1B includes a combining circuit that combines the input signal and the carrier. The summed modulation signal is sent to a row of comparators (or the window detector as shown in Figure 1E above). Each comparator compares the received modulation signal V(t) with a respective reference signal (eg, V ₁ , V ₂ ). As mentioned above, the reference levels V ₁ and V ₂ should ideally be stable and can be set to any suitable value within the voltage range of the summed modulation signal. The control logic blocks receive the comparator outputs and generate respective trigger events (such as the trigger events 110, 112 previously described with respect to FIG. 1C). As a reaction to a trigger event, control logic start / stop counter block, which is configured to use the input clock is estimated during a time interval T ₁ and T ₂ are the. The output of the counter block is sent to the time to digital converter, which provides a digital representation of the time interval between successive trigger pulses.

Figure 6C presents an embodiment of a TDS ADC configured to provide both carrier frequency and amplitude measurements and no input signal measurements. ADC device 680 includes two ADC blocks 682 and 684. The ADC block 682 is configured to receive and measure the summed modulated signal, and block 684 is configured to receive only the carrier signal. The ADC device 680 further includes a TDSA processing block, which is actually used as a common mode noise estimation and rejection algorithm. Figure 6C The ADC embodiment facilitates the use of Equations 5 and 6 as described above to allow calculation of the positive and negative periods of the carrier. Although it is also possible to use only two references to measure the positive and negative modulated signal periods, it is desirable to have three references due to the symmetry of the modulated oscillations and the reference signal configuration. Such a configuration facilitates accurate measurement of the slope of each side of the modulated signal to predict speed and acceleration items (assuming the voltage replaces the y-axis), thereby enabling more accurate measurement of rapidly changing input signals.

The ADC configuration as shown in Figure 6C can facilitate common mode noise estimation by comparing the time interval of the carrier (e.g., measured at ADC block 684) with the time interval of the modulated carrier (measured by ADC block 682) ( And compensation). Since both ADC blocks 682, 684 use the same signal reference, common mode noise can be estimated and removed. Furthermore, the ADC configuration of Figure 6C facilitates providing a convenient means of measuring the period and amplitude of the carriers used in Equations 5 and 6.

Various other implementations rely on other types of two-channel measurements. Referring now to Figure 7, an exemplary differential signaling technique 700 is shown. At step 702, on the first channel, the time interval at which the carrier plus the input waveform is measured (ie, the period between the intersections of the reference levels) is measured. In parallel step 704, the time interval corresponding to the carrier minus the input waveform is measured on the second channel. This result is then subtracted from each other to produce an estimate of twice the signal input level (step 706). In some variations, this result is subtracted after estimating the input signal level. In other variations, this result is subtracted before the input signal level is estimated. Referring now to Figure 7A, the effect of method 700 is shown. Method 700 has been shown through simulation to preserve signal input 722 and eliminate all even The harmonics 724, as well as the important part of generating harmonic distortion. However, odd harmonics 726 are still left.

Referring to Figure 7B, the functional block diagram shows the line pattern for an exemplary embodiment 780 of the differential measurement circuit. In this embodiment, the carrier and signal are split into two parallel paths (782 and 784). One path uses voltage adder 786 and the other uses voltage subtractor 788. The modulated waveform is then input into the TDS ADC 790 to measure separately and compare the outputs of the two paths. Other differential architectures including two or more channels, and various combinations of input signals and carriers can reduce harmonics without the need for curve adaptation or sampling and hold.

In some variations, other differential signal/carrier combinations are used. In these examples, a positive or negative (reverse amplitude) input signal is mixed with a positive or negative carrier waveform. This produces four possibilities (732, 734, 736, 738), which are shown in Figure 7C. These different combinations produce varying independent time event measurements that can be used in method 700 to mitigate distortion that occurs in various stages of the ADC process (eg, sampling, measurement, carrier effects, etc.).

Referring now to Figure 7D, there is shown an exemplary process in which differential signal techniques can be used to indicate the reference level drift. Differential techniques (e.g., process 700 of Figure 7) distinguish between carrier offset or signal offset and reference level drift. Differential measurements are not susceptible to changes in carrier or signal offset (ie, timing values are changed in the same way for positive/positive modulated signals and negative/negative modulated signals). However, the timing values are offset by making the reference level shift amount (for various differential combinations) different. Compare these offsets to indicate Reference level drift.

Some embodiments of the invention implement an averaging method. Exemplary averaging techniques include, for example: (i) a technique for combining data points generated by a TDS ADC algorithm, (ii) another technique involving an average time interval prior to applying a signal estimation algorithm, and (iii) based on multiple Reference level technology.

Combining the points produced by the TDS ADC includes a plurality of estimates that produce signal levels (eg, many measurements that are parallel on a repeated/fixed signal or on a single signal) and then average the results.

The average time interval consists of moving the average distance earlier in the process instead of waiting until the estimate is completed. The average interval itself is measured multiple times, and an estimate of the signal input is generated from the average time interval value. In this example, the averaging is also based on multiple parallel measurements of the same signal, and/or multiple consecutive measurements of the repeated/fixed signal. It should be noted that in some cases, a signal that changes much more time than the sampling rate can be considered a fixed signal.

Multiple reference levels allow the calculation of the input signal to be performed using time intervals in association with noise. As the number of reference levels increases, the number of measurements and the average number increase. In the case of multiple reference levels, measurement accuracy is increased by adding some circuit complexity. However, the complexity and benefits must be weighed against the ability to implement multiple averaging without reducing the system bandwidth.

Figure 8 is a graph showing the improvement in noise level using an averaging technique based on a plurality of uncorrelated measurements that produce timing intervals. The figure shows that the improvement in the noise level is close to the limit of its theory. Another average technique shown in Figure 8A The system is based on increasing the sampling period. This can increase the number of points to average. However, it will increase the period during which the system can sample the smallest features. Therefore, this is equivalent to reducing the system bandwidth. More generally, the sampling period can be adjusted with respect to the carrier period. The sampling period can be compressed to half the period of the carrier. This can be used to increase the average point. In other implementations, this half-cycle measurement can also be used to reduce system startup time to reduce resource consumption.

Referring now to Figure 8B, an exemplary embodiment of a sampling method using a shorter measurement period is shown. This embodiment can increase the measurement bandwidth over other compensation methods because no filtering or bandwidth limiting circuitry is required. Power savings can be achieved by periodically measuring the power between measurements because the increased system bandwidth allows for shorter measurement periods. Alternatively, these shorter periods can be used to measure timing parameters (eg, half-cycle measurements) over even shorter time intervals to increase the sampling frequency. In addition, the system can be controlled to reduce noise to achieve increased resolution.

Curve adaptation

Various implementations of the invention utilize curve adaptation techniques. Various implementations of these techniques are used to achieve algorithmic distortion reduction, improved input estimation accuracy, and/or timely estimation of input levels at any point. The above curve adaptation techniques include, but are not limited to, Levenberg-Marquardt estimation, Nelder-Mead monomer analysis, and polynomial curve adaptation techniques.

By way of example, the polynomial adaptation process is described below. In this example, the carrier is a sinusoidal waveform and the number of triggers is generated based on the addition of the carrier to the input signal to be tested. The related functions and parameters are shown in Figure 9. Trigger point 902 is used to generate an adaptation curve that represents all modulated signals (904, all polynomial fits). Carrier 906 is modeled as a polynomial estimate of a sinusoidal function. All polynomial fits are subtracted from the carrier to produce an external signal input 908. For this process, all modulated signals 904 (signal and carrier) are defined as: V _total ( t ) = A sin( ωt + φ ) + V _input ( t ) (Equation 27)

A "least square" polynomial fit 904 is generated for V _total (t) due to the trigger event. The measured trigger point and its associated reference level form a matrix :

Use the following relationship to get the matrix P:

The input signal 908 is then estimated by the following:

The carrier 906 here is:

The simulation results using the above polynomial fitting method are shown in Fig. 9A. Regarding the area close to the trigger point, an average error of 1.5 ppm is achieved in this example for estimating the signal input.

Reference level

In various embodiments, the input signal itself (or processed input) can be used as a reference instead of a fixed reference source. The input can be added or subtracted, multiplied or divided by a fixed reference source. Alternatively, the phase shifted carrier can incorporate or replace a fixed reference. Each of these possibilities creates a time interval that can be used to calculate the input signal. Non-fixed references provide the advantage of reducing common mode noise caused by carrier or reference, as well as errors due to reference drift. Figure 10 shows an exemplary embodiment in which a fixed reference level circuit 1050 is replaced with the input signal itself as a reference. In signal reference embodiment 1000, the timing period is defined by an event where the carrier intersects the signal input voltage level. The timing between these intersecting events changes as the voltage level of the signal input rises or falls. Conversely, if the voltage level of the signal remains the same, the timing will remain the same. Therefore, these timing values can be used to estimate the current signal level.

While some of the previously described embodiments use two or three reference signal levels, those skilled in the art will appreciate that the practice of the present invention is not limited to the embodiments described above, and any feasible number of reference levels may be used. . Additional reference levels provide additional timing information to enhance modulation and input signal measurements. Furthermore, additional signal levels increase the converter frequency response. The time varying input signal will "skew" the modulated carrier signal and may affect the quality of the signal waveform fitting function (see, for example, Equations 5 and 6). Additional trigger events associated with additional reference levels result in better signal waveform fit.

Waveform analysis

Figure 11 shows an exemplary screen capture of a window detector showing the time interval between two consecutive trigger events. These intervals may vary as a function of the input signal DC bias level of the input modulation signal.

The input signal of the amplitude and/or frequency of the unrelated carrier signal can be measured by the time domain switching analog to digital conversion method described in the preceding equations 5 and 6. Figures 12 and 12A present simulation results obtained with an exemplary ADC device of the embodiment of Figure 11. Figure 12 shows the RMS voltage (in volts (V)) of the input signal taken as a function of carrier amplitude (in V). The data shown in Fig. 12 illustrates that the TDS ADC measurement method of the present invention is not susceptible to carrier amplitude. Figure 12A shows the RMS voltage (in V) of the acquired input signal as a function of carrier frequency (in Hz). The data shown in Fig. 12A illustrates that the TDS ADC measurement method of the present invention is not susceptible to carrier frequency.

The simulation results shown in Figures 12 and 12A confirm that the reconstructed (measured) signal is not susceptible to time variations in the amplitude and/or frequency of the carrier signal. The characteristics of these measurement methods of the present invention are advantageous for enabling the TDS ADC device of the present invention to dynamically adjust measurement characteristics during operation. In particular, a change in carrier amplitude can adjust the sampling range of the signal, whereby the ADC dynamic range can be adjusted instantaneously by ensuring that the time intervals T ₂ and T ₄ remain above the required minimum. Furthermore, changes in the carrier frequency can adjust the ADC sampling rate without affecting the reconstructed signal. This allows the sensitivity of the ADC to be adjusted on the fly (lower carrier frequencies allow for more bit resolution).

In one embodiment, the reference signal level is scaled with the carrier signal amplitude, and thus any input signal within the limits of the power of the TDS ADC device can be adjusted.

The frequency of the carrier can be adjusted by the user inputting to the ADC externally or by automatically monitoring the maximum rate of acceleration change per cycle and adjusting the frequency appropriately.

Figure 13 shows various embodiments of carrier signal waveforms (other than the sinusoidal signals previously described) useful for the time domain switching analog to digital conversion apparatus and methods described herein. The sawtooth 1302 or triangle 1304 waveform provides a linear relationship between the measured time period and the offset due to the input signal. Waveforms 1306, 1308 may be useful for small input signal offsets because the slope of the carrier waveform will be small enough to be close to the origin (equivalent to a small offset). When sampling a low frequency signal without sacrificing the sensor sampling bandwidth (which is associated with reducing the sampling frequency), a small slope helps to improve accuracy, because when the modulation signal slowly changes through a critical level, the energy ratio has The steep slope modulation signal measures the time period more accurately. The waveform shown in Fig. 13 is exemplary in nature. Algorithms capable of performing the functions required for TDS ADC operation can be generated using various carrier signals having well-defined waveform characteristics that are expected to be repeated.

Demonstration performance

FIG 14-14H first exemplary presentation of the information on the amplitude of the carrier of the relative error sensitivity, and the reference voltage signal level difference _{△ V = V 2 - V 1} . The data in Figures 14-14H is obtained with a fixed carrier frequency of 1000 Hz and a sampling clock resolution of 10 microseconds (ps). The lines indicated by arrows 1402-1420 in Figures 14-14H are obtained as follows: - Figures 14-14B conform to the carrier amplitude of 10V, and the reference signal differences are 0.2V, 0.4V and 1V, respectively; and - 14C The -14E map satisfies the carrier amplitude of 5V, and the reference signal difference is 0.25V, 0.5V, and 1.25V, respectively; and - the 14F-14H map conforms to the carrier amplitude of 2.5V, and the reference signal difference is 0.25V, 0.5V, and 1.25V.

As can be seen from the data presented on FIG. 14-14H, a small reference signal corresponding to a difference △ V is typically high relative error (e.g., as shown in FIG. 14G thereof than the first curve in a graph of FIG. 14H 1420 1416 is more upward offset), while the smaller carrier amplitude corresponds to a lower relative error and a lower voltage measurement range (eg, as shown by curve 1402 in Figure 14, which is more than curve 1420 in Figure 14H) Off and to the left).

As can be seen from the data in Figures 14-14H, the performance of the exemplary TDS ADC is characterized by certain quantified noise layers. That is, there are some detectable voltage levels that can be detected and converted (to some level of accuracy). By way of example, a voltage of 0.2 millivolts (mV) can be measured with an accuracy of 50 nanovolts (nV). This means that the TDS ADC can detect input signals that are lower than this threshold, although the ADC resolution will be much higher. In an embodiment useful for measuring low amplitude signals, the TDS ADC can be configured to apply a small signal (of known amplitude) to the input signal to be able to use the full range of ADCs to drop to a 50 nV resolution level. By subtracting the "known" input Signals, we can directly measure small input signals that are too small for us to detect. This embodiment is presented by way of example and in no way limiting the scope of the invention.

Referring now to Figure 14I, a plot showing the output noise of an exemplary TDS ADC system versus jitter performance is shown.

Demonstration use and application

The exemplary TDS ADC apparatus and method of the present invention can advantageously convert signals that vary over a wide dynamic range. In one variation, the wide dynamic range capability described above is achieved by adjusting the carrier signal amplitude during operation of the ADC. Furthermore, by adjusting the carrier period to control the signal conversion rate, it is easy to adjust the ADC bandwidth and accuracy in real time.

This feature is also commonly referred to as "automatic modulation," and a single ADC of an exemplary embodiment of the present invention can be used to measure a wide range of signal values (both amplitude and frequency), thus rejecting as used in conventional techniques. Adjust to multiple sensors in a specific (narrower) range.

Furthermore, since the resolution of the TDS ADC is determined by the ratio of the input modulation frequency and the clock resolution, the ADC device of the present invention can achieve extremely high resolution, for example, more than 30 bits, without being expensive and high. Power implementation (characteristics of currently available ADC devices). In addition, the TDS ADC resolution and bandwidth can be adjusted instantaneously by adjusting the carrier frequency.

In addition to the front-end comparator, the entire conversion method is digital, thus eliminating many sources of noise and drift (such as analog component drift). Demonstration of time domain switching analog to digital converter device accuracy is advantageous for carrier-independent signals Amplitude or frequency, therefore rejecting the need for calibration. The above configuration further ensures that the accuracy of the device is determined only by the consistency of the trigger event, the accuracy of the reference signal level difference, and the accuracy of the time measurement of the front and rear trigger events.

The use of additional signal reference levels is used to further improve the frequency response and accuracy of the converter device.

As mentioned above, some of the sensor embodiments described herein measure the input signal based on the ratio of the clock frequency to the modulation frequency, thus making the sensor accuracy less susceptible to clock drift (to the first level). . In addition, measurements averaged over multiple oscillation periods can filter out unwanted noise.

If the output is faithfully quantified, the average will not help. In this example, dithering is used to introduce a small amount of white noise into the clock or input signal, enabling an average output. Input jitter is typically on the scale equivalent to a 1/2 clock cycle.

The TDS ADC concept described herein in particular makes power conversion techniques impractical in other ADC architectures. For example, if the data is sampled less often than once per cycle, the TDC measurement block can be placed in a low power or "sleep" mode during the period of the carrier where the data is not calculated. In addition, the input signal can be calculated from short time intervals separated by longer intervals (where no time interval information is necessary). In this case, the digital side of the input signal in the logic control block can be used to trigger the TDC device to enter an active mode. The TDC can then measure the trigger time of the signal pulse train of the time delay. After measuring a certain number of trigger points, the TDC can enter a low power sleep mode before the next set of pulse edges arrive. Another example of power conversion is to change the frequency of the carrier. Higher frequency carriers will be able to generate It calculates a small time interval of the input signal, thus reducing the total amount of time required to start the TDC. In this case, there may be a trade-off between accuracy (decreased as the carrier frequency increases) and power.

In addition, TDS TDC technology can be used to convert digital pulses into time series events. One advantage of using TDS TDC technology is the ability to perform time measurements with excellent resolution (under 10 picoseconds) with very low power. The ability to measure time events with excellent resolution is a key component of the high resolution advantages of TDS ADCs. For example, at a 1 kHz bandwidth, the signal can have features of the order of 10 ^-3 seconds. However, the TDS TDC implementation consistent with the present invention provides the ability to measure these features with a resolution of ^10-12 seconds. This means that there are 9 magnitude differences between the measured signal and the resolution.

In the conventional method of solving time measurement, a counter driven by a high speed clock is gated by an ADC digital pulse. In order to achieve excellent resolution (eg, on the picosecond level), a high speed clock signal that oscillates at a frequency close to 1 THz may be required. This method will surpass the limitations of modern high-speed electronics.

In an implementation of the TDS ADC technique consistent with the present invention, a vernier interpolation technique is used. Similar to a machine vernier scale that requires two scales, two clock signals are required. One of the clocks operates at a higher frequency than the other clock. The lower frequency clock is used to gate the "poor" counter, while the higher frequency clock is used to gate the "fine" counter (for example, the counter can count its respective clock signal to intersect a voltage reference level) The number of times). At the start time measurement, the "poor" counter is started. When the end event occurs, the "fine" counter is started. When the low frequency clock and the high frequency clock finally occur simultaneously (ie, they simultaneously generate a gate event) Then stop the two counters. The counter value is then used to calculate the time measurement and achieve excellent resolution. An exemplary vernier timing technique is described in Lange et al. (K. Lange and M. Kasnia, "Application of Vernier Interpolation for Digital Time Error Measurement," Poznan Workshop on Telecommunications, 2008 11 Dec. 2008), by Reference is made to the above in its entirety. An exemplary apparatus for measuring time intervals using a small amount of delay measurement is described in U.S. Patent No. 3,611,134, entitled "APPARATUS FOR AUTOMATICALLY MEASURING TIME INTERVALS USING MULTIPLE INTERPOLATIONS OF ANY FRACTIONAL TIME INTERVAL", filed on 1969/4/30, and U.S. Patent No. 4,164,648, the entire disclosure of which is incorporated herein by reference in its entirety in its entirety in its entirety in the the the the the the the the the the the the the the the the the

One design compromise of the vernier interpolation technique is the time at which the two clocks occur simultaneously. Longer simultaneous times result in better time resolution measurements. In particular, if the high and low frequencies are approximate (but well defined and distinct), their phase offsets can be measured with high accuracy (if any errors in the measurement are distributed over many clock periods) ). Note that the time required to reach a simultaneous event is close to infinity because the higher frequency is close to one of the lower frequencies or its harmonics (assuming a non-zero phase offset). This phase offset can be used to calculate where the lower frequency clock will cycle when the end event occurs. This results in an accurate measurement of past cycles. cursor Advantages of the ruler technology include saving power during the entire duty cycle (ie, the clock does not have to operate continuously, so it can be turned off temporarily to reduce power consumption), and has the opportunity to continuously calibrate the power of the misaligned clocks in the two clocks. And temperature changes. The vernier technique has been implemented in commercially available devices with common integrated circuit processing (e.g., CMOS) for time-of-flight applications (i.e., ultrasonic instruments). The application of this technology and other TDC technologies provides significant advantages and synergies over TDS ADCs over other ADC technologies.

In various implementations, the TDS ADC uses a tapped delay chain before successively connecting a series of registers, wherein the input signal (or input clock) to be tested is continuously delayed by an equal amount. The total delay is designed to cover at least one clock cycle that causes a transition point (1-0 or 0-1) in the scratchpad chain. This represents the input side time between two clock cycles and can be used to achieve fine time measurements. In addition, the number of clock cycles between the two input sides can be counted to provide a poor measurement. These two combined measurements provide a total measure of the time between the two sides with the accuracy of the measurement set by the delay. In CMOS based implementations, the delay times are equal and a test pulse is used to periodically recalibrate the delay time to compensate for environmental conditions. The advantage of this method is that only a single system clock is required. This method has been implemented in field programmable gate array (FPGA) technology that is limited by unequal tap delays. Various techniques have been applied to compensate for unequal tap delays. An exemplary technique for using FPGA based methods to achieve 10 picosecond accuracy is described in Wu (J. Wu, "On-Chip processing for the wave union TDC implemented in FPGA," in Real Time Conference, 2009. RT). '09.16th IEEE-NPSS, May 2009, pp. 279-282) and Wu et al. (J. Wu, Z. Shi, "The 10-ps Wave Union TDC: Improving FPGA TDC Resolution beyond Its Cell Delay," in Nuclear In Science Symposium Conference Record, 2008 IEEE, 19-25 Oct. 2008: 3440-3446, the two are hereby incorporated by reference in their entirety.

Table 3 summarizes exemplary performance parameters for a TDS ADC device configured in accordance with the present invention. As can be seen from the data in Table 3, the exemplary embodiment of the TDS ADC of the present invention facilitates providing a higher dynamic range and lower nonlinearity error at a lower cost than other ADC techniques.

Although the content of the voltage conversion is mainly discussed, the present invention is not limited thereto. In fact, many other physical sensing mechanisms are useful for the sensor devices and methods described herein, including but not limited to: current, compression waves, seismic activity, intensity, frequency, phase, and the like.

It is to be understood that while certain aspects of the invention are described as a particular sequential step of the method, these descriptions are only illustrative of the broader methods of the invention and may be modified as needed for the particular application. In some cases, certain steps may be made unnecessary or unnecessary. In addition, some steps or functions may be added to the disclosed embodiments, or the order of the two or more steps may be interchanged. All of the above variations are contemplated to be encompassed by the invention disclosed and claimed herein.

While the foregoing detailed description has been shown and described, the embodiments of the present invention And changes without departing from the invention. The foregoing description is based on the best mode of practicing the invention. This description is in no way meant to be limiting, but rather to be construed as a generalized principle of the invention. The scope of the invention should be determined by reference to the scope of the patent application.

101‧‧‧ front-end processing

103‧‧‧Timing discrimination

109‧‧‧Control logic

111‧‧‧Time to digital conversion

113‧‧‧ algorithm components

115‧‧‧ signal

Claims (13)

An analog to digital converter device comprising: an interface configured to receive an analog input signal, wherein the analog input signal is a periodic signal from an inertial sensor, the analog input signal being at least partially based on an entity displacement of the oscillating element; and processing Communicating with the interface and configured to: identify a reference level; detect an intersection of the reference level with the analog input signal; determine a plurality of timing periods based on the detected intersection; based at least in part on the A plurality of timing cycles that produce one or more digital estimates of the analog input signal. The converter device of claim 1, wherein each of the timing periods comprises a time interval between two of the detected intersections. The converter device of claim 2, wherein the inertial sensor comprises: a verification block; a position sensing electrode disposed on the verification block; and a driving circuit configured to cause the verification block to be sensed relative to the position An oscillating action of the electrode; an inductive circuit coupled to the position sensing electrode and configured to generate a first pulse having a first time value, and a second pulse having a second time value; the plurality of timing cycles being The second time value and the first time value The difference is determined; the difference is configured to be based at least in part on the displacement of the verification block. The converter device of claim 3, further comprising a comparator configured to generate a substantially binary signal based on the analog input signal and the reference level. The converter device of claim 4, further comprising: a counter configured to trigger an on and off in response to the substantially binary signal generated for the comparator; and the plurality of timing periods It is determined by this counter. The converter device of claim 5, wherein the counter triggers an open and a close when the analog input signal intersects the reference level. The converter device of claim 3, wherein the processor is further configured to apply a trigonometric function to the independent variable according to at least one of the plurality of timing periods to determine a triangular result; and the triangular result Extract the inertia parameter of the inertial sensor. The converter device of claim 7, wherein the processor is further configured to: receive a second timing cycle; determine a sum of the first and second timing cycles; determine the first and second timing cycles a ratio of one to the sum; determining an independent variable based on the ratio; and applying a trigonometric function to the independent variable. The converter device of claim 8, wherein the The processor is further configured to: determine the second triangular result based on the ratio comprising the plurality of triangular results. The converter device of claim 1, wherein the interface is further configured to: receive a second analog input signal; generate a modulated signal according to the analog input signal and the second analog input signal; and detect The one or more reference levels intersect the modulated signal. The converter device of claim 10, wherein the converter device further comprises a dynamically adjustable dynamic measurement range; and the adjusting is performed based on an amplitude of the at least one analog input signal. The converter device of claim 1, wherein the converter device further comprises a compensation device configured to mitigate one or more signal distortions. The converter device of claim 1, wherein the converter device further comprises a sample and hold device configured to provide a fixed sampling amplitude over a sampling period of the converter device.