TWI566105B - Rack - Google Patents

Description

Chassis device

The present invention relates to a chassis device, and more particularly to a chassis device having a Basic Input/Output System (BIOS) supporting an Extensible Firmware Interface (EFI).

Since the introduction of the world's first personal computer (PC) in the early 1980s, the Basic Input/Output System (BIOS) has become a must-have system firmware for personal computers. Manage basic hardware devices, provide various interrupt mechanisms, boot operating systems, and more. Today, the operating system of personal computers has entered 32-bit and 64-bit. Today, the traditional basic input and output system still stays in the real mode of 16-bit, making the development of basic input and output systems difficult, and more because of its architecture and memory. The limitation of the body severely limits the number of devices that can be connected to the personal computer.

In order to solve the problems of the traditional basic input and output system, some people have proposed a basic input and output system supporting the EMF. The Elongate Firmware Interface (EFI) is a specification for a personal computer system to define the operating system. A software interface to the system firmware. This basic input/output system mostly accesses a memory using a Serial Peripheral Interface Bus (SPI) during booting. For example, at boot time, the basic input/output system reads user settings stored in the memory, such as boot options, boot orders, user passwords, etc., and these related The various parameters of the boot process are referred to as an extendable firmware interface (EFI Variable) or data under the definition of the extendable firmware interface.

Since the drivers of other hardware devices of the computer system have not been initialized during the booting process, the memory for storing the variables of the extendable firmware interface required for the basic input/output system must be Stored in a non-Volatile manner, such as a read-only memory (ROM). Under the condition that the capacity of the read-only memory is limited, when the number of such variables of the extendable firmware interface is increased and more memory space is needed for storage, it will result in storing the basic input/output system. The memory space of the firmware program is reduced and becomes a problem to be solved.

Accordingly, it is an object of the present invention to provide a chassis device that is more resilient to access to variables of the extendable firmware interface.

Therefore, the chassis device of the present invention comprises a chassis manager, a local server, a bus bar, a transmission unit, and a transmission control unit.

The chassis manager includes a first processing unit and a first random access memory electrically connected to the first processing unit. The local server supports an Extensible Firmware Interface (EFI) and includes a second random access memory and a second processing unit electrically connected to the second random access memory.

The transmission unit electrically connects the first processing unit of the chassis manager and the bus bar with a transmission interface. The transmission control unit electrically connects the second processing unit of the local server and the bus bar by using the transmission interface.

When the second processing unit of the local server performs a booting process, the second processing unit reads a specific address of the second random access memory, and when the second processing unit is to read the corresponding When a variable data of the variable of the firmware interface is extended, the second processing unit reads a memory mapped to the first random access memory via the transmission control unit, the bus bar, and the transmission unit Block to get the variable data.

When the second processing unit of the local server performs the booting process, the second processing unit reads the specific address of the second random access memory, and when the second processing unit is to be stored, When the variable data of the variable of the firmware interface is extendable, the second processing unit stores the variable data in the mapping to the first random access memory via the transmission control unit, the bus bar, and the transmission unit. The memory block.

In some implementations, the second random access memory stores an identification code. When the second processing unit is to read or store the variable data of the variable of the extendable firmware interface, the second processing unit transmits a data signal to the bus bar via the transmission control unit, and the data signal includes The identification code of the local server should be the same as the variable of the variable of the extendable firmware interface. When the first processing unit receives the data signal of the bus bar via the transmission unit, the first processing unit determines the corresponding identifier of the first random access memory according to the identification code of the data signal. The memory block is accessed in relation to the variable data.

In some implementations, the variable data includes a Globally Unique Identifier (GUID) number, a variable name, and a trigger value. The chassis manager further includes a storage unit electrically connected to the first processing unit to store a plurality of variable values respectively corresponding to different global unique identifier numbers and different variable names.

When the second processing unit is to read the variable value corresponding to the global unique identifier number and the variable name, the second processing unit sets the trigger value of the data signal to a first logic value.

When the first processing unit receives the data signal of the bus bar, the first processing unit numbers the global unique identifier of the data signal, the variable name, and the trigger value according to the identification code of the data signal. And storing the memory block corresponding to the identification code in the first random access memory. When the first processing unit determines that the trigger value is equal to the first logic value, the first processing unit numbers the global unique identifier corresponding to the memory block in the storage unit and the variable value of the variable name, Storing to the memory block, and transmitting the identification code including the data signal, the global unique identifier number of the memory block, the variable name, and the new data signal of the variable value via the transmission unit To the bus.

When the transmission control unit receives the new data signal of the bus bar, and the identification code of the new data signal matches the identification code of the local server, the transmission control unit transmits the new data signal to the The second processing unit of the local server.

In some implementations, wherein the variable data further comprises a variable value. When the second processing unit is to store the variable value corresponding to the global unique identifier number and the variable name, the second processing unit sets the trigger value of the data signal to be different from the first logical value. Two logical values.

When the first processing unit receives the data signal of the bus bar, the first processing unit further stores the variable value of the data signal into the first random access memory according to the identification code of the data signal. The memory block corresponding to the identification code. When the first processing unit determines that the trigger value is equal to the second logic value, the first processing unit, the identifier of the memory block of the first random access memory, the global unique identifier number, The variable name and the variable value are stored to the storage unit.

In some implementations, the transmission interface is a Low Pin Count Bus Interface (LPCBI), and the bus bar is a low pin count bus (LPC).

In some implementations, the chassis manager further includes a communication module, wherein the communication module is adapted to connect to a remote server via a communication network, the remote server can be the same for the chassis manager The globally unique identifier numbers of the storage units, the variable names, and the variable values are accessed.

In some implementations, the storage unit of the chassis manager is a flash flash drive.

Therefore, another chassis device of the present invention is adapted to connect to a remote server via a communication network, and includes: a chassis manager, a local server, a bus, a transmission unit, and a transmission control unit.

The chassis manager includes a communication module connected to the remote server via the communication network, a first processing unit, and a first random access memory electrically connected to the first processing unit. The local server supports an extendable firmware interface (EFI) and includes a second random access memory and a second processing unit electrically coupled to the second random access memory.

The transmission unit electrically connects the first processing unit of the chassis manager and the bus bar with a transmission interface. The transmission control unit electrically connects the second processing unit of the local server and the bus bar by using the transmission interface.

When the second processing unit of the local server performs a booting process, the second processing unit reads a specific address of the second random access memory, and when the second processing unit is to read a When the variable data of the variable of the firmware interface is extended, the second processing unit reads, by the transmission control unit, the bus bar, and the transmission unit, a memory region mapped to the first random access memory. And the first processing unit reads the variable data pre-stored in the remote server via the communication network and stores the variable data in the memory block of the first random access memory. So that the second processing unit obtains the variable data.

When the second processing unit of the local server performs the booting process, the second processing unit reads the specific address of the second random access memory, and when the second processing unit is to store the When the variable data of the variable of the firmware interface is extended, the second processing unit stores the variable data in the first random access memory via the transmission control unit, the bus bar, and the transmission unit. The memory block, and the first processing unit stores the variable data stored in the memory block by the communication module via the communication network, and stores the variable data in the remote server.

In some implementations, wherein the second processing unit reads the memory block mapped to the first random access memory via the transmission control unit, the bus bar, and the transmission unit, The first processing unit decodes the data mapped to the memory block according to a pre-designed service program, and then reads, by the communication module, the variable data pre-stored in the remote server via the communication network. . When the second processing unit stores the variable data in the memory block mapped to the first random access memory via the transmission control unit, the bus bar, and the transmission unit, the first processing unit According to the pre-designed service program, the data mapped to the memory block is decoded, and then stored by the communication module on the remote server via the communication network.

The effect of the present invention is to store or read the variable of the extendable firmware interface to or from the storage unit by mapping the second random access memory to the first random access memory. The variable of the extendable firmware interface, in addition to the ability of the storage unit to have a greater capacity, allows for greater and better flexibility in accessing the variables of the extendable firmware interface.

Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same reference numerals.

Referring to FIG. 1, a first embodiment of a chassis device of the present invention includes a local server 2, a chassis manager (Chassis Manager) 1, a transmission unit 3, a transmission control unit 4, and a bus bar 6. The transmission unit 3 electrically connects the chassis manager 1 and the bus bar 6 with a transmission interface. The transmission control unit 4 electrically connects the local server 2 and the bus bar 6 with the transmission interface. In addition, it is particularly worth mentioning that the transmission unit 3 and the transmission control unit 4 can utilize a Field Programmable Gate Array (FPGA), a Complex Programmable Logic Device (CPLD), or It is implemented by means of Application-Specific Integrated Circuit (ASIC).

More specifically, the transmission interface is a Low Pin Count Bus Interface (LPCBI), the bus 6 is a low pin count bus (LPC), and the chassis device is a server cabinet ( Server Rack), the local server 2 is a node of the server cabinet. The local server 2 and the cabinet manager are respectively disposed on the second board of the server cabinet, and are respectively inserted on a back board of the server cabinet, and the bus bar 6 is also disposed on the back board. on. It is particularly worth mentioning that the transmission unit 3 and the transmission control unit 4 are respectively disposed on the same board as the chassis manager 1 and the local server 2, or are disposed on the backplane.

The local server 2 supports an extendable firmware interface (EFI) and includes a second random access memory 22 and a second processing unit 21. The second random access memory 22 stores an identification code. The second processing unit 21 is electrically connected to the second random access memory 22 and the transmission control unit 4, and executes a booting process according to a boot signal.

The chassis manager 1 includes a first processing unit 11, a first random access memory 12, a storage unit 13, and a communication module 14. The first processing unit 11 is electrically connected to the transmission unit 3. The first random access memory 12 is electrically connected to the first processing unit 11. The storage unit 13 is electrically connected to the first processing unit 11 and stores a plurality of variable values corresponding to different Globally Unique Identifier (GUID) numbers and different variable names. In this embodiment, the second processing unit 21 belongs to the x86 architecture, that is, the second processing unit 21 includes a processor 211 and a chip set 212, and the first processing unit 11 also belongs to the x86 architecture, but the processor The chipset is integrated into a chip, and the first random access memory 12 and the second random access memory 22 respectively serve as system memory under the x86 architecture. The storage unit 13 is a flash ROM. In other embodiments, the first processing unit 11 may also include another processor and another chip set. The second processing unit 21 may also integrate the processor 211 and the chip set 212 into another chip. The storage unit 13 may also be other storage devices such as a hard disk.

Referring to FIG. 1 and FIG. 2, FIG. 2 is a schematic diagram illustrating the relationship between the first random access memory 12 and the second random access memory 22 when the local server 2 executes the booting process. The first random access memory 12 and the second random access memory 22 have a capacity of 4 GB, and the addresses of the first random access memory 12 and the second random access memory 22 ( Address) is from 0x00000000 to 0xFFFFFFFF, but not limited to this.

When the second processing unit 21 of the local server 2 is executing the booting process, the second processing unit 21 sequentially reads and executes the specific address from the second random access memory 22. The boot code stored in the second random access memory 22, in this embodiment, the specific address is 0xFFFFFFFF, and the boot code has a capacity of 4MB, but not limited thereto. When the second processing unit 21 executes the boot code and reads or stores an EFI Variable of the extendable firmware interface, the second processing unit 21 transmits a data signal via the transmission control unit 4. To the bus 6 . The variable of the extendable firmware interface is, for example, a boot option, a boot order, a user password, a setting value of a transmission interface of a Universal Asynchronous Receiver/Transmitter (UART), The enhanced mode (Turbo Mode) of the processor 211, the setting of the power saving mode, and the like. The data signal includes the identification code corresponding to the local server 2 and the variable data corresponding to the variable of the extendable firmware interface. The variable data includes a globally unique identifier (GUID) number, a variable name, a variable value, and a trigger value.

In particular, when the local server 2 receives the power-on signal, the second random access memory 22 can pass through a low pin count bus interface (LPCBI) or a sequence peripheral interface ( Serial Peripheral Interface Bus; SPI) loads the boot code from a read-only memory (ROM), and the read-only memory can be set in the local server 2, or can be set outside the local server 2 . In addition, in this embodiment, the variable data includes only one global unique identifier number, one variable name, and one variable value corresponding to the variable of one extendable firmware interface, and in other embodiments, the variable data is also A plurality of globally unique identifier numbers, a plurality of variable names, and a plurality of variable values respectively corresponding to variables of the plurality of extensible firmware interfaces may be included.

When the second processing unit 21 is to read the variable of the extendable firmware interface (EFI Variable), that is, the second processing unit 21 is to read the globally unique identifier corresponding to the variable of the extendable firmware interface. When the variable is numbered with the variable name, the second processing unit 21 sets the trigger value of the data signal to a first logic value, such as logic 0, but not limited thereto.

When the first processing unit 11 receives the data signal of the bus bar 6, the first processing unit 11 numbers the global unique identifier of the data signal according to the identification code of the data signal, the variable name. (variable name), and the trigger value trigger is stored in the first random access memory 12 corresponding to the memory block of the identification code. In this embodiment, the memory block is located between the address 0x00005000 to 0x00004000 of the first random access memory 12 as an example. When the first processing unit 11 determines that the trigger value trigger is equal to the first logic value, the first processing unit 11 associates the global unique identifier number GUID# corresponding to the memory block in the storage unit 13 with the variable. The variable value of the variable name is stored in the memory block, and the identification code including the data signal, the global unique identifier number GUID# of the memory block, and the variable name are A new data signal of the variable name) and the variable value value is transmitted to the bus bar 6 via the transmission unit 3.

When the transmission control unit 4 receives the new data signal of the bus bar 6, and the identification code of the new data signal matches the identification code of the local server 2, the transmission control unit 4 adds the new data. The signal is transmitted to the first processing unit 11 of the local server 2, so that the first processing unit 11 can correctly read to obtain the variable (EFI Variable) of the extendable firmware interface.

When the second processing unit 21 is to store the variable (EFI Variable) of the extendable firmware interface, that is, the second processing unit 21 stores the global unique identifier number corresponding to the variable of the extendable firmware interface, When the variable name and the variable value are used, the second processing unit 21 sets the trigger value trigger of the data signal to a second logic value different from the first logic value, for example, logic 1, but not limited thereto.

When the first processing unit 11 receives the data signal of the bus bar 6, the first processing unit 11 numbers the global unique identifier of the data signal according to the identification code of the data signal, the variable name. (variable name), the variable value value, and the trigger value trigger are stored in the first random access memory 12 corresponding to the memory block of the identification code. In this embodiment, the memory block is located between the addresses 0x005000 to 0x004000 of the first random access memory 12 as an example. When the first processing unit 11 determines that the trigger value trigger is equal to the second logic value, the first processing unit 11 the identifier of the memory block of the first random access memory 12, the global unique The identifier number GUID#, the variable name, and the variable value value are stored in the storage unit 13.

Referring to Figures 1 and 3, Figure 3 is a flow chart to re-emphasize the steps associated with the boot process. In step S1, the second processing unit 21 executes the booting process. In step S2, the second processing unit 21 reads or writes (stores) the variable data corresponding to the variable of the extendable firmware interface. In step S3, the second processing unit 21 maps the memory, that is, an address of the second random access memory 22 via the second processing unit 21, the transmission control unit 4, the transmission unit 3, and the first The processing unit 11 maps or decodes to another address of the first random access memory 12, and writes the variable name and the variable value of the variable data. In step S4, the second processing unit 21 writes the trigger value in the mapping memory. In step S5, the first processing unit 11 determines whether the trigger value is equal to the first logic value, and if so, proceeds to step S6, and if not, proceeds to step S7. In step S6, the first processing unit 11 returns the new data signal, so that the second processing unit 21 reads the variable data. In step S7, the first processing unit 11 stores the variable data (write) in the storage unit 13. That is to say, the second random access memory 22 does not actually store the variables of the extendable firmware interfaces, but only uses the manner of mapping to the first random access memory 12. Moreover, since the capacity of the storage unit 13 is much larger than the capacity of the prior art read-only memory, no matter how many extensions need to be read or stored during the execution of the boot code by the second processing unit 21 The firmware interface (EFI Variable) has almost no capacity limitation, which can overcome the problems of the prior art.

Moreover, the communication module 14 of the chassis manager 1 is, for example, a network card, and is adapted to connect to a remote server 9 via a communication network 8. The remote server 9 can access the global unique identifier number, the variable name, and the variable values of the storage unit 13 of the chassis manager 1 to implement remote storage or update. The function of extending the variable of the firmware interface. In addition, in this embodiment, the storage unit 13 of the chassis manager 1 stores the global unique identifier numbers, the variable names, and the variable values for remote storage by the remote server 9. Or update. In other embodiments, the storage unit 13 of the chassis manager 1 may not store the global unique identifier number, the variable name, and the variable values, but is executed by the local server 2 After the booting process, the second random access memory 22 maps the variables of the extendable firmware interface to the first random access memory 12, and the first processing unit 11 follows a pre-designed service. The program decodes the data of the memory block mapped to the first random access memory 12, and transmits the data to the remote server 9 via the communication network 8 through the communication module 14 to Accessing the remote server 9 with respect to the variable data, that is, storing the global unique identifier numbers, the variable names, and the variable values on the remote server 9, or reading the far The globally unique identifier numbers, the variable names, and the variable values stored by the end server 9.

In addition, in the embodiment, the chassis device only includes one local server 2, and in other embodiments, the chassis device may also include multiple local servers 2, and by different The plurality of identification codes respectively correspond to the local server 2, and then read, store, remotely store or remotely update the variables of the extendable firmware interfaces of the local server 2.

In summary, the second random access memory is mapped to the first random access memory, and the variable of the extendable firmware interface is stored to or read by the storage unit. The variables of the extendable firmware interface not only do not need to occupy the space of any non-volatile memory of the local server, but also have greater flexibility to access the variables, and are not expected to be unexpected by the local server. In the event of a crash, the variable data is corrupted or disappeared. Further, it is convenient to remotely manage the variable data by the remote server, and the object of the present invention can be achieved.

However, the above is only the embodiment of the present invention, and the scope of the invention is not limited thereto, and all the equivalent equivalent changes and modifications according to the scope of the patent application and the patent specification of the present invention are still The scope of the invention is covered.

1‧‧‧Chassis Manager
11‧‧‧First Processing Unit
12‧‧‧First random access memory
13‧‧‧ storage unit
14‧‧‧Communication module
2‧‧‧Local server
21‧‧‧Second processing unit
211‧‧‧ processor
212‧‧‧ chipsets
22‧‧‧Second random access memory
3‧‧‧Transmission unit
4‧‧‧Transmission Control Unit
6‧‧‧ Busbar
8‧‧‧Communication network
9‧‧‧Remote Server
GUID# global unique identifier number
Variable name‧‧‧variable name
Value‧‧‧variable value
Trigger‧‧‧trigger value
S1~S7‧‧‧ steps

Other features and advantages of the present invention will be apparent from the embodiments of the present invention, wherein: FIG. 1 is a block diagram illustrating an embodiment of a chassis apparatus of the present invention; FIG. 2 is a schematic diagram illustrating the implementation For example, a relationship between a first random access memory and a second random access memory; and FIG. 3 is a flowchart illustrating a booting process of the embodiment.

1‧‧‧Chassis Manager

11‧‧‧First Processing Unit

12‧‧‧First random access memory

13‧‧‧ storage unit

14‧‧‧Communication module

2‧‧‧Local server

21‧‧‧Second processing unit

211‧‧‧ processor

212‧‧‧ chipsets

22‧‧‧Second random access memory

3‧‧‧Transmission unit

4‧‧‧Transmission Control Unit

6‧‧‧ Busbar

8‧‧‧Communication network

9‧‧‧Remote Server

Claims (9)

A chassis device includes: a chassis manager, including a first processing unit, and a first random access memory electrically connected to the first processing unit; and a local server supporting an extendable firmware interface (Extensible Firmware) Interface (EFI), and includes a second random access memory, and a second processing unit electrically connected to the second random access memory; a bus; a transmission unit electrically connected to the chassis by using a transmission interface The first processing unit of the manager and the bus bar; and a transmission control unit electrically connecting the second processing unit of the local server and the bus bar by using the transmission interface; when the second processing of the local server When the unit performs a booting process, the second processing unit reads a specific address of the second random access memory, and when the second processing unit is to read a variable corresponding to a variable of the extendable firmware interface When the data is changed, the second processing unit reads a memory mapped to the first random access memory via the transmission control unit, the bus bar, and the transmission unit. Blocking, to obtain the variable data, when the second processing unit of the local server performs the booting process, the second processing unit reads the specific address of the second random access memory, and when When the second processing unit is to store the variable data corresponding to the variable of the extendable firmware interface, the second processing unit stores the variable data in the mapping control unit, the bus bar, and the transmitting unit. The memory block of the first random access memory. The chassis device of claim 1, wherein the second random access memory stores an identification code, and when the second processing unit is to read or store the variable data of the variable of the extendable firmware interface, The second processing unit transmits a data signal to the bus bar via the transmission control unit, the data signal includes the identification code corresponding to the local server, and the variable data corresponding to the variable of the extendable firmware interface. When the first processing unit receives the data signal of the bus bar via the transmission unit, the first processing unit, according to the identification code of the data signal, the corresponding identifier of the first random access memory The memory block is accessed in relation to the variable data. The chassis device of claim 2, wherein the variable data includes a Globally Unique Identifier (GUID) number, a variable name, and a trigger value, and the chassis manager further includes an electrical connection. a storage unit of the processing unit to store a plurality of variable values respectively corresponding to different global unique identifier numbers and different variable names, when the second processing unit reads the corresponding global unique identifier number and the variable name When the value is set, the second processing unit sets the trigger value of the data signal to a first logic value. When the first processing unit receives the data signal of the bus bar, the first processing unit is configured according to the data signal. The identification code stores the global unique identifier number, the variable name, and the trigger value of the data signal to the memory block corresponding to the identification code in the first random access memory, when the first When the processing unit determines that the trigger value is equal to the first logic value, the first processing unit selects the global unique corresponding memory block in the storage unit And the identifier number and the variable value of the variable name are stored in the memory block, and the identification code including the data signal, the global unique identifier number of the memory block, the variable name, and The new data signal of the variable value is transmitted to the bus bar via the transmission unit, when the transmission control unit receives the new data signal of the bus bar, and the identification code of the new data signal and the identification of the local server When the code matches, the transmission control unit transmits the new data signal to the second processing unit of the local server. The chassis device of claim 3, wherein the variable data further comprises a variable value, and when the second processing unit is to store the variable value corresponding to the global unique identifier number and the variable name, the second processing The unit sets the trigger value of the data signal to a second logic value different from the first logic value. When the first processing unit receives the data signal of the bus bar, the first processing unit is configured according to the data. The identification code of the signal further stores the variable value of the data signal to the memory block corresponding to the identification code in the first random access memory, when the first processing unit determines that the trigger value is equal to the second And the first processing unit stores the identification code of the memory block of the first random access memory, the global unique identifier number, the variable name, and the variable value to the storage unit. The chassis device of claim 4, wherein the transmission interface is a Low Pin Count Bus Interface (LPCBI), and the bus bar is a low pin count bus (LPC). The chassis device of claim 5, wherein the chassis manager further comprises a communication module, wherein the communication module is adapted to connect to a remote server via a communication network, and the remote server can manage the chassis The globally unique identifier numbers, the variable names, and the variable values of the storage unit of the device are accessed. The chassis device of claim 6, wherein the storage unit of the chassis manager is a flash flash drive. A chassis device, configured to connect to a remote server via a communication network, and comprising: a chassis manager, including a communication module, connected to the remote server, a first processing unit, and a communication network a first random access memory electrically connected to the first processing unit; a local server supporting an extendable firmware interface (EFI), and including a second random access memory, and a second processing unit, Connecting the second random access memory; a bus; a transmission unit electrically connecting the first processing unit and the bus bar of the chassis manager by using a transmission interface; and a transmission control unit, using the transmission interface Connecting the second processing unit of the local server and the bus bar; when the second processing unit of the local server is performing a booting process, the second processing unit reads the second random access memory a specific address, and when the second processing unit is to read a variable data of a variable of the extendable firmware interface, the second processing unit via the transmission control unit, the confluence The memory unit is read and mapped to a memory block of the first random access memory, and the first processing unit is pre-stored at the remote end by the communication module via the communication network. The variable data of the server is stored in the memory block of the first random access memory, so that the second processing unit obtains the variable data, when the second processing unit of the local server is executing the When the booting process is performed, the second processing unit reads the specific address of the second random access memory, and when the second processing unit is to store the variable data of the variable of the extendable firmware interface, the first The processing unit stores the variable data in the memory block mapped to the first random access memory via the transmission control unit, the bus bar, and the transmission unit, and the first processing unit uses the The communication module transmits the variable data stored in the memory block to the remote server via the communication network. The chassis device of claim 8, wherein the second processing unit reads the memory region mapped to the first random access memory via the transmission control unit, the bus bar, and the transmission unit Blocking, the first processing unit decodes the data mapped to the memory block according to a pre-designed service program, and then reads, by the communication module, the data pre-stored on the remote server via the communication network. The variable data, and when the second processing unit stores the variable data in the memory block mapped to the first random access memory via the transmission control unit, the bus bar, and the transmission unit, The first processing unit decodes the data mapped to the memory block according to the pre-designed service program, and then stores the data on the remote server via the communication network.